May 2018 - U-Boot

[U-Boot] [PATCH] drivers: spi: migrate cf_spi to DM
by Angelo Dureghello 02 May '18

02 May '18

This patch adds DM support to cf_spi.c. To be able to build spi driver with DM support, a new config option has been introdiced (DM_NO_DT) since m68k architecture does not support fdt. Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- arch/Kconfig | 1 + drivers/core/Kconfig | 4 + drivers/spi/cf_spi.c | 408 ++++++++++++++++++++------------ drivers/spi/spi-uclass.c | 12 +- include/dm/platform_data/spi_coldfire.h | 22 ++ 5 files changed, 291 insertions(+), 156 deletions(-) create mode 100644 include/dm/platform_data/spi_coldfire.h diff --git a/arch/Kconfig b/arch/Kconfig index e599e7a39c..735669921b 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -28,6 +28,7 @@ config M68K select HAVE_PRIVATE_LIBGCC select SYS_BOOT_GET_CMDLINE select SYS_BOOT_GET_KBD + select DM_NO_OF config MICROBLAZE bool "MicroBlaze architecture" diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index e8ba20ca82..47960a8a6a 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -244,4 +244,8 @@ config DM_DEV_READ_INLINE bool default y if !OF_LIVE +config DM_NO_OF + bool + default n + endmenu diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 7be9427781..2c0298eeeb 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -6,16 +6,23 @@ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) * + * Support for device model: + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <dm/platform_data/spi_coldfire.h> #include <spi.h> #include <malloc.h> #include <asm/immap.h> -struct cf_spi_slave { +struct coldfire_spi_priv { +#ifndef CONFIG_DM_SPI struct spi_slave slave; +#endif uint baudrate; int charbit; }; @@ -39,12 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000 -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) -{ - return container_of(slave, struct cf_spi_slave, slave); -} - -static void cfspi_init(void) +static void __spi_init(void) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -82,7 +84,123 @@ static void cfspi_init(void) #endif } -static void cfspi_tx(u32 ctrl, u16 data) +int __spi_set_speed(struct coldfire_spi_priv *cfspi, uint bus, uint mode) +{ + /* + * bit definition for mode: + * bit 31 - 28: Transfer size 3 to 16 bits + * 27 - 26: PCS to SCK delay prescaler + * 25 - 24: After SCK delay prescaler + * 23 - 22: Delay after transfer prescaler + * 21 : Allow overwrite for bit 31-22 and bit 20-8 + * 20 : Double baud rate + * 19 - 16: PCS to SCK delay scaler + * 15 - 12: After SCK delay scaler + * 11 - 8: Delay after transfer scaler + * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST + */ + volatile dspi_t *dspi = (dspi_t *)MMAP_DSPI; + int prescaler[] = { 2, 3, 5, 7 }; + int scaler[] = { + 2, 4, 6, 8, + 16, 32, 64, 128, + 256, 512, 1024, 2048, + 4096, 8192, 16384, 32768 + }; + int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; + int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed; + u32 bus_setup = 0; + + tmp = (prescaler[3] * scaler[15]); + /* Maximum and minimum baudrate it can handle */ + if ((cfspi->baudrate > (gd->bus_clk >> 1)) || + (cfspi->baudrate < (gd->bus_clk / tmp))) { + printf("Exceed baudrate limitation: Max %d - Min %d\n", + (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp)); + return -1; + } + + /* Activate Double Baud when it exceed 1/4 the bus clk */ + if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) || + (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { + bus_setup |= DSPI_CTAR_DBR; + dbr = 1; + } + + /* Overwrite default value set in platform configuration file */ + if (mode & SPI_MODE_MOD) { + /* + * Check to see if it is enabled by default in platform + * config, or manual setting passed by mode parameter + */ + if (mode & SPI_DBLRATE) { + bus_setup |= DSPI_CTAR_DBR; + dbr = 1; + } + } + + pbrcnt = sizeof(prescaler) / sizeof(int); + brcnt = sizeof(scaler) / sizeof(int); + + /* baudrate calculation - to closer value, may not be exact match */ + for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) { + baud_speed = gd->bus_clk / prescaler[i]; + for (j = 0; j < brcnt; j++) { + tmp = (baud_speed / scaler[j]) * (1 + dbr); + + if (tmp > cfspi->baudrate) + diff = tmp - cfspi->baudrate; + else + diff = cfspi->baudrate - tmp; + + if (diff < bestmatch) { + bestmatch = diff; + best_i = i; + best_j = j; + } + } + } + bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); + dspi->ctar[bus] |= bus_setup; + + return 0; +} + +static int __spi_set_mode(struct coldfire_spi_priv *cfspi, uint bus, uint mode) +{ + volatile dspi_t *dspi = (dspi_t *)MMAP_DSPI; + u32 bus_setup = 0; + + if (mode & SPI_CPOL) + bus_setup |= DSPI_CTAR_CPOL; + if (mode & SPI_CPHA) + bus_setup |= DSPI_CTAR_CPHA; + if (mode & SPI_LSB_FIRST) + bus_setup |= DSPI_CTAR_LSBFE; + + /* Overwrite default value set in platform configuration file */ + if (mode & SPI_MODE_MOD) { + if ((mode & 0xF0000000) == 0) + bus_setup |= + dspi->ctar[bus] & 0x78000000; + else + bus_setup |= ((mode & 0xF0000000) >> 1); + + bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */ + bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */ + } else { + bus_setup |= (dspi->ctar[bus] & 0x78FCFFF0); + } + + cfspi->charbit = + ((dspi->ctar[bus] & 0x78000000) == 0x78000000) ? 16 : 8; + + dspi->ctar[bus] |= bus_setup; + + return 0; +} + +static void __cfspi_tx(u32 ctrl, u16 data) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -91,7 +209,7 @@ static void cfspi_tx(u32 ctrl, u16 data) dspi->tfr = (ctrl | data); } -static u16 cfspi_rx(void) +static u16 __cfspi_rx(void) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -100,16 +218,15 @@ static u16 cfspi_rx(void) return (dspi->rfr & 0xFFFF); } -static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, - void *din, ulong flags) +static int __spi_xfer(struct coldfire_spi_priv *cfspi, uint cs, uint bitlen, + const void *dout, void *din, ulong flags) { - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); u16 *spi_rd16 = NULL, *spi_wr16 = NULL; u8 *spi_rd = NULL, *spi_wr = NULL; static u32 ctrl = 0; uint len = bitlen >> 3; - if (cfslave->charbit == 16) { + if (cfspi->charbit == 16) { bitlen >>= 1; spi_wr16 = (u16 *) dout; spi_rd16 = (u16 *) din; @@ -121,25 +238,25 @@ static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN) ctrl |= DSPI_TFR_CONT; - ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16); + ctrl = (ctrl & 0xFF000000) | ((1 << cs) << 16); if (len > 1) { int tmp_len = len - 1; while (tmp_len--) { if (dout != NULL) { - if (cfslave->charbit == 16) - cfspi_tx(ctrl, *spi_wr16++); + if (cfspi->charbit == 16) + __cfspi_tx(ctrl, *spi_wr16++); else - cfspi_tx(ctrl, *spi_wr++); - cfspi_rx(); + __cfspi_tx(ctrl, *spi_wr++); + __cfspi_rx(); } if (din != NULL) { - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - if (cfslave->charbit == 16) - *spi_rd16++ = cfspi_rx(); + __cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); + if (cfspi->charbit == 16) + *spi_rd16++ = __cfspi_rx(); else - *spi_rd++ = cfspi_rx(); + *spi_rd++ = __cfspi_rx(); } } @@ -151,135 +268,60 @@ static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, if (len) { if (dout != NULL) { - if (cfslave->charbit == 16) - cfspi_tx(ctrl, *spi_wr16); + if (cfspi->charbit == 16) + __cfspi_tx(ctrl, *spi_wr16); else - cfspi_tx(ctrl, *spi_wr); - cfspi_rx(); + __cfspi_tx(ctrl, *spi_wr); + __cfspi_rx(); } if (din != NULL) { - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - if (cfslave->charbit == 16) - *spi_rd16 = cfspi_rx(); + __cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); + if (cfspi->charbit == 16) + *spi_rd16 = __cfspi_rx(); else - *spi_rd = cfspi_rx(); + *spi_rd = __cfspi_rx(); } } else { /* dummy read */ - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - cfspi_rx(); + __cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); + __cfspi_rx(); } return 0; } -static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, - uint mode) -{ - /* - * bit definition for mode: - * bit 31 - 28: Transfer size 3 to 16 bits - * 27 - 26: PCS to SCK delay prescaler - * 25 - 24: After SCK delay prescaler - * 23 - 22: Delay after transfer prescaler - * 21 : Allow overwrite for bit 31-22 and bit 20-8 - * 20 : Double baud rate - * 19 - 16: PCS to SCK delay scaler - * 15 - 12: After SCK delay scaler - * 11 - 8: Delay after transfer scaler - * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST - */ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - int prescaler[] = { 2, 3, 5, 7 }; - int scaler[] = { - 2, 4, 6, 8, - 16, 32, 64, 128, - 256, 512, 1024, 2048, - 4096, 8192, 16384, 32768 - }; - int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; - int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed; - u32 bus_setup = 0; - - tmp = (prescaler[3] * scaler[15]); - /* Maximum and minimum baudrate it can handle */ - if ((cfslave->baudrate > (gd->bus_clk >> 1)) || - (cfslave->baudrate < (gd->bus_clk / tmp))) { - printf("Exceed baudrate limitation: Max %d - Min %d\n", - (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp)); - return NULL; - } +#ifndef CONFIG_DM_SPI - /* Activate Double Baud when it exceed 1/4 the bus clk */ - if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) || - (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { - bus_setup |= DSPI_CTAR_DBR; - dbr = 1; - } - - if (mode & SPI_CPOL) - bus_setup |= DSPI_CTAR_CPOL; - if (mode & SPI_CPHA) - bus_setup |= DSPI_CTAR_CPHA; - if (mode & SPI_LSB_FIRST) - bus_setup |= DSPI_CTAR_LSBFE; - - /* Overwrite default value set in platform configuration file */ - if (mode & SPI_MODE_MOD) { - - if ((mode & 0xF0000000) == 0) - bus_setup |= - dspi->ctar[cfslave->slave.bus] & 0x78000000; - else - bus_setup |= ((mode & 0xF0000000) >> 1); +static inline struct coldfire_spi_priv *to_coldfire_spi_slave + (struct spi_slave *slave) +{ + return container_of(slave, struct coldfire_spi_priv, slave); +} - /* - * Check to see if it is enabled by default in platform - * config, or manual setting passed by mode parameter - */ - if (mode & SPI_DBLRATE) { - bus_setup |= DSPI_CTAR_DBR; - dbr = 1; - } - bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */ - bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */ - } else - bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0); +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct coldfire_spi_priv *cfspi; - cfslave->charbit = - ((dspi->ctar[cfslave->slave.bus] & 0x78000000) == - 0x78000000) ? 16 : 8; + if (!spi_cs_is_valid(bus, cs)) + return NULL; - pbrcnt = sizeof(prescaler) / sizeof(int); - brcnt = sizeof(scaler) / sizeof(int); + cfspi = spi_alloc_slave(struct coldfire_spi_priv, bus, cs); + if (!cfspi) + return NULL; - /* baudrate calculation - to closer value, may not be exact match */ - for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) { - baud_speed = gd->bus_clk / prescaler[i]; - for (j = 0; j < brcnt; j++) { - tmp = (baud_speed / scaler[j]) * (1 + dbr); + cfspi->baudrate = max_hz; - if (tmp > cfslave->baudrate) - diff = tmp - cfslave->baudrate; - else - diff = cfslave->baudrate - tmp; + if (__spi_set_speed(cfspi, bus, mode)) + return NULL; - if (diff < bestmatch) { - bestmatch = diff; - best_i = i; - best_j = j; - } - } - } - bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); - dspi->ctar[cfslave->slave.bus] = bus_setup; + if (__spi_set_mode(cfspi, bus, mode)) + return NULL; - return &cfslave->slave; + return &cfspi->slave; } -#endif /* CONFIG_CF_DSPI */ -#ifdef CONFIG_CMD_SPI int spi_cs_is_valid(unsigned int bus, unsigned int cs) { if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) @@ -298,32 +340,14 @@ void spi_init_r(void) void spi_init(void) { - cfspi_init(); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct cf_spi_slave *cfslave; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs); - if (!cfslave) - return NULL; - - cfslave->baudrate = max_hz; - - /* specific setup */ - return cfspi_setup_slave(cfslave, mode); + __spi_init(); } void spi_free_slave(struct spi_slave *slave) { - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); + struct coldfire_spi_priv *cfspi = to_coldfire_spi_slave(slave); - free(cfslave); + free(cfspi); } int spi_claim_bus(struct spi_slave *slave) @@ -339,6 +363,88 @@ void spi_release_bus(struct spi_slave *slave) int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - return cfspi_xfer(slave, bitlen, dout, din, flags); + struct coldfire_spi_priv *cfspi = to_coldfire_spi_slave(slave); + + return __spi_xfer(cfspi, slave->cs, bitlen, dout, din, flags); } -#endif /* CONFIG_CMD_SPI */ + +#else + +void spi_init(void) +{ + /* arch-related port configuration */ + __spi_init(); +} + +static int coldfire_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + + return cfspi_claim_bus(bus->seq, plat->cs); +} + +static int coldfire_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + + cfspi_release_bus(bus->seq, plat->cs); + + return 0; +} + +static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, + unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + + return __spi_xfer(cfspi, plat->cs, bitlen, dout, din, flags); +} + +static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz) +{ + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + + return __spi_set_speed(cfspi, bus->seq, plat->mode); +} + +static int coldfire_spi_set_mode(struct udevice *bus, uint mode) +{ + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + + return __spi_set_mode(cfspi, bus->seq, plat->mode); +} + +static int coldfire_spi_probe(struct udevice *bus) +{ + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + + cfspi->baudrate = plat->speed_hz; + + return 0; +} + +static const struct dm_spi_ops coldfire_spi_ops = { + .claim_bus = coldfire_spi_claim_bus, + .release_bus = coldfire_spi_release_bus, + .xfer = coldfire_spi_xfer, + .set_speed = coldfire_spi_set_speed, + .set_mode = coldfire_spi_set_mode, +}; + +U_BOOT_DRIVER(coldfire_spi) = { + .name = "spi_coldfire", + .id = UCLASS_SPI, + .probe = coldfire_spi_probe, + .ops = &coldfire_spi_ops, + .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv), +}; +#endif /* CONFIG_DM_SPI */ +#endif /* CONFIG_CF_DSPI */ diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 15d90a54a1..908be1d4cf 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -107,7 +107,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, return dm_spi_xfer(slave->dev, bitlen, dout, din, flags); } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if !CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(CONFIG_DM_NO_OF) static int spi_child_post_bind(struct udevice *dev) { struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); @@ -121,7 +121,7 @@ static int spi_child_post_bind(struct udevice *dev) static int spi_post_probe(struct udevice *bus) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if !CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(CONFIG_DM_NO_OF) struct dm_spi_bus *spi = dev_get_uclass_priv(bus); spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); @@ -274,7 +274,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, bool created = false; int ret; -#if CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_PLATDATA) || defined(CONFIG_DM_NO_OF) ret = uclass_first_device_err(UCLASS_SPI, &bus); #else ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus); @@ -283,6 +283,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, printf("Invalid bus %d (err=%d)\n", busnum, ret); return ret; } + ret = spi_find_chip_select(bus, cs, &dev); /* @@ -321,6 +322,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, } plat = dev_get_parent_platdata(dev); + if (!speed) { speed = plat->max_hz; mode = plat->mode; @@ -427,7 +429,7 @@ UCLASS_DRIVER(spi) = { .id = UCLASS_SPI, .name = "spi", .flags = DM_UC_FLAG_SEQ_ALIAS, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if !CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(CONFIG_DM_NO_OF) .post_bind = dm_scan_fdt_dev, #endif .post_probe = spi_post_probe, @@ -436,7 +438,7 @@ UCLASS_DRIVER(spi) = { .per_child_auto_alloc_size = sizeof(struct spi_slave), .per_child_platdata_auto_alloc_size = sizeof(struct dm_spi_slave_platdata), -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if !CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(CONFIG_DM_NO_OF) .child_post_bind = spi_child_post_bind, #endif }; diff --git a/include/dm/platform_data/spi_coldfire.h b/include/dm/platform_data/spi_coldfire.h new file mode 100644 index 0000000000..44094b428d --- /dev/null +++ b/include/dm/platform_data/spi_coldfire.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2015 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __spi_coldfire_h +#define __spi_coldfire_h + +/* + * struct coldfire_spi_platdata - information about a coldfire spi module + * + * @speed_hz: SPI speed + */ +struct coldfire_spi_platdata { + uint speed_hz; + uint mode; + uint cs; +}; + +#endif /* __spi_coldfire_h */ + -- 2.15.1

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[U-Boot] [PATCH] Make cmd_get_data_size() a dependency of setexpr
by qlb1234 02 May '18

02 May '18

This commit broke the command setexpr. http://git.denx.de/?p=u-boot.git;a=commit;h=6f62d7c4f7a2242a76e19b09dccca6f… setexpr uses cmd_get_data_size(). If none of I2C, ITEST or PCI is chosen, setexpr will fail to be built.

2 2

[U-Boot] [PATCH] clk: renesas: Drop USB extal from the R8A7792 clock driver
by Marek Vasut 02 May '18

02 May '18

The R8A7792 does not have the USB extal, so drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c index 4ba18b18be..46dd3c9c91 100644 --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c @@ -214,10 +214,8 @@ static const struct cpg_mssr_info r8a7792_cpg_mssr_info = { .mstp_table = r8a7792_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table), .reset_node = "renesas,r8a7792-rst", - .extal_usb_node = "usb_extal", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, - .clk_extal_usb_id = CLK_USB_EXTAL, .pll0_div = 2, .get_pll_config = r8a7792_get_pll_config, }; -- 2.16.2

1 0

[U-Boot] [RFC PATCH] rockchip: asus c201 support
by Marty E. Plummer 02 May '18

02 May '18

From: "Marty E. Plummer" <hanetzer(a)protonmail.com> I realize this patch is not up to standards for the sake of mainlining right now, but I'm mostly interested in getting some feedback on how to make it work before getting into the nicities of mainline inclusion. As of right now the bulk of this is the rk3288-veyron-speedy.dts file, which I assume has a similar enough boot system to the jerry and minnie. If the resultant u-boot-spl.bin and u-boot-dtb.img are prepared according to the instructions in doc/README.rockchip and then flashed to the c201's spi memory I get very little in the way of result; the most I/O that to be seen is the board reacts to the power switch (led on, led off). I can not seem to get it to output the u-boot console to the built-in screen, and currently do not have a mini-hdmi cable to see if that is working or not (one is ordered, arrives thursday). Can't find a location to purchase a servo board for better debugging possibilities. I was hoping someone on this mailing list could assist me in getting this to work; once a working setup is figured I'll do proper patchset for mainline inclusion. Regards, Marty --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-veyron-speedy.dts | 203 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +- arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++ board/google/veyron/Kconfig | 16 +++ configs/chromebook_speedy_defconfig | 92 ++++++++++++++ drivers/mtd/spi/spi_flash_ids.c | 1 + 7 files changed, 326 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts create mode 100644 configs/chromebook_speedy_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7c062f0cad..c8630889dc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-jerry.dtb \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ + rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb \ rk3328-evb.dtb \ rk3368-lion.dtb \ diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts new file mode 100644 index 0000000000..51e155d141 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-speedy.dts @@ -0,0 +1,203 @@ +/* + * Google Veyron Speedy Rev 1+ board device tree source + * + * Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3288-veyron-chromebook.dtsi" +#include "cros-ec-sbs.dtsi" + +/ { + model = "Google Jerry"; + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", + "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", + "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", + "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", + "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; + + /* chosen { */ + /* stdout-path = &uart1; */ + /* }; */ + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x1>; + rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>; +}; + +&gpio_keys { + power { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + }; +}; + +&backlight { + power-supply = <&backlight_regulator>; +}; + +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_alert1 { + temperature = <70000>; +}; + +&panel { + power-supply = <&panel_regulator>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; +}; + +&sdmmc { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; + disable-wp; +}; + +&vcc_5v { + enable-active-high; + /* gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; */ + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&edp { + /* pinctrl-names = "default"; */ + /* pinctrl-0 = <&edp_hpd>; */ + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + + force-hpd; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp_hpd { + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; + }; + }; + + emmc { + /* Make sure eMMC is not in reset */ + emmc_deassert_reset: emmc-deassert-reset { + rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +/* &i2c4 { */ +/* status = "okay"; */ + +/* pinctrl-names = "default"; */ +/* pinctrl-0 = <&i2c4_xfer>; */ + +/* trackpad@15 { */ +/* compatible = "elan,i2c_touchpad"; */ +/* interrupt-parent = <&gpio7>; */ +/* interrupts = <3 IRQ_TYPE_EDGE_FALLING>; */ +/* /* */ +/* * Remove the inherited pinctrl settings to avoid clashing */ +/* * with bus-wide ones. */ +/* *1/ */ +/* /delete-property/pinctrl-names; */ +/* /delete-property/pinctrl-0; */ +/* reg = <0x15>; */ +/* vcc-supply = <&vcc33_io>; */ +/* wakeup-source; */ +/* }; */ +/* }; */ diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 6b7bf85d8d..5b76114d9b 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -69,7 +69,8 @@ u32 spl_boot_device(void) fallback: #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ + defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) return BOOT_DEVICE_SPI; #endif return BOOT_DEVICE_MMC1; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 4ad2940069..04377f9ea8 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -30,6 +30,17 @@ config TARGET_CHROMEBOOK_MINNIE functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of internal MMC. The product name is ASUS Chromebook Flip. +config TARGET_CHROMEBOOK_SPEEDY + bool "Google/Rockchip Veyron-Speedy Chromebook" + select BOARD_LATE_INIT + help + Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports, + micro HDMI, an 11.6 inch display, micro-SD card, + HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS + EC (Cortex-M3) to provide access to the keyboard and battery + functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC. + The product name is Asus Chromebook C201PA. + config TARGET_EVB_RK3288 bool "Evb-RK3288" select BOARD_LATE_INIT diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig index 770e9aad28..7f55d78dac 100644 --- a/board/google/veyron/Kconfig +++ b/board/google/veyron/Kconfig @@ -45,3 +45,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y endif + +if TARGET_CHROMEBOOK_SPEEDY + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig new file mode 100644 index 0000000000..9626be9743 --- /dev/null +++ b/configs/chromebook_speedy_defconfig @@ -0,0 +1,92 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_TARGET_CHROMEBOOK_SPEEDY=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_SILENT_CONSOLE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_ROCKCHIP_RK3288=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK8XX=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Rockchip" +CONFIG_G_DNL_VENDOR_NUM=0x2207 +CONFIG_G_DNL_PRODUCT_NUM=0x320a +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index 13f64e773f..cbfd8b7636 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -63,6 +63,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ + {"gd25q32b", INFO(0xc84016, 0x0, 64 * 1024, 64, SECT_4K) }, {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, #endif -- 2.14.2

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[U-Boot] [PATCH] armv8: ls1088a: Enable USB in ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
by Ran Wang 02 May '18

02 May '18

Signed-off-by: Ran Wang <ran.wang_1(a)nxp.com> --- configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 43472ac..1cbff34 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -48,3 +48,10 @@ CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_STORAGE=y -- 2.7.4

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[U-Boot] [PATCH] [U-boot] net/phy/cortina: Add support for CS4223 PHY
by Vicentiu Galanopulo 02 May '18

02 May '18

Add support for Cortina CS4223 10G PHY - As per the CS4223 specs, an EEPROM module is connected to the PHY. At startup the PHY reads the firmware line and tries to load the firmware into the internal memory. - This driver reads the EEPROM status and checks if firmware has been loaded Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo(a)nxp.com> --- drivers/net/phy/cortina.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++- include/cortina.h | 4 ++++ include/phy.h | 1 + 3 files changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index 9cb3a52..cb6dc56 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -285,6 +285,38 @@ int cs4340_startup(struct phy_device *phydev) return 0; } +int cs4223_phy_init(struct phy_device *phydev) +{ + int reg_value; + + reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS); + if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) { + printf("%s CS4223 Firmware not present in EERPOM\n", __func__); + return -1; + } + + return 0; +} + +int cs4223_config(struct phy_device *phydev) +{ + return cs4223_phy_init(phydev); +} + +int cs4223_probe(struct phy_device *phydev) +{ + phydev->flags = PHY_FLAG_BROKEN_RESET; + return 0; +} + +int cs4223_startup(struct phy_device *phydev) +{ + phydev->link = 1; + phydev->speed = SPEED_10000; + phydev->duplex = DUPLEX_FULL; + return 0; +} + struct phy_driver cs4340_driver = { .name = "Cortina CS4315/CS4340", .uid = PHY_UID_CS4340, @@ -299,9 +331,23 @@ struct phy_driver cs4340_driver = { .shutdown = &gen10g_shutdown, }; +struct phy_driver cs4223_driver = { + .name = "Cortina CS4223", + .uid = PHY_UID_CS4223, + .mask = 0x0ffff00f, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | + MDIO_DEVS_AN), + .config = &cs4223_config, + .probe = &cs4223_probe, + .startup = &cs4223_startup, + .shutdown = &gen10g_shutdown, +}; + int phy_cortina_init(void) { phy_register(&cs4340_driver); + phy_register(&cs4223_driver); return 0; } @@ -320,7 +366,7 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) return -EIO; *phy_id |= (phy_reg & 0xffff); - if (*phy_id == PHY_UID_CS4340) + if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223)) return 0; /* diff --git a/include/cortina.h b/include/cortina.h index 6cadd28..b64cb44 100644 --- a/include/cortina.h +++ b/include/cortina.h @@ -65,6 +65,10 @@ #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427 #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428 +/* Cortina CS4223 */ +#define CS4223_EEPROM_STATUS 0x5001 +#define CS4223_EEPROM_FIRMWARE_LOADDONE 0x1 + #define mseq_edc_bist_done (0x1<<0) #define mseq_edc_bist_fail (0x1<<8) diff --git a/include/phy.h b/include/phy.h index 0543ec1..2239317 100644 --- a/include/phy.h +++ b/include/phy.h @@ -315,6 +315,7 @@ static inline bool phy_interface_is_sgmii(struct phy_device *phydev) /* PHY UIDs for various PHYs that are referenced in external code */ #define PHY_UID_CS4340 0x13e51002 +#define PHY_UID_CS4223 0x03e57003 #define PHY_UID_TN2020 0x00a19410 #endif -- 1.9.3

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[U-Boot] U-Boot Hole in Verified Boot
by Larry.Gass＠microchip.com 01 May '18

01 May '18

This is my first post to the U-Boot mailing list so if I'm doing it wrong I apologize in advance and would welcome feedback. I was able to bypass the SHA+RSA check of an image by performing a "fdt checksign" followed by a load of an unsigned image, even though I have 'required="conf"' in my control FDT. Below, I have 2 images. linuxnosec.itb is not signed. linux.itb IS signed correctly. How do I report the bug? Thanks, Larry ------------------------------------------------------------------------------------------------ Good behavior: => fatload mmc 1:1 0x20000000 linuxnosec.itb 4989282 bytes read in 331 ms (14.4 MiB/s) => bootm 0x20000000 ## Loading kernel from FIT Image at 20000000 ... Using 'conf@1' configuration Verifying Hash Integrity ... sha256,rsa4096:samkey- Failed to verify required signature 'key-samkey' Bad Data Hash ERROR: can't get kernel image! => ------------------------------------------------------------------------------------------------- How to bypass the signature check: => fatload mmc 1:1 0x20000000 linux.itb 4975090 bytes read in 330 ms (14.4 MiB/s) => bdinfo arch_number = 0x00000000 boot_params = 0x20000100 DRAM bank = 0x00000000 -> start = 0x20000000 -> size = 0x20000000 baudrate = 115200 bps TLB addr = 0x3FFF0000 relocaddr = 0x3FD58000 reloc off = 0x18E58000 irq_sp = 0x3F952FB0 sp start = 0x3F952FA0 Early malloc usage: 14f0 / 2000 fdt_blob = 3f952fc8 => fdt addr 0x3f952fc8 => fdt check 0x20000000 => fatload mmc 1:1 0x20000000 linuxnosec.itb 4989282 bytes read in 332 ms (14.3 MiB/s) => bootm 0x20000000 ## Loading kernel from FIT Image at 20000000 ... Using 'conf@1' configuration Verifying Hash Integrity ... OK Trying 'kernel@1' kernel subimage Description: unavailable Type: Kernel Image Compression: uncompressed Data Start: 0x200000c4 Data Size: 4937752 Bytes = 4.7 MiB Architecture: ARM OS: Linux Load Address: 0x21000000 Entry Point: 0x21000000 Hash algo: sha256 Hash value: a6fa3b9d6b8ec4e302130b56a95dfdbcb5845980a6cd8fbf7de1f21dafaa3229 Verifying Hash Integrity ... sha256+ OK ## Loading fdt from FIT Image at 20000000 ... Using 'conf@1' configuration Trying 'fdt@1' fdt subimage Description: unavailable Type: Flat Device Tree Compression: uncompressed Data Start: 0x204b59b4 Data Size: 33480 Bytes = 32.7 KiB Architecture: ARM Hash algo: sha256 Hash value: 4e338db79f27d05fc666aaffce73c5e03562562da7b59913eec2b374aaef4b07 Verifying Hash Integrity ... sha256+ OK Booting using the fdt blob at 0x204b59b4 Loading Kernel Image ... OK Loading Device Tree to 3f946000, end 3f9512c7 ... OK Starting kernel ...

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[U-Boot] [PATCH v10 0/3] Why netboot:
by DH＠synoia.com 01 May '18

01 May '18

From: Duncan Hare <DuncanCHare(a)yahoo.com> Central management, including logs and change control, coupled with with enhanced security and unauthorized change detection and remediation by exposing a small attack surface. Why TCP: Currently file transfer are done using tftp or NFS both over udp. This requires a request to be sent from client (u-boot) to the boot server. For a 4 Mbyte kernel, with a 1k block size this requires 4,000 request for a block. Using a large block size, one greater than the Ethernet maximum frame size limitation, would require fragmentation, which u-boot supports. However missing fragment recovery requires timeout detection and re-transmission requests for missing fragments. UDP is ideally suited to fast single packet exchanges, inquiry/response, for example dns, becuse of the lack of connection overhead. UDP as a file transport mechanism is slow, even in low latency networks, because file transfer with udp requires poll/response mechanism to provide transfer integrity. In networks with large latency, for example: the internet, UDP is even slower. What is a 30 second transfer on a local boot server and LAN increase to over 3 minutes, because of all the requests/response traffic. This was anticipated in the evolution of the IP protocols and TCP was developed and then enhanced for high latency high bandwidth networks. The current standard is TCP with selective acknowledgment. In our testing we have reduce kernel transmission time to around 0.4 seconds for a 4Mbyte kernel, with a 100 Mbps downlink. Why http and wget: HTTP is the most efficient file retrieval protocol in common use. The client send a single request, after TCP connection, to receive a file of any length. WGET is the application which implements http file transfer outside browsers as a file transfer protocol. Versions of wget exists on many operating systems. Changes in v10: Initial changes for adding TCP Duncan Hare (3): Adding TCP and wget into u-boot Adding TCP Adding wget cmd/Kconfig | 5 + cmd/net.c | 13 + include/net.h | 33 ++- include/net/tcp.h | 218 ++++++++++++++++ include/net/wget.h | 17 ++ net/Kconfig | 10 + net/Makefile | 3 +- net/net.c | 89 +++++-- net/ping.c | 9 +- net/tcp.c | 749 +++++++++++++++++++++++++++++++++++++++++++++++++++++ net/wget.c | 420 ++++++++++++++++++++++++++++++ 11 files changed, 1532 insertions(+), 34 deletions(-) create mode 100644 include/net/tcp.h create mode 100644 include/net/wget.h create mode 100644 net/tcp.c create mode 100644 net/wget.c -- 2.11.0

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[U-Boot] [PATCH] MAINTAINERS: Switch to Alison's nxp.com address
by Fabio Estevam 01 May '18

01 May '18

From: Fabio Estevam <fabio.estevam(a)nxp.com> freescale.com domain is no longer reachable, so switch to Alison's nxp.com domain instead. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 9f653a0..60d4adf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -307,7 +307,7 @@ F: drivers/mtd/cfi_flash.c F: drivers/mtd/jedec_flash.c COLDFIRE -M: Huan Wang <alison.wang(a)freescale.com> +M: Huan Wang <alison.wang(a)nxp.com> M: Angelo Dureghello <angelo(a)sysam.it> S: Maintained T: git git://git.denx.de/u-boot-coldfire.git -- 2.7.4

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[U-Boot] [ANN] U-Boot v2018.05-rc3 released
by Tom Rini 01 May '18

01 May '18

Hey all, Just like for v2018.03-rc3, we're a day late. That's just on me, sorry. Things are looking good for final release on May 7th. I might be able to pull in one or two more Kconfig migrations if I can be sure about the lack of size changes. I see there's a lot of stuff that's ready to come in once the release happens which is good. I also plan to right away switch travis-ci over to using gcc-7.3 for builds, once the release happens. Thanks all! -- Tom

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