May 2018 - U-Boot

[U-Boot] [PATCH v2 1/5] regmap: Add size parameter
by Mario Six 04 May '18

04 May '18

The regmap functions currently assume that all register map accesses have a data width of 32 bits, but there are maps that have different widths. Implement a size parameter for the regmap_read and regmap_write functions to specify the width of a desired read or write operation on a regmap. Correct all current clients of the regmap API to use 32 bit width reads and writes to keep backwards compatibility. Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- v1 -> v2: New in v2 --- drivers/clk/at91/clk-utmi.c | 6 +++-- drivers/clk/clk_boston.c | 3 ++- drivers/core/regmap.c | 45 ++++++++++++++++++++++++------- drivers/phy/meson-gxl-usb2.c | 18 ++++++------- drivers/phy/meson-gxl-usb3.c | 22 +++++++-------- drivers/power/regulator/pbias_regulator.c | 5 ++-- drivers/reset/reset-meson.c | 14 +++++----- drivers/sysreset/sysreset_syscon.c | 2 +- include/regmap.h | 11 ++++++-- 9 files changed, 82 insertions(+), 44 deletions(-) diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index 875bf293f9..1da625cab1 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -68,13 +68,15 @@ static int utmi_clk_enable(struct clk *clk) } if (plat->regmap_sfr) { - err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp); + err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp, + REGMAP_SIZE_32); if (err) return -EINVAL; tmp &= ~AT91_UTMICKTRIM_FREQ; tmp |= utmi_ref_clk_freq; - err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp); + err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp, + REGMAP_SIZE_32); if (err) return -EINVAL; } else if (utmi_ref_clk_freq) { diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c index 5c05e3d78d..e09fd06fa0 100644 --- a/drivers/clk/clk_boston.c +++ b/drivers/clk/clk_boston.c @@ -33,7 +33,8 @@ static ulong clk_boston_get_rate(struct clk *clk) uint mmcmdiv; int err; - err = regmap_read(state->regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv); + err = regmap_read(state->regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv, + REGMAP_SIZE_32); if (err) return 0; diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 8a0e00ff9a..c2cdff3979 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -130,20 +130,47 @@ int regmap_uninit(struct regmap *map) return 0; } -int regmap_read(struct regmap *map, uint offset, uint *valp) +int regmap_read(struct regmap *map, ulong offset, ulong *valp, + enum regmap_size_t size) { - uint32_t *ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE); - - *valp = le32_to_cpu(readl(ptr)); - + void *ptr; + + switch (size) { + case REGMAP_SIZE_8: + ptr = map_physmem(map->base + offset, 1, MAP_NOCACHE); + *valp = readb(ptr); + break; + case REGMAP_SIZE_16: + ptr = map_physmem(map->base + offset, 2, MAP_NOCACHE); + *valp = le16_to_cpu(readw(ptr)); + break; + case REGMAP_SIZE_32: + ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE); + *valp = le32_to_cpu(readl(ptr)); + break; + } return 0; } -int regmap_write(struct regmap *map, uint offset, uint val) +int regmap_write(struct regmap *map, ulong offset, ulong val, + enum regmap_size_t size) { - uint32_t *ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE); - - writel(cpu_to_le32(val), ptr); + void *ptr; + + switch (size) { + case REGMAP_SIZE_8: + ptr = map_physmem(map->base + offset, 1, MAP_NOCACHE); + writel((u8)val, ptr); + break; + case REGMAP_SIZE_16: + ptr = map_physmem(map->base + offset, 2, MAP_NOCACHE); + writel(cpu_to_le16((u16)val), ptr); + break; + case REGMAP_SIZE_32: + ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE); + writel(cpu_to_le32((u32)val), ptr); + break; + } return 0; } diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c index 15c9c89fd9..704b78747c 100644 --- a/drivers/phy/meson-gxl-usb2.c +++ b/drivers/phy/meson-gxl-usb2.c @@ -111,15 +111,15 @@ static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv) { uint val; - regmap_read(priv->regmap, U2P_R0, &val); + regmap_read(priv->regmap, U2P_R0, &val, REGMAP_SIZE_32); /* reset the PHY and wait until settings are stabilized */ val |= U2P_R0_POWER_ON_RESET; - regmap_write(priv->regmap, U2P_R0, val); + regmap_write(priv->regmap, U2P_R0, val, REGMAP_SIZE_32); udelay(RESET_COMPLETE_TIME); val &= ~U2P_R0_POWER_ON_RESET; - regmap_write(priv->regmap, U2P_R0, val); + regmap_write(priv->regmap, U2P_R0, val, REGMAP_SIZE_32); udelay(RESET_COMPLETE_TIME); } @@ -128,11 +128,11 @@ phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv) { uint val; - regmap_read(priv->regmap, U2P_R0, &val); + regmap_read(priv->regmap, U2P_R0, &val, REGMAP_SIZE_32); val |= U2P_R0_DM_PULLDOWN; val |= U2P_R0_DP_PULLDOWN; val &= ~U2P_R0_ID_PULLUP; - regmap_write(priv->regmap, U2P_R0, val); + regmap_write(priv->regmap, U2P_R0, val, REGMAP_SIZE_32); phy_meson_gxl_usb2_reset(priv); } @@ -143,10 +143,10 @@ static int phy_meson_gxl_usb2_power_on(struct phy *phy) struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); uint val; - regmap_read(priv->regmap, U2P_R0, &val); + regmap_read(priv->regmap, U2P_R0, &val, REGMAP_SIZE_32); /* power on the PHY by taking it out of reset mode */ val &= ~U2P_R0_POWER_ON_RESET; - regmap_write(priv->regmap, U2P_R0, val); + regmap_write(priv->regmap, U2P_R0, val, REGMAP_SIZE_32); phy_meson_gxl_usb2_set_host_mode(priv); @@ -167,10 +167,10 @@ static int phy_meson_gxl_usb2_power_off(struct phy *phy) struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); uint val; - regmap_read(priv->regmap, U2P_R0, &val); + regmap_read(priv->regmap, U2P_R0, &val, REGMAP_SIZE_32); /* power off the PHY by putting it into reset mode */ val |= U2P_R0_POWER_ON_RESET; - regmap_write(priv->regmap, U2P_R0, val); + regmap_write(priv->regmap, U2P_R0, val, REGMAP_SIZE_32); #if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->phy_supply) { diff --git a/drivers/phy/meson-gxl-usb3.c b/drivers/phy/meson-gxl-usb3.c index a385fbdf12..33c24fd989 100644 --- a/drivers/phy/meson-gxl-usb3.c +++ b/drivers/phy/meson-gxl-usb3.c @@ -100,13 +100,13 @@ phy_meson_gxl_usb3_set_host_mode(struct phy_meson_gxl_usb3_priv *priv) { uint val; - regmap_read(priv->regmap, USB_R0, &val); + regmap_read(priv->regmap, USB_R0, &val, REGMAP_SIZE_32); val &= ~USB_R0_U2D_ACT; - regmap_write(priv->regmap, USB_R0, val); + regmap_write(priv->regmap, USB_R0, val, REGMAP_SIZE_32); - regmap_read(priv->regmap, USB_R4, &val); + regmap_read(priv->regmap, USB_R4, &val, REGMAP_SIZE_32); val &= ~USB_R4_P21_SLEEP_M0; - regmap_write(priv->regmap, USB_R4, val); + regmap_write(priv->regmap, USB_R4, val, REGMAP_SIZE_32); return 0; } @@ -117,12 +117,12 @@ static int phy_meson_gxl_usb3_power_on(struct phy *phy) struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); uint val; - regmap_read(priv->regmap, USB_R5, &val); + regmap_read(priv->regmap, USB_R5, &val, REGMAP_SIZE_32); val |= USB_R5_ID_DIG_EN_0; val |= USB_R5_ID_DIG_EN_1; val &= ~USB_R5_ID_DIG_TH_MASK; val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff); - regmap_write(priv->regmap, USB_R5, val); + regmap_write(priv->regmap, USB_R5, val, REGMAP_SIZE_32); return phy_meson_gxl_usb3_set_host_mode(priv); } @@ -133,10 +133,10 @@ static int phy_meson_gxl_usb3_power_off(struct phy *phy) struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); uint val; - regmap_read(priv->regmap, USB_R5, &val); + regmap_read(priv->regmap, USB_R5, &val, REGMAP_SIZE_32); val &= ~USB_R5_ID_DIG_EN_0; val &= ~USB_R5_ID_DIG_EN_1; - regmap_write(priv->regmap, USB_R5, val); + regmap_write(priv->regmap, USB_R5, val, REGMAP_SIZE_32); return 0; } @@ -147,10 +147,10 @@ static int phy_meson_gxl_usb3_init(struct phy *phy) struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); uint val; - regmap_read(priv->regmap, USB_R1, &val); + regmap_read(priv->regmap, USB_R1, &val, REGMAP_SIZE_32); val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK; val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20); - regmap_write(priv->regmap, USB_R1, val); + regmap_write(priv->regmap, USB_R1, val, REGMAP_SIZE_32); return 0; } @@ -169,7 +169,7 @@ int meson_gxl_usb3_phy_probe(struct udevice *dev) ret = regmap_init_mem(dev, &priv->regmap); if (ret) return ret; - + #if CONFIG_IS_ENABLED(CLK) ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) diff --git a/drivers/power/regulator/pbias_regulator.c b/drivers/power/regulator/pbias_regulator.c index adf589b224..386da3a58f 100644 --- a/drivers/power/regulator/pbias_regulator.c +++ b/drivers/power/regulator/pbias_regulator.c @@ -46,7 +46,7 @@ static int pbias_write(struct udevice *dev, uint reg, const uint8_t *buff, if (len != 4) return -EINVAL; - return regmap_write(priv->regmap, priv->offset, val); + return regmap_write(priv->regmap, priv->offset, val, REGMAP_SIZE_32); } static int pbias_read(struct udevice *dev, uint reg, uint8_t *buff, int len) @@ -56,7 +56,8 @@ static int pbias_read(struct udevice *dev, uint reg, uint8_t *buff, int len) if (len != 4) return -EINVAL; - return regmap_read(priv->regmap, priv->offset, (u32 *)buff); + return regmap_read(priv->regmap, priv->offset, (u32 *)buff, + REGMAP_SIZE_32); } static int pbias_ofdata_to_platdata(struct udevice *dev) diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 5324f86f5f..c31f302143 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -41,12 +41,12 @@ static int meson_reset_level(struct reset_ctl *reset_ctl, bool assert) uint reg_offset = LEVEL_OFFSET + (bank << 2); uint val; - regmap_read(priv->regmap, reg_offset, &val); + regmap_read(priv->regmap, reg_offset, &val, REGMAP_SIZE_32); if (assert) val &= ~BIT(offset); else val |= BIT(offset); - regmap_write(priv->regmap, reg_offset, val); + regmap_write(priv->regmap, reg_offset, val, REGMAP_SIZE_32); return 0; } @@ -68,15 +68,15 @@ struct reset_ops meson_reset_ops = { .rst_deassert = meson_reset_deassert, }; -static const struct udevice_id meson_reset_ids[] = { - { .compatible = "amlogic,meson-gxbb-reset" }, - { } -}; +static const struct udevice_id meson_reset_ids[] = { + { .compatible = "amlogic,meson-gxbb-reset" }, + { } +}; static int meson_reset_probe(struct udevice *dev) { struct meson_reset_priv *priv = dev_get_priv(dev); - + return regmap_init_mem(dev, &priv->regmap); } diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c index 22c602a4d2..0c374a7443 100644 --- a/drivers/sysreset/sysreset_syscon.c +++ b/drivers/sysreset/sysreset_syscon.c @@ -25,7 +25,7 @@ static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type) { struct syscon_reboot_priv *priv = dev_get_priv(dev); - regmap_write(priv->regmap, priv->offset, priv->mask); + regmap_write(priv->regmap, priv->offset, priv->mask, REGMAP_SIZE_32); return -EINPROGRESS; } diff --git a/include/regmap.h b/include/regmap.h index 493a5d8eff..a6e2fafd27 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -8,6 +8,13 @@ #ifndef __REGMAP_H #define __REGMAP_H +/* Access sizes for fpgamap reads and writes */ +enum regmap_size_t { + REGMAP_SIZE_8 = 1, + REGMAP_SIZE_16 = 2, + REGMAP_SIZE_32 = 4, +}; + /** * struct regmap_range - a register map range * @@ -37,8 +44,8 @@ struct regmap { * Interface to provide access to registers either through a direct memory * bus or through a peripheral bus like I2C, SPI. */ -int regmap_write(struct regmap *map, uint offset, uint val); -int regmap_read(struct regmap *map, uint offset, uint *valp); +int regmap_write(struct regmap *map, ulong offset, ulong val, enum regmap_size_t size); +int regmap_read(struct regmap *map, ulong offset, ulong *valp, enum regmap_size_t size); #define regmap_write32(map, ptr, member, val) \ regmap_write(map, (uint32_t *)(ptr)->member - (uint32_t *)(ptr), val) -- 2.16.1

3 10

[U-Boot] Getting issue while building u-boot with the revision v2018.01 for armv8.
by Ashwin Kumar 04 May '18

04 May '18

I am getting the following error message when I configure u-boot to vexpress_aemv8a_dram_defconfig. *Error:* {standard input}: Assembler messages: {standard input}:36: Error: unexpected character `n' in type specifier {standard input}:36: Error: bad instruction `b.ne 1b' scripts/Makefile.build:280: recipe for target 'arch/arm/cpu/armv8/cpu.o' failed make[1]: *** [arch/arm/cpu/armv8/cpu.o] Error 1 Makefile:1284: recipe for target 'arch/arm/cpu/armv8' failed make: *** [arch/arm/cpu/armv8] Error 2 I am using toolchain arm-none-eabi-gcc version 6.3.1. -- Sent from: http://u-boot.10912.n7.nabble.com/

1 0

[U-Boot] Re-introducing support for OLD hardware
by Jason Mitchell 04 May '18

04 May '18

Good day all I am currently faced with a task of having to run new software on ageing hardware. We have currently about 1000 units in the field of a machine that runs Windows CE using the Samsung S3C6410. Because these are considerable assets its not a simple case of replacing them with new, more modern hardware. The goal is to be able to get these existing boards to run Ubuntu so that we can run GoLang applications, so we need the GUI with just a relatively recent browser. The board in question is a near perfect clone of the SMDK6410, which was supported fully in U-boot in the past, indeed I can select SMDK6410 and compile a working U-boot using 1.3.4 sources After much effort I managed to get a tailored (tailored as in having changed the memory configuration to match the hardware) U-boot V1.3.4 compiled and running for this chip, the problem now, obviously we have a fairly recent Linux kernel compiled and it won't boot because the Device Tree Blob doesn't exist on such an old version of U-boot. So my questions are: - Has anyone perhaps created a branch or fork of the current or nearly current version of U-boot and patched in this support. I see a lot of Chinese websites where they seem to have done this but the language barrier is a big problem. Also a lot of dead links are another problem. - If there isn't something out there, would it be possible to run through the steps with me to add support for this CPU again. I don't mind doing the work, the main issue is I have no clue how U-boot actually works internally. I have FULL JTAG access to this board, with a perfectly functional OpenOCD setup. This is how we are able to program versions of U-boot into the FLASH. Hoping someone can assist Kindest Regards, Jason Mitchell Software Developer Spark ATM Systems (PTY) LTD

3 4

[U-Boot] [PATCH v2 1/2] board: move ppa firmware address in board specific kconfig
by Bhaskar Upadhaya 04 May '18

04 May '18

ppa firmware address may vary depending upon different boards, configure ppa firmware address in board specific kconfig Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya(a)nxp.com> --- Comments from v1: - move SYS_LS_PPA_FW_IN_MMC, SYS_LS_PPA_FW_IN_NAND in board files. arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 17 ------------- board/freescale/ls1012afrdm/Kconfig | 4 +++ board/freescale/ls1012aqds/Kconfig | 3 +++ board/freescale/ls1012ardb/Kconfig | 8 ++++++ board/freescale/ls1043aqds/Kconfig | 21 ++++++++++++++++ board/freescale/ls1043ardb/Kconfig | 21 ++++++++++++++++ board/freescale/ls1046aqds/Kconfig | 21 ++++++++++++++++ board/freescale/ls1046ardb/Kconfig | 22 ++++++++++++++++ board/freescale/ls1088a/Kconfig | 28 +++++++++++++++++++++ board/freescale/ls2080aqds/Kconfig | 21 ++++++++++++++++ board/freescale/ls2080ardb/Kconfig | 42 +++++++++++++++++++++++++++++++ 11 files changed, 191 insertions(+), 17 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 7edc06d..67bb28e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -261,23 +261,6 @@ config SYS_LS_PPA_FW_IN_NAND endchoice -config SYS_LS_PPA_FW_ADDR - hex "Address of PPA firmware loading from" - depends on FSL_LS_PPA - default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A - default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT - default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A - default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A - default 0x60400000 if SYS_LS_PPA_FW_IN_XIP - default 0x400000 if SYS_LS_PPA_FW_IN_MMC - default 0x400000 if SYS_LS_PPA_FW_IN_NAND - - help - If the PPA firmware locate at XIP flash, such as NOR or - QSPI flash, this address is a directly memory-mapped. - If it is in a serial accessed flash, such as NAND and SD - card, it is a byte offset. - config SYS_LS_PPA_ESBC_ADDR hex "hdr address of PPA firmware loading from" depends on FSL_LS_PPA && CHAIN_OF_TRUST diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig index 22d521b..fd33807 100644 --- a/board/freescale/ls1012afrdm/Kconfig +++ b/board/freescale/ls1012afrdm/Kconfig @@ -12,6 +12,10 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1012afrdm" +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 + if FSL_PFE config BOARD_SPECIFIC_OPTIONS # dummy diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig index c0b12ed..b702fb2 100644 --- a/board/freescale/ls1012aqds/Kconfig +++ b/board/freescale/ls1012aqds/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1012aqds" +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 if FSL_PFE diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 493d477..0b873dd 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -12,6 +12,10 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1012ardb" +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 + if FSL_PFE config BOARD_SPECIFIC_OPTIONS # dummy @@ -59,6 +63,10 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1012a2g5rdb" +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 + if FSL_PFE config BOARD_SPECIFIC_OPTIONS # dummy diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig index 95d2888..3c571aa 100644 --- a/board/freescale/ls1043aqds/Kconfig +++ b/board/freescale/ls1043aqds/Kconfig @@ -12,6 +12,27 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1043aqds" +if SYS_LS_PPA_FW_IN_XIP + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x60400000 +endif + +if (SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 +endif + +if (SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x400000 +endif + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig index 1bab7ca..26272c9 100644 --- a/board/freescale/ls1043ardb/Kconfig +++ b/board/freescale/ls1043ardb/Kconfig @@ -22,6 +22,27 @@ config SYS_HAS_ARMV8_SECURE_BASE If enabled, please also define the value for ARMV8_SECURE_BASE, for LS1043ARDB, it could be some address in OCRAM. +if SYS_LS_PPA_FW_IN_XIP + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x60400000 +endif + +if (SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 +endif + +if (SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x400000 +endif + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig index 070827d..d75960f 100644 --- a/board/freescale/ls1046aqds/Kconfig +++ b/board/freescale/ls1046aqds/Kconfig @@ -12,6 +12,27 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1046aqds" +if SYS_LS_PPA_FW_IN_XIP + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x60400000 +endif + +if (SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 +endif + +if (SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x400000 +endif + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig index b9f2ed7..cd05cbf 100644 --- a/board/freescale/ls1046ardb/Kconfig +++ b/board/freescale/ls1046ardb/Kconfig @@ -12,5 +12,27 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1046ardb" + +if SYS_LS_PPA_FW_IN_XIP + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x60400000 +endif + +if (SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 +endif + +if (SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x400000 +endif + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig index 4479dd0..235e5d1 100644 --- a/board/freescale/ls1088a/Kconfig +++ b/board/freescale/ls1088a/Kconfig @@ -12,6 +12,20 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1088aqds" +if SYS_LS_PPA_FW_IN_XIP + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x20400000 +endif + +if (SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x400000 +endif + source "board/freescale/common/Kconfig" endif @@ -29,5 +43,19 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1088ardb" +if SYS_LS_PPA_FW_IN_XIP + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x20400000 +endif + +if (SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x400000 +endif + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls2080aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig index e2b2c8d..5f23304 100644 --- a/board/freescale/ls2080aqds/Kconfig +++ b/board/freescale/ls2080aqds/Kconfig @@ -13,6 +13,27 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls2080aqds" +if SYS_LS_PPA_FW_IN_XIP + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x580400000 +endif + +if (SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x20400000 +endif + +if (SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x400000 +endif + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig index 8f64642..787f8f4 100644 --- a/board/freescale/ls2080ardb/Kconfig +++ b/board/freescale/ls2080ardb/Kconfig @@ -13,6 +13,27 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls2080ardb" +if SYS_LS_PPA_FW_IN_XIP + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x580400000 +endif + +if (SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x20400000 +endif + +if (SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x400000 +endif + source "board/freescale/common/Kconfig" endif @@ -31,6 +52,27 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls2080ardb" +if SYS_LS_PPA_FW_IN_XIP + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x580400000 +endif + +if (SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x20400000 +endif + +if (SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND) + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x400000 +endif + source "board/freescale/common/Kconfig" endif -- 1.9.1

1 0

[U-Boot] [PATCH v2 2/2] drivers: spi: migrate cf_spi to DM
by Angelo Dureghello 04 May '18

04 May '18

This patch adds DM support to cf_spi.c. --- Changes from v1: - split into 2 patches Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- drivers/spi/cf_spi.c | 406 +++++++++++++++--------- include/dm/platform_data/spi_coldfire.h | 22 ++ 2 files changed, 278 insertions(+), 150 deletions(-) create mode 100644 include/dm/platform_data/spi_coldfire.h diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 68317ed633..ae8b7ef524 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -6,16 +6,23 @@ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) * + * Support for device model: + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <dm/platform_data/spi_coldfire.h> #include <spi.h> #include <malloc.h> #include <asm/immap.h> -struct cf_spi_slave { +struct coldfire_spi_priv { +#ifndef CONFIG_DM_SPI struct spi_slave slave; +#endif uint baudrate; int charbit; }; @@ -39,12 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000 -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) -{ - return container_of(slave, struct cf_spi_slave, slave); -} - -static void cfspi_init(void) +static void __spi_init(void) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -82,7 +84,123 @@ static void cfspi_init(void) #endif } -static void cfspi_tx(u32 ctrl, u16 data) +int __spi_set_speed(struct coldfire_spi_priv *cfspi, uint bus, uint mode) +{ + /* + * bit definition for mode: + * bit 31 - 28: Transfer size 3 to 16 bits + * 27 - 26: PCS to SCK delay prescaler + * 25 - 24: After SCK delay prescaler + * 23 - 22: Delay after transfer prescaler + * 21 : Allow overwrite for bit 31-22 and bit 20-8 + * 20 : Double baud rate + * 19 - 16: PCS to SCK delay scaler + * 15 - 12: After SCK delay scaler + * 11 - 8: Delay after transfer scaler + * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST + */ + volatile dspi_t *dspi = (dspi_t *)MMAP_DSPI; + int prescaler[] = { 2, 3, 5, 7 }; + int scaler[] = { + 2, 4, 6, 8, + 16, 32, 64, 128, + 256, 512, 1024, 2048, + 4096, 8192, 16384, 32768 + }; + int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; + int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed; + u32 bus_setup = 0; + + tmp = (prescaler[3] * scaler[15]); + /* Maximum and minimum baudrate it can handle */ + if ((cfspi->baudrate > (gd->bus_clk >> 1)) || + (cfspi->baudrate < (gd->bus_clk / tmp))) { + printf("Exceed baudrate limitation: Max %d - Min %d\n", + (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp)); + return -1; + } + + /* Activate Double Baud when it exceed 1/4 the bus clk */ + if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) || + (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { + bus_setup |= DSPI_CTAR_DBR; + dbr = 1; + } + + /* Overwrite default value set in platform configuration file */ + if (mode & SPI_MODE_MOD) { + /* + * Check to see if it is enabled by default in platform + * config, or manual setting passed by mode parameter + */ + if (mode & SPI_DBLRATE) { + bus_setup |= DSPI_CTAR_DBR; + dbr = 1; + } + } + + pbrcnt = sizeof(prescaler) / sizeof(int); + brcnt = sizeof(scaler) / sizeof(int); + + /* baudrate calculation - to closer value, may not be exact match */ + for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) { + baud_speed = gd->bus_clk / prescaler[i]; + for (j = 0; j < brcnt; j++) { + tmp = (baud_speed / scaler[j]) * (1 + dbr); + + if (tmp > cfspi->baudrate) + diff = tmp - cfspi->baudrate; + else + diff = cfspi->baudrate - tmp; + + if (diff < bestmatch) { + bestmatch = diff; + best_i = i; + best_j = j; + } + } + } + bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); + dspi->ctar[bus] |= bus_setup; + + return 0; +} + +static int __spi_set_mode(struct coldfire_spi_priv *cfspi, uint bus, uint mode) +{ + volatile dspi_t *dspi = (dspi_t *)MMAP_DSPI; + u32 bus_setup = 0; + + if (mode & SPI_CPOL) + bus_setup |= DSPI_CTAR_CPOL; + if (mode & SPI_CPHA) + bus_setup |= DSPI_CTAR_CPHA; + if (mode & SPI_LSB_FIRST) + bus_setup |= DSPI_CTAR_LSBFE; + + /* Overwrite default value set in platform configuration file */ + if (mode & SPI_MODE_MOD) { + if ((mode & 0xF0000000) == 0) + bus_setup |= + dspi->ctar[bus] & 0x78000000; + else + bus_setup |= ((mode & 0xF0000000) >> 1); + + bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */ + bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */ + } else { + bus_setup |= (dspi->ctar[bus] & 0x78FCFFF0); + } + + cfspi->charbit = + ((dspi->ctar[bus] & 0x78000000) == 0x78000000) ? 16 : 8; + + dspi->ctar[bus] |= bus_setup; + + return 0; +} + +static void __cfspi_tx(u32 ctrl, u16 data) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -91,7 +209,7 @@ static void cfspi_tx(u32 ctrl, u16 data) dspi->tfr = (ctrl | data); } -static u16 cfspi_rx(void) +static u16 __cfspi_rx(void) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -100,16 +218,15 @@ static u16 cfspi_rx(void) return (dspi->rfr & 0xFFFF); } -static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, - void *din, ulong flags) +static int __spi_xfer(struct coldfire_spi_priv *cfspi, uint cs, uint bitlen, + const void *dout, void *din, ulong flags) { - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); u16 *spi_rd16 = NULL, *spi_wr16 = NULL; u8 *spi_rd = NULL, *spi_wr = NULL; static u32 ctrl = 0; uint len = bitlen >> 3; - if (cfslave->charbit == 16) { + if (cfspi->charbit == 16) { bitlen >>= 1; spi_wr16 = (u16 *) dout; spi_rd16 = (u16 *) din; @@ -121,25 +238,25 @@ static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN) ctrl |= DSPI_TFR_CONT; - ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16); + ctrl = (ctrl & 0xFF000000) | ((1 << cs) << 16); if (len > 1) { int tmp_len = len - 1; while (tmp_len--) { if (dout != NULL) { - if (cfslave->charbit == 16) - cfspi_tx(ctrl, *spi_wr16++); + if (cfspi->charbit == 16) + __cfspi_tx(ctrl, *spi_wr16++); else - cfspi_tx(ctrl, *spi_wr++); - cfspi_rx(); + __cfspi_tx(ctrl, *spi_wr++); + __cfspi_rx(); } if (din != NULL) { - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - if (cfslave->charbit == 16) - *spi_rd16++ = cfspi_rx(); + __cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); + if (cfspi->charbit == 16) + *spi_rd16++ = __cfspi_rx(); else - *spi_rd++ = cfspi_rx(); + *spi_rd++ = __cfspi_rx(); } } @@ -151,186 +268,175 @@ static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, if (len) { if (dout != NULL) { - if (cfslave->charbit == 16) - cfspi_tx(ctrl, *spi_wr16); + if (cfspi->charbit == 16) + __cfspi_tx(ctrl, *spi_wr16); else - cfspi_tx(ctrl, *spi_wr); - cfspi_rx(); + __cfspi_tx(ctrl, *spi_wr); + __cfspi_rx(); } if (din != NULL) { - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - if (cfslave->charbit == 16) - *spi_rd16 = cfspi_rx(); + __cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); + if (cfspi->charbit == 16) + *spi_rd16 = __cfspi_rx(); else - *spi_rd = cfspi_rx(); + *spi_rd = __cfspi_rx(); } } else { /* dummy read */ - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - cfspi_rx(); + __cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); + __cfspi_rx(); } return 0; } -static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, - uint mode) +#ifndef CONFIG_DM_SPI + +static inline struct coldfire_spi_priv *to_coldfire_spi_slave + (struct spi_slave *slave) { - /* - * bit definition for mode: - * bit 31 - 28: Transfer size 3 to 16 bits - * 27 - 26: PCS to SCK delay prescaler - * 25 - 24: After SCK delay prescaler - * 23 - 22: Delay after transfer prescaler - * 21 : Allow overwrite for bit 31-22 and bit 20-8 - * 20 : Double baud rate - * 19 - 16: PCS to SCK delay scaler - * 15 - 12: After SCK delay scaler - * 11 - 8: Delay after transfer scaler - * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST - */ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - int prescaler[] = { 2, 3, 5, 7 }; - int scaler[] = { - 2, 4, 6, 8, - 16, 32, 64, 128, - 256, 512, 1024, 2048, - 4096, 8192, 16384, 32768 - }; - int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; - int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed; - u32 bus_setup = 0; + return container_of(slave, struct coldfire_spi_priv, slave); +} - tmp = (prescaler[3] * scaler[15]); - /* Maximum and minimum baudrate it can handle */ - if ((cfslave->baudrate > (gd->bus_clk >> 1)) || - (cfslave->baudrate < (gd->bus_clk / tmp))) { - printf("Exceed baudrate limitation: Max %d - Min %d\n", - (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp)); +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct coldfire_spi_priv *cfspi; + + if (!spi_cs_is_valid(bus, cs)) return NULL; - } - /* Activate Double Baud when it exceed 1/4 the bus clk */ - if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) || - (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { - bus_setup |= DSPI_CTAR_DBR; - dbr = 1; - } + cfspi = spi_alloc_slave(struct coldfire_spi_priv, bus, cs); + if (!cfspi) + return NULL; - if (mode & SPI_CPOL) - bus_setup |= DSPI_CTAR_CPOL; - if (mode & SPI_CPHA) - bus_setup |= DSPI_CTAR_CPHA; - if (mode & SPI_LSB_FIRST) - bus_setup |= DSPI_CTAR_LSBFE; + cfspi->baudrate = max_hz; - /* Overwrite default value set in platform configuration file */ - if (mode & SPI_MODE_MOD) { + if (__spi_set_speed(cfspi, bus, mode)) + return NULL; - if ((mode & 0xF0000000) == 0) - bus_setup |= - dspi->ctar[cfslave->slave.bus] & 0x78000000; - else - bus_setup |= ((mode & 0xF0000000) >> 1); + if (__spi_set_mode(cfspi, bus, mode)) + return NULL; - /* - * Check to see if it is enabled by default in platform - * config, or manual setting passed by mode parameter - */ - if (mode & SPI_DBLRATE) { - bus_setup |= DSPI_CTAR_DBR; - dbr = 1; - } - bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */ - bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */ - } else - bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0); + return &cfspi->slave; +} - cfslave->charbit = - ((dspi->ctar[cfslave->slave.bus] & 0x78000000) == - 0x78000000) ? 16 : 8; +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) + return 1; + else + return 0; +} - pbrcnt = sizeof(prescaler) / sizeof(int); - brcnt = sizeof(scaler) / sizeof(int); +void spi_init(void) +{ + __spi_init(); +} - /* baudrate calculation - to closer value, may not be exact match */ - for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) { - baud_speed = gd->bus_clk / prescaler[i]; - for (j = 0; j < brcnt; j++) { - tmp = (baud_speed / scaler[j]) * (1 + dbr); +void spi_free_slave(struct spi_slave *slave) +{ + struct coldfire_spi_priv *cfspi = to_coldfire_spi_slave(slave); - if (tmp > cfslave->baudrate) - diff = tmp - cfslave->baudrate; - else - diff = cfslave->baudrate - tmp; + free(cfspi); +} - if (diff < bestmatch) { - bestmatch = diff; - best_i = i; - best_j = j; - } - } - } - bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); - dspi->ctar[cfslave->slave.bus] = bus_setup; +int spi_claim_bus(struct spi_slave *slave) +{ + return cfspi_claim_bus(slave->bus, slave->cs); +} - return &cfslave->slave; +void spi_release_bus(struct spi_slave *slave) +{ + cfspi_release_bus(slave->bus, slave->cs); } -#endif /* CONFIG_CF_DSPI */ -#ifdef CONFIG_CMD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) { - if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) - return 1; - else - return 0; + struct coldfire_spi_priv *cfspi = to_coldfire_spi_slave(slave); + + return __spi_xfer(cfspi, slave->cs, bitlen, dout, din, flags); } +#else + void spi_init(void) { - cfspi_init(); + /* arch-related port configuration */ + __spi_init(); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +static int coldfire_spi_claim_bus(struct udevice *dev) { - struct cf_spi_slave *cfslave; + struct udevice *bus = dev_get_parent(dev); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); - if (!spi_cs_is_valid(bus, cs)) - return NULL; + return cfspi_claim_bus(bus->seq, plat->cs); +} - cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs); - if (!cfslave) - return NULL; +static int coldfire_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); - cfslave->baudrate = max_hz; + cfspi_release_bus(bus->seq, plat->cs); - /* specific setup */ - return cfspi_setup_slave(cfslave, mode); + return 0; } -void spi_free_slave(struct spi_slave *slave) +static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, + unsigned long flags) { - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); + struct udevice *bus = dev_get_parent(dev); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); - free(cfslave); + return __spi_xfer(cfspi, plat->cs, bitlen, dout, din, flags); } -int spi_claim_bus(struct spi_slave *slave) +static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz) { - return cfspi_claim_bus(slave->bus, slave->cs); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + + return __spi_set_speed(cfspi, bus->seq, plat->mode); } -void spi_release_bus(struct spi_slave *slave) +static int coldfire_spi_set_mode(struct udevice *bus, uint mode) { - cfspi_release_bus(slave->bus, slave->cs); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + + return __spi_set_mode(cfspi, bus->seq, plat->mode); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +static int coldfire_spi_probe(struct udevice *bus) { - return cfspi_xfer(slave, bitlen, dout, din, flags); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + + cfspi->baudrate = plat->speed_hz; + + return 0; } -#endif /* CONFIG_CMD_SPI */ + +static const struct dm_spi_ops coldfire_spi_ops = { + .claim_bus = coldfire_spi_claim_bus, + .release_bus = coldfire_spi_release_bus, + .xfer = coldfire_spi_xfer, + .set_speed = coldfire_spi_set_speed, + .set_mode = coldfire_spi_set_mode, +}; + +U_BOOT_DRIVER(coldfire_spi) = { + .name = "spi_coldfire", + .id = UCLASS_SPI, + .probe = coldfire_spi_probe, + .ops = &coldfire_spi_ops, + .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv), +}; +#endif /* CONFIG_DM_SPI */ +#endif /* CONFIG_CF_DSPI */ diff --git a/include/dm/platform_data/spi_coldfire.h b/include/dm/platform_data/spi_coldfire.h new file mode 100644 index 0000000000..44094b428d --- /dev/null +++ b/include/dm/platform_data/spi_coldfire.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2015 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __spi_coldfire_h +#define __spi_coldfire_h + +/* + * struct coldfire_spi_platdata - information about a coldfire spi module + * + * @speed_hz: SPI speed + */ +struct coldfire_spi_platdata { + uint speed_hz; + uint mode; + uint cs; +}; + +#endif /* __spi_coldfire_h */ + -- 2.17.0

1 0

[U-Boot] Booting Jerry chromebook from eMMC
by Carlo Caione 03 May '18

03 May '18

Hi, I'm trying to boot a Veyron Jerry chromebook using U-Boot placed in the eMMC. Booting from SPI using 'chromebook_jerry_defconfig' works perfectly fine, but I'm hitting a wall when moving from SPI to eMMC (mostly related to the limited space for the SPL). Has anyone managed to boot this platform directly from eMMC? Reading sources and documentation there is explicitly nothing related to boot this platform from eMMC so I was wondering if this is feasible at all. Thank you, -- Carlo Caione | +44.7384.69.16.04 | Endless

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[U-Boot] BUG: cannot boot with CONFIG_LOG
by Heinrich Schuchardt 03 May '18

03 May '18

Hello Simon, I am running vexpress_ca15_tc2_defconfig with qemu: QEMU_AUDIO_DRV=none qemu-system-arm \ -M vexpress-a15 -cpu cortex-a15 \ -kernel u-boot \ -net user -net nic,model=lan9118 \ -m 1024M --nographic \ -drive if=sd,file=../img.vexpress,media=disk,format=raw If I enable CONFIG_LOG=y starting U-Boot fails. This is due to log_init() returning -ENOMEM. If I change return -ENOMEM; to return 0; the board boots. log_init() is called twice: common/board_r.c:680: log_init, common/board_f.c:760: log_init, If I remove the call from common/board_f.c the board boots. What do you expect debug("%s: Cannot allocate memory\n", __func__); to do if logging is not yet initialized and the board is out of memory? Even if I #define DEBUG 1 I get no output created by this line. Best regards Heinrich

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[U-Boot] [PATCH v2 00/19] Introduce SPI TPM v2.0 support
by Miquel Raynal 03 May '18

03 May '18

Current U-Boot supports TPM v1.2 specification. The new specification (v2.0) is not backward compatible and renames/introduces several functions. This series introduces a new SPI driver following the TPM v2.0 specification. It has been tested on a ST TPM but should be usable with others v2.0 compliant chips. Then, basic functionalities are introduced one by one for the v2.0 specification. The INIT command now can receive a parameter to distinguish further TPMv1/TPMv2 commands. After that, the library itself will know which one is pertinent and will return a special error if the desired command is not supported for the selected specification. Available commands for v2.0 TPMs are: * STARTUP * SELF TEST * CLEAR * PCR EXTEND * PCR READ * GET CAPABILITY * DICTIONARY ATTACK LOCK RESET * DICTIONARY ATTACK CHANGE PARAMETERS * HIERARCHY CHANGE AUTH Two commands have been written but could not be tested (unsupported by the TPM chosen): * PCR CHANGE AUTH POLICY * PCR CHANGE AUTH VALUE With this set of function, minimal TPMv2.0 handling is possible with the following sequence. * First, initialize the TPM stack in U-Boot: "TPM2" is a new parameter to discern the format of the commands: > tpm init TPM2 * Then send the STARTUP command to the TPM. The flag is slightly different between the revisions. > tpm startup TPM2_SU_CLEAR * To enable full TPM capabilities, continue the tests (or do them all again). It seems like self_test_full always waits for the operation to finish, while continue_self_test returns a busy state if called to early. > tpm continue_self_test > tpm self_test_full * Manage passwords (force_clear also resets a lot of internal stuff). Olderly, TAKE OWNERSHIP == CLEAR + CHANGE AUTH. LOCKOUT is an example, ENDORSEMENT and PLATFORM hierarchies are available too: > tpm force_clear TPM2_RH_LOCKOUT [<pw>] > tpm change_auth TPM2_RH_LOCKOUT <new_pw> [<old_pw>] * Dictionary Attack Mitigation (DAM) parameters can be changed. It is possible to reset the failure counter and disable the lockout (values erased after a CLEAR). It is then possible to check the parameters have been correctly applied. > tpm dam_reset_counter [<pw>] > tpm dam_set_parameters 0xffff 1 0 [<pw>] > tpm get_capability 0x0006 0x020e 0x4000000 4 * PCR policy may be changed (untested). PCR can be extended (no protection against packet replay yet). PCR can be read (the counter with the number of "extensions" is also given). > tpm pcr_setauthpolicy 0 12345678901234567890123456789012 [<pw>] > tpm pcr_read 0 0x4000000 > tpm pcr_extend 0 0x4000000 Regular testing may be done through the test/py/ framework when using real hardware, there is no sandbox support for now. Thanks, Miquèl Miquel Raynal (19): tpm: add Revision ID field in the chip structure tpm: rename tpm_tis_infineon in tpm_tis_infineon_i2c tpm: add support for TPMv2 SPI modules tpm: fix indentation in command list before adding more tpm: prepare support for TPMv2 commands tpm: add macros for TPMv2 commands tpm: add possible traces to analyze buffers returned by the TPM tpm: handle different buffer sizes tpm: add TPM2_Startup command support tpm: add TPM2_SelfTest command support tpm: add TPM2_Clear command support tpm: rename the _extend() function to be _pcr_event() tpm: add TPM2_PCR_Extend command support tpm: add TPM2_PCR_Read command support tpm: add TPM2_GetCapability command support tpm: add dictionary attack mitigation commands support tpm: add TPM2_HierarchyChangeAuth command support tpm: add PCR authentication commands support test/py: add TPMv2.0 test suite cmd/tpm.c | 360 +++++++++-- cmd/tpm_test.c | 10 +- drivers/tpm/Kconfig | 13 +- drivers/tpm/Makefile | 3 +- drivers/tpm/tpm_tis.h | 4 + .../{tpm_tis_infineon.c => tpm_tis_infineon_i2c.c} | 2 +- drivers/tpm/tpm_tis_spi.c | 656 +++++++++++++++++++++ include/tpm.h | 183 +++++- lib/tpm.c | 654 ++++++++++++++++++-- test/py/tests/test_tpm2.py | 254 ++++++++ 10 files changed, 1993 insertions(+), 146 deletions(-) rename drivers/tpm/{tpm_tis_infineon.c => tpm_tis_infineon_i2c.c} (99%) create mode 100644 drivers/tpm/tpm_tis_spi.c create mode 100644 test/py/tests/test_tpm2.py -- 2.14.1

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[U-Boot] [PATCH v2 1/3] drivers: Add board uclass
by Mario Six 03 May '18

03 May '18

Since there is no canonical "board device" that can be used in board files, it is difficult to use DM function for board initialization in these cases. Hence, add a uclass that implements a simple "board device", which can hold devices not suitable anywhere else in the device tree, and is also able to read encoded information, e.g. hard-wired GPIOs on a GPIO expander, read-only memory ICs, etc. that carry information about the hardware. The devices of this uclass expose methods to read generic data types (integers, strings, booleans) to encode the information provided by the hardware. Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- v1 -> v2: * Corrected description of dev parameter of devinfo_detect * Added size parameter to devinfo_get_str * Expanded uclass documentation * Added function to get devinfo instance * Renamed the uclass from devinfo to board --- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/board/Kconfig | 17 +++++++ drivers/board/Makefile | 9 ++++ drivers/board/board-uclass.c | 61 +++++++++++++++++++++++ include/board.h | 115 +++++++++++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + 7 files changed, 206 insertions(+) create mode 100644 drivers/board/Kconfig create mode 100644 drivers/board/Makefile create mode 100644 drivers/board/board-uclass.c create mode 100644 include/board.h diff --git a/drivers/Kconfig b/drivers/Kconfig index c2e813f5ad..19c7c448c0 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -22,6 +22,8 @@ source "drivers/ddr/Kconfig" source "drivers/demo/Kconfig" +source "drivers/board/Kconfig" + source "drivers/ddr/fsl/Kconfig" source "drivers/dfu/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 6846d181aa..fecf64021c 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -72,6 +72,7 @@ obj-y += block/ obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/ obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ +obj-y += board/ obj-y += firmware/ obj-$(CONFIG_FPGA) += fpga/ obj-y += misc/ diff --git a/drivers/board/Kconfig b/drivers/board/Kconfig new file mode 100644 index 0000000000..cc1cf27205 --- /dev/null +++ b/drivers/board/Kconfig @@ -0,0 +1,17 @@ +menuconfig BOARD + bool "Device Information" + help + Support methods to query hardware configurations from internal + mechanisms (e.g. reading GPIO values, determining the presence of + devices on busses, etc.). This enables the usage of U-Boot with + modular board architectures. + +if BOARD + + +config BOARD_GAZERBEAM + bool "Enable device information for the Gazerbeam board" + help + Support querying device information for the gdsys Gazerbeam board. + +endif diff --git a/drivers/board/Makefile b/drivers/board/Makefile new file mode 100644 index 0000000000..397706245a --- /dev/null +++ b/drivers/board/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2017 +# Mario Six, Guntermann & Drunck GmbH, mario.six(a)gdsys.cc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_BOARD) += board-uclass.o +obj-$(CONFIG_BOARD_GAZERBEAM) += gazerbeam.o diff --git a/drivers/board/board-uclass.c b/drivers/board/board-uclass.c new file mode 100644 index 0000000000..3137437245 --- /dev/null +++ b/drivers/board/board-uclass.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six(a)gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <board.h> + +int get_board(struct udevice **devp) +{ + return uclass_first_device_err(UCLASS_BOARD, devp); +} + +int board_detect(struct udevice *dev) +{ + struct board_ops *ops = board_get_ops(dev); + + if (!ops->detect) + return -ENOSYS; + + return ops->detect(dev); +} + +int board_get_bool(struct udevice *dev, int id, bool *val) +{ + struct board_ops *ops = board_get_ops(dev); + + if (!ops->get_bool) + return -ENOSYS; + + return ops->get_bool(dev, id, val); +} + +int board_get_int(struct udevice *dev, int id, int *val) +{ + struct board_ops *ops = board_get_ops(dev); + + if (!ops->get_int) + return -ENOSYS; + + return ops->get_int(dev, id, val); +} + +int board_get_str(struct udevice *dev, int id, size_t size, char *val) +{ + struct board_ops *ops = board_get_ops(dev); + + if (!ops->get_str) + return -ENOSYS; + + return ops->get_str(dev, id, size, val); +} + +UCLASS_DRIVER(board) = { + .id = UCLASS_BOARD, + .name = "board", + .post_bind = dm_scan_fdt_dev, +}; diff --git a/include/board.h b/include/board.h new file mode 100644 index 0000000000..0e64a3dfce --- /dev/null +++ b/include/board.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six(a)gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/** + * This uclass encapsulates hardware methods to gather information about a + * board or a specific device such as hard-wired GPIOs on GPIO expanders, + * read-only data in flash ICs, or similar. + * + * The interface offers functions to read the usual standard data types (bool, + * int, string) from the device, each of which is identified by a static + * numeric ID (which will usually be defined as a enum in a header file). + * + * If for example dev was a board device representing a read-only serial + * number flash IC, we could call + * + * board_detect(dev); + * board_get_int(dev, ID_SERIAL_NUMBER, &serial); + * + * to read the serial number from the device. + */ + +struct board_ops { + /** + * detect() - Run the hardware info detection procedure for this + * device. + * + * @dev: The device containing the information + * @return 0 if OK, -ve on error. + */ + int (*detect)(struct udevice *dev); + + /** + * get_bool() - Read a specific bool data value that describes the + * hardware setup. + * + * @dev: The board instance to gather the data. + * @id: A unique identifier for the bool value to be read. + * @val: Pointer to a buffer that receives the value read. + * @return 0 if OK, -ve on error. + */ + int (*get_bool)(struct udevice *dev, int id, bool *val); + + /** + * get_int() - Read a specific int data value that describes the + * hardware setup. + * + * @dev: The board instance to gather the data. + * @id: A unique identifier for the int value to be read. + * @val: Pointer to a buffer that receives the value read. + * @return 0 if OK, -ve on error. + */ + int (*get_int)(struct udevice *dev, int id, int *val); + + /** + * get_str() - Read a specific string data value that describes the + * hardware setup. + * + * @dev: The board instance to gather the data. + * @id: A unique identifier for the string value to be read. + * @size: The size of the buffer to receive the string data. + * @val: Pointer to a buffer that receives the value read. + * @return 0 if OK, -ve on error. + */ + int (*get_str)(struct udevice *dev, int id, size_t size, char *val); +}; + +#define board_get_ops(dev) ((struct board_ops *)(dev)->driver->ops) + +/** + * board_detect() - Run the hardware info detection procedure for this device. + * + * @dev: The device containing the information + * @return 0 if OK, -ve on error. + */ +int board_detect(struct udevice *dev); + +/** + * board_get_bool() - Read a specific bool data value that describes the + * hardware setup. + * + * @dev: The board instance to gather the data. + * @id: A unique identifier for the bool value to be read. + * @val: Pointer to a buffer that receives the value read. + * @return 0 if OK, -ve on error. + */ +int board_get_bool(struct udevice *dev, int id, bool *val); + +/** + * board_get_int() - Read a specific int data value that describes the + * hardware setup. + * + * @dev: The board instance to gather the data. + * @id: A unique identifier for the int value to be read. + * @val: Pointer to a buffer that receives the value read. + * @return 0 if OK, -ve on error. + */ +int board_get_int(struct udevice *dev, int id, int *val); + +/** + * board_get_str() - Read a specific string data value that describes the + * hardware setup. + * + * @dev: The board instance to gather the data. + * @id: A unique identifier for the string value to be read. + * @size: The size of the buffer to receive the string data. + * @val: Pointer to a buffer that receives the value read. + * @return 0 if OK, -ve on error. + */ +int board_get_str(struct udevice *dev, int id, size_t size, char *val); + +int get_board(struct udevice **devp); diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index d28fb3e23f..97327194b4 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -30,6 +30,7 @@ enum uclass_id { UCLASS_ADC, /* Analog-to-digital converter */ UCLASS_AHCI, /* SATA disk controller */ UCLASS_BLK, /* Block device */ + UCLASS_BOARD, /* Device information from hardware */ UCLASS_CLK, /* Clock source, e.g. used by peripherals */ UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CROS_EC, /* Chrome OS EC */ -- 2.16.1

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[U-Boot] FitImage add pubkey signature in DTS
by Clément Péron 03 May '18

03 May '18

Hi, I'm looking to add the public key for the FitImage signature in my dts. Do you know if there is a script to add the pubkey in the .dts and not in the .dtb ? Actually I "decompile" the .dtb to get those values, but maybe there is an easier way. Looking to generate something like this from the RSA keys : signature { key-product-dev { required = "conf"; algo = "sha1,rsa2048"; rsa,r-squared = <0x68b44337 0x916dcfda 0x.....> rsa,modulus = <0xb7929d33 0x34df0e32 0x......> rsa,exponent = <0x0 0x10001>; rsa,n0-inverse = <0x29.....>; rsa,num-bits = <0x800>; key-name-hint = "product-dev"; }; }; Thanks, Clement

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