May 2018 - U-Boot

[U-Boot] boot progress for invalid ramdisk
by Marcel Hellwig 14 May '18

14 May '18

Hi there, I'm using the show_boot_progress function to keep track of the boot process and display errors during the boot on a display (which will be controlled via UART). This works fine for e.g. a bad CRC in the kernel, which will give me a negative progress and I can check, that that is an error. For the Ramdisk on the other hand, there is no show_boot_progress for an invalid ramdisk (see [0]). So, two questions. 1. There are many places which don't have a show_boot_progress but are a "fail" branch. Can this be done so you can track every (possible) error? 2. Is there a way to "get notified" if the shell opens (e.g. call a callback function), so I can check that (this is usally an error :) )? Greetings, Marcel [0]: https://github.com/u-boot/u-boot/blob/62d77cea31216cad526e5f45c88e8377efc6f…

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[U-Boot] [PATCH v2 00/11] pmic: sandbox: Add support for MC34709 PMIC
by Lukasz Majewski 14 May '18

14 May '18

Adding this device required some changes into the PMIC uclass. Most notable one was the support for 3 bytes r/w operations. Moreover, emulation and tests for this device has been added to sandbox. Lukasz Majewski (11): pmic: fsl: Provide some more definitions for MC34708 PMIC pmic: fsl: Define number of bytes sent at once by MC34708 PMIC pmic: Add support for setting transmission length in uclass private data pmic: dm: Rewrite pmic_reg_{read|write|clrsetbits} to support 3 bytes transmissions pmic: dm: Add support for MC34708 for PMIC DM pmic: Rewrite the pmic command to not only work with single byte transmission sandbox: Rewrite i2c_pmic_emul.c to support PMIC with 3 bytes transmission sandbox: Enable support for MC34708 PMIC in DTS sandbox: Enable MC34708 PMIC support sandbox: tests: Exclude common test code (pmic_get) in test/dm/pmic.c sandbox: tests: Add tests for mc34708 PMIC device arch/sandbox/dts/sandbox.dts | 4 ++ arch/sandbox/dts/sandbox64.dts | 4 ++ arch/sandbox/dts/sandbox_pmic.dtsi | 33 ++++++++++++ arch/sandbox/dts/test.dts | 4 ++ cmd/pmic.c | 31 +++++++----- configs/sandbox_defconfig | 1 + drivers/power/pmic/Kconfig | 7 +++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/i2c_pmic_emul.c | 45 ++++++++++++----- drivers/power/pmic/mc34708.c | 101 +++++++++++++++++++++++++++++++++++++ drivers/power/pmic/pmic-uclass.c | 54 +++++++++++++++----- include/fsl_pmic.h | 41 +++++++++++++++ include/power/pmic.h | 4 ++ test/dm/pmic.c | 68 ++++++++++++++++++++++++- 14 files changed, 358 insertions(+), 40 deletions(-) create mode 100644 drivers/power/pmic/mc34708.c -- 2.11.0

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[U-Boot] [PATCH] rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC
by Wadim Egorov 14 May '18

14 May '18

The generic ehci-driver (ehci-generic.c) will try to enable the clocks listed in the DTSI. If this fails (e.g. due to clk_enable not being implemented in a driver and -ENOSYS being returned by the clk-uclass), the driver will bail our and print an error message. This implements a minimal clk_enable for the RK3288 and supports the clocks mandatory for the EHCI controllers; as these are enabled by default we simply return success. Signed-off-by: Wadim Egorov <w.egorov(a)phytec.de> --- drivers/clk/rockchip/clk_rk3288.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 552a71a..a028b8b 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -893,12 +893,25 @@ static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *par return -ENOENT; } +static int rk3288_clk_enable(struct clk *clk) +{ + switch (clk->id) { + case HCLK_USBHOST0: + case HCLK_HSIC: + return 0; + } + + debug("%s: unsupported clk %ld\n", __func__, clk->id); + return -ENOENT; +} + static struct clk_ops rk3288_clk_ops = { .get_rate = rk3288_clk_get_rate, .set_rate = rk3288_clk_set_rate, #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .set_parent = rk3288_clk_set_parent, #endif + .enable = rk3288_clk_enable, }; static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) -- 2.7.4

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[U-Boot] [RFC PATCH 0/1] Convert USB fastboot code to use shared protocol
by Alex Kiernan 14 May '18

14 May '18

This builds on the fastboot UDP support and migrates the USB fastboot code to the shared code. It's currently untested, other than passing in Travis: https://travis-ci.org/akiernan/u-boot/builds/378475039 Alex Kiernan (1): usb: fastboot: Convert USB f_fastboot to shared fastboot drivers/usb/gadget/f_fastboot.c | 310 +++++----------------------------------- 1 file changed, 36 insertions(+), 274 deletions(-) -- 2.7.4

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[U-Boot] [PATCH v2] board: sun50i: Add Amarula A64 Relic initial support
by Jagan Teki 14 May '18

14 May '18

Amarula A64 Relic is A64 based IoT device, which support - Allwinner A64 Cortex-A53 - Mali-400MP2 GPU - AXP803 PMIC - 1GB DDR3 RAM - 8GB eMMC - AP6330 Wifi/BLE - MIPI-DSI - CSI: OV5640 sensor - USB OTG - 12V DC power supply Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v2: - Rename dts name to sun50i-a64-relic.dts which is simple to use - Rename defconfig to a64_relic_defconfig - Use licence year as 2018 Note: Maxime, I saw your previous comments about CONFIG_CMD_USB_MASS_STORAGE defining in defconfig, may I know why we can't enable it in defconfig file? arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun50i-a64-relic.dts | 65 +++++++++++++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 6 ++++ configs/a64_relic_defconfig | 18 +++++++++++ 4 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun50i-a64-relic.dts create mode 100644 configs/a64_relic_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 289e11551a..676d7944c0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -381,7 +381,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-olinuxino.dtb \ sun50i-a64-orangepi-win.dtb \ sun50i-a64-pine64-plus.dtb \ - sun50i-a64-pine64.dtb + sun50i-a64-pine64.dtb \ + sun50i-a64-relic.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb \ diff --git a/arch/arm/dts/sun50i-a64-relic.dts b/arch/arm/dts/sun50i-a64-relic.dts new file mode 100644 index 0000000000..0320fd01b4 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-relic.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki <jagan(a)amarulasolutions.com> + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Amarula A64 Relic"; + compatible = "amarula,a64-relic", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 6dd48c0265..603dc1287e 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -116,6 +116,12 @@ M: Paul Kocialkowski <contact(a)paulk.fr> S: Maintained F: configs/Ainol_AW1_defconfig +AMARULA A64 RELIC +M: Jagan Teki <jagan(a)amarulasolutions.com> +S: Maintained +F: configs/a64_relic_defconfig +F: arch/arm/dts/sun50i-a64-relic.dts + AMPE A76 BOARD M: Paul Kocialkowski <contact(a)paulk.fr> S: Maintained diff --git a/configs/a64_relic_defconfig b/configs/a64_relic_defconfig new file mode 100644 index 0000000000..385a11a437 --- /dev/null +++ b/configs/a64_relic_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I=y +CONFIG_DRAM_ODT_EN=y +CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-relic" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_VIDEO_DE2 is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_MUSB_GADGET=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -- 2.14.3

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[U-Boot] u-boot linker problem
by Dennis Jacobs 14 May '18

14 May '18

Dear U-boot mailing list During the development of a boot loader for a Marvel armv7-a Ethernet switch (98DX3235) I found a linker problem causing u-boot to not recognize any commands. Development tools: u-boot 2013.01 with 2016_T1.0.eng_drop_v6 Marvell modifications extracted over it. CROSS_COMPILER = armv7-marvell-linux-gnueabi-hard-4.6.4_64K_i686_20160226/bin/arm-marvell-linux-gnueabi- CROSS_COMPILE_BH = armv7-marvell-linux-gnueabi-hard-4.6.4_64K_i686_20160226/bin/arm-marvell-linux-gnueabi- To be clear I was able to compile, Load trough UART and even execute u-boot. Everything works fine until I get to the u-boot prompt line. I found out that no commands where recognized by u-boot because the commands are not listed in the right address category. u-boot searches in a list between 2 address locations, _u_boot_list_cmd__end and _u_boot_list_cmd__start. As you can see in the following address list created by u-boot called System.map, The commands are not sorted between the earlier mentioned address locations -----------------------------System.map----------------------------- 3076 000b6cd4 D _u_boot_list__end 3077 000b6cd4 D _u_boot_list_cmd_Creset 3078 000b6cf0 D _u_boot_list_cmd_SatR 3079 000b6d0c D _u_boot_list_cmd_active_units 3080 000b6d28 D _u_boot_list_cmd_base 3081 000b6d44 D _u_boot_list_cmd_bdinfo 3082 000b6d60 D _u_boot_list_cmd_boot 3083 000b6d7c D _u_boot_list_cmd_bootd < " " more commands in list" "> 3193 000b7984 D _u_boot_list_cmd_ubifsmount 3194 000b79a0 D _u_boot_list_cmd_ubifsumount 3195 000b79bc D _u_boot_list_cmd_usb 3196 000b79d8 D _u_boot_list_cmd_usbboot 3197 000b79f4 D _u_boot_list_cmd_version 3198 000b7a10 D _u_boot_list_cmd_whoAmI 3199 000b7a2c D _u_boot_list_env_clbk_baudrate 3200 000b7a34 D _u_boot_list_env_clbk_bootfile 3201 000b7a3c D _u_boot_list_env_clbk_callbacks 3202 000b7a44 D _u_boot_list_env_clbk_console 3203 000b7a4c D _u_boot_list_env_clbk_flags 3204 000b7a54 D _u_boot_list_env_clbk_loadaddr 3205 000b7a5c A __image_copy_end 3206 000b7a5c B __bss_start 3207 000b7a5c D _u_boot_list__start 3208 000b7a5c D _u_boot_list_cmd__end 3209 000b7a5c D _u_boot_list_cmd__start 3210 000b7a5c D _u_boot_list_env_clbk__end 3211 000b7a5c D _u_boot_list_env_clbk__start -------------------------------------------------------------------------- The following code form include/u-boot.lst shows that the commands should be sorted between the earlier mentioned addresses but they are not. -----------------------------include/u-boot.lst----------------------------- 1 _u_boot_list__end = .; 2 *(SORT(.u_boot_list.*)); 3 _u_boot_list__start = .; 4 _u_boot_list_cmd__end = .; 5 *(SORT(.u_boot_list.cmd.*)); 6 _u_boot_list_cmd__start = .; 7 _u_boot_list_env_clbk__end = .; 8 *(SORT(.u_boot_list.env_clbk.*)); 9 _u_boot_list_env_clbk__start = .; ------------------------------------------------------------------------------------- I would like you to rank posible solutions listed below - Am I using the wrong cross compiler? - Should I not use the same cross compiler for u-boot and the binary header? - Should the sorting order be ending with the sorting of u_boot_list prefixes so the others get sorted first? - Do you have another possible solution? Great thanks for all help of the u-boot mailing list Kind regards, Dennis Jacobs

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[U-Boot] [PATCH v2] timer: Add Cadence TTC timer counter support
by Michal Simek 14 May '18

14 May '18

This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Remove tabs from U_BOOT_DRIVER MAINTAINERS | 1 + drivers/timer/Kconfig | 7 +++ drivers/timer/Makefile | 1 + drivers/timer/cadence-ttc.c | 91 +++++++++++++++++++++++++++++++++++++ 4 files changed, 100 insertions(+) create mode 100644 drivers/timer/cadence-ttc.c diff --git a/MAINTAINERS b/MAINTAINERS index 60d4adf26664..5b139e51acf1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -288,6 +288,7 @@ F: drivers/net/zynq_gem.c F: drivers/serial/serial_zynq.c F: drivers/spi/zynq_qspi.c F: drivers/spi/zynq_spi.c +F: drivers/timer/cadence-ttc.c F: drivers/usb/host/ehci-zynq.c F: drivers/watchdog/cdns_wdt.c F: include/zynqmppl.h diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 2c9689672627..8a31397553df 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -52,6 +52,13 @@ config ATMEL_PIT_TIMER it is designed to offer maximum accuracy and efficient management, even for systems with long response time. +config CADENCE_TTC_TIMER + bool "Cadence TTC (Triple Timer Counter)" + depends on TIMER + help + Enables support for the cadence ttc driver. This driver is present + on Xilinx Zynq and ZynqMP SoCs. + config SANDBOX_TIMER bool "Sandbox timer support" depends on SANDBOX && TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index a8b531ab7b2b..ee2fcb1fa716 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -4,6 +4,7 @@ obj-y += timer-uclass.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o +obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c new file mode 100644 index 000000000000..5b91c8a90b34 --- /dev/null +++ b/drivers/timer/cadence-ttc.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Xilinx, Inc. (Michal Simek) + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> +#include <asm/io.h> + +#define CNT_CNTRL_RESET BIT(4) + +struct cadence_ttc_regs { + u32 clk_cntrl1; /* 0x0 - Clock Control 1 */ + u32 clk_cntrl2; /* 0x4 - Clock Control 2 */ + u32 clk_cntrl3; /* 0x8 - Clock Control 3 */ + u32 counter_cntrl1; /* 0xC - Counter Control 1 */ + u32 counter_cntrl2; /* 0x10 - Counter Control 2 */ + u32 counter_cntrl3; /* 0x14 - Counter Control 3 */ + u32 counter_val1; /* 0x18 - Counter Control 1 */ + u32 counter_val2; /* 0x1C - Counter Control 2 */ + u32 counter_val3; /* 0x20 - Counter Control 3 */ + u32 reserved[15]; + u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */ + u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */ + u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */ +}; + +struct cadence_ttc_priv { + struct cadence_ttc_regs *regs; +}; + +static int cadence_ttc_get_count(struct udevice *dev, u64 *count) +{ + struct cadence_ttc_priv *priv = dev_get_priv(dev); + + *count = readl(&priv->regs->counter_val1); + + return 0; +} + +static int cadence_ttc_probe(struct udevice *dev) +{ + struct cadence_ttc_priv *priv = dev_get_priv(dev); + + /* Disable interrupts for sure */ + writel(0, &priv->regs->interrupt_enable1); + writel(0, &priv->regs->interrupt_enable2); + writel(0, &priv->regs->interrupt_enable3); + + /* Make sure that clocks are configured properly without prescaller */ + writel(0, &priv->regs->clk_cntrl1); + writel(0, &priv->regs->clk_cntrl2); + writel(0, &priv->regs->clk_cntrl3); + + /* Reset and enable this counter */ + writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1); + + return 0; +} + +static int cadence_ttc_ofdata_to_platdata(struct udevice *dev) +{ + struct cadence_ttc_priv *priv = dev_get_priv(dev); + + priv->regs = map_physmem(devfdt_get_addr(dev), + sizeof(struct cadence_ttc_regs), MAP_NOCACHE); + + return 0; +} + +static const struct timer_ops cadence_ttc_ops = { + .get_count = cadence_ttc_get_count, +}; + +static const struct udevice_id cadence_ttc_ids[] = { + { .compatible = "cdns,ttc" }, + {} +}; + +U_BOOT_DRIVER(cadence_ttc) = { + .name = "cadence_ttc", + .id = UCLASS_TIMER, + .of_match = cadence_ttc_ids, + .ofdata_to_platdata = cadence_ttc_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct cadence_ttc_priv), + .probe = cadence_ttc_probe, + .ops = &cadence_ttc_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- 2.17.0

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[U-Boot] [GIT] Pull request: u-boot-dfu (13.05.2018)
by Lukasz Majewski 13 May '18

13 May '18

Dear Marek, Travis CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/378387230 The following changes since commit 62d77cea31216cad526e5f45c88e8377efc6fcae: mmc: Improve tinification (2018-05-13 07:57:32 -0400) are available in the git repository at: git://git.denx.de/u-boot-dfu.git for you to fetch changes up to 8780dca82fa6c5dbf264acf78140d39d8ed4acc2: gadget: f_thor: update to support more than 4GB file as thor 5.0 (2018-05-13 17:07:06 +0200) ---------------------------------------------------------------- Seung-Woo Kim (2): gadget: f_thor: fix filename overflow gadget: f_thor: update to support more than 4GB file as thor 5.0 drivers/usb/gadget/f_thor.c | 13 +++++++++---- drivers/usb/gadget/f_thor.h | 2 +- 2 files changed, 10 insertions(+), 5 deletions(-) Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de

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[U-Boot] [PATCH 0/3] fpga: zynqmp: Fpga changes
by Michal Simek 13 May '18

13 May '18

Hi, these patches are syncing latest firmware expectation and showing information about fpga status. Thanks, Michal Nitin Jain (1): fpga: zynqmp: Add support to get the PCAP status for fpga info command Siva Durga Prasad Paladugu (2): fpga: zynqmp: Update zynqmp_load() as per latest xilfpga fpga: zynqmp: Fix the nonsecure bitstream loading issue arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 ++ drivers/fpga/zynqmppl.c | 28 +++++++++++++++++++++------- include/zynqmppl.h | 1 + 3 files changed, 24 insertions(+), 7 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] mx6: remove duplicated BOUNCE_BUFFER defines
by Peter Robinson 13 May '18

13 May '18

The mx6_common.h file already defines BOUNCE_BUFFER so no need to definit it again in specific configs. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- include/configs/advantech_dms-ba16.h | 1 - include/configs/apalis_imx6.h | 1 - include/configs/colibri_imx6.h | 1 - include/configs/dh_imx6.h | 1 - include/configs/ge_bx50v3.h | 1 - include/configs/kp_imx6q_tpc.h | 2 -- 6 files changed, 7 deletions(-) diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index a6e99192ba..8e33d38f97 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -45,7 +45,6 @@ /* MMC Configs */ #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_BOUNCE_BUFFER /* USB Configs */ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 00255c80d6..7225c03ac5 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -56,7 +56,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_BOUNCE_BUFFER /* * SATA Configs diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 49ec0bf108..7e3463e184 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_BOUNCE_BUFFER /* Network */ #define CONFIG_FEC_MXC diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 24b35161b6..3e0ac15229 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -33,7 +33,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_BOUNCE_BUFFER #define CONFIG_BZIP2 /* Size of malloc() pool */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 32631a20c3..424c0dd1d0 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -62,7 +62,6 @@ /* MMC Configs */ #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_BOUNCE_BUFFER /* USB Configs */ #ifdef CONFIG_USB diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index d243fc675f..bf3cc174cd 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -21,8 +21,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_BOUNCE_BUFFER - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) -- 2.17.0

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