November 2018 - U-Boot

[U-Boot] Please pull u-boot/master
by Stefan Roese 06 Nov '18

06 Nov '18

Hi Tom, could you please pull these MVEBU fixes for the upcoming release? Thanks, Stefan The following changes since commit 5ef76e59c12c79d106ebda70b710468aa6bd8b75: Merge branch 'master' of git://git.denx.de/u-boot-sh (2018-11-04 08:12:21 -0500) are available in the Git repository at: git://www.denx.de/git/u-boot-marvell.git for you to fetch changes up to ae4c38a5384033c7f5584e33cce1adc511fff333: arm: mvebu: armada-xp-theadorable.dts: Change CS# for 2nd FPGA (2018-11-06 13:21:13 +0100) ---------------------------------------------------------------- Stefan Roese (3): arm: mvebu: Move PCI(e) MBUS window to end of RAM arm: mvebu: armada-xp-theadorable.dts: Add "spi-flash" compatible property arm: mvebu: armada-xp-theadorable.dts: Change CS# for 2nd FPGA arch/arm/dts/armada-xp-theadorable.dts | 6 +++--- arch/arm/mach-mvebu/dram.c | 10 ++++++---- arch/arm/mach-mvebu/include/mach/cpu.h | 4 +++- 3 files changed, 12 insertions(+), 8 deletions(-)

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[U-Boot] Please pull u-boot-x86
by Bin Meng 06 Nov '18

06 Nov '18

Hi Tom, This contains a fix to a warning by newer version IASL compiler. The following changes since commit 5ef76e59c12c79d106ebda70b710468aa6bd8b75: Merge branch 'master' of git://git.denx.de/u-boot-sh (2018-11-04 08:12:21 -0500) are available in the git repository at: git://git.denx.de/u-boot-x86.git for you to fetch changes up to 24109bba6a4f81774e384c15c2e8a4d47791455f: x86: acpi: Remove redundant Offset (0x00) (2018-11-06 13:35:06 +0800) ---------------------------------------------------------------- Andy Shevchenko (1): x86: acpi: Remove redundant Offset (0x00) arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl | 1 - arch/x86/include/asm/arch-quark/acpi/global_nvs.asl | 1 - arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl | 1 - 3 files changed, 3 deletions(-) Regards, Bin

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[U-Boot] [PATCH v2 1/2] cpu: Add DM_FLAG_PRE_RELOC flag to various cpu drivers
by Bin Meng 06 Nov '18

06 Nov '18

It turns out commit c0434407b595 broke some boards which have DM CPU driver with CONFIG_DISPLAY_CPUINFO option on. These boards just fail to boot when print_cpuinfo() is called during boot. Fixes: c0434407b595 ("board_f: Use static print_cpuinfo if CONFIG_CPU is active") Reported-by: Stefan Roese <sr(a)denx.de> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - drop the sandbox cpu driver change arch/x86/cpu/baytrail/cpu.c | 1 + arch/x86/cpu/broadwell/cpu.c | 1 + arch/x86/cpu/cpu_x86.c | 1 + arch/x86/cpu/ivybridge/model_206ax.c | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 56e9813..2eb9172 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -203,4 +203,5 @@ U_BOOT_DRIVER(cpu_x86_baytrail_drv) = { .bind = cpu_x86_bind, .probe = cpu_x86_baytrail_probe, .ops = &cpu_x86_baytrail_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 02b3169..232fa40 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -764,4 +764,5 @@ U_BOOT_DRIVER(cpu_x86_broadwell_drv) = { .probe = cpu_x86_broadwell_probe, .ops = &cpu_x86_broadwell_ops, .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv), + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 2b6cc9f..1aaf851 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -94,4 +94,5 @@ U_BOOT_DRIVER(cpu_x86_drv) = { .of_match = cpu_x86_ids, .bind = cpu_x86_bind, .ops = &cpu_x86_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 33e5c62..6edc3e2 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -478,4 +478,5 @@ U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = { .bind = cpu_x86_bind, .probe = cpu_x86_model_206ax_probe, .ops = &cpu_x86_model_206ax_ops, + .flags = DM_FLAG_PRE_RELOC, }; -- 2.7.4

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[U-Boot] Pull request: u-boot-net.git master
by Joe Hershberger 06 Nov '18

06 Nov '18

Hi Tom, Built successfully on Travis: https://travis-ci.org/jhershbe/u-boot/builds/450020193 The following changes since commit 5ef76e59c12c79d106ebda70b710468aa6bd8b75: Merge branch 'master' of git://git.denx.de/u-boot-sh (2018-11-04 08:12:21 -0500) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to 79d8127168e211f4745bd2183a3338c6c4e2d003: driver: net: ti: keystone_net: switch to use common mdio lib (2018-11-05 10:42:01 -0600) ---------------------------------------------------------------- Cédric Le Goater (13): net: ftgmac100: use the BIT() macro net: ftgmac100: use the aligned() macro net: ftgmac100: convert to driver model net: ftgmac100: use setbits_le32() in the reset method net: ftgmac100: add MDIO bus and phylib support net: ftgmac100: convert the RX/TX descriptor arrays net: ftgmac100: handle timeouts when transmitting net: ftgmac100: add clock support aspeed: ast2500: fix missing break in D2PLL clock enablement net: ftgmac100: Add support for the Aspeed SoC aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level aspeed: Activate ethernet devices on the ast2500 Eval Board aspeed: ast2500: fix D2-PLL clock setting in RGMII mode Grygorii Strashko (7): driver: net: consolidate ti's code in separate folder configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig drivers: net: keystone_net: drop non dm code driver: net: ti: cpsw: update to use SPDX identifier driver: net: ti: introduce common mdio support library driver: net: ti: cpsw: switch to use common mdio lib driver: net: ti: keystone_net: switch to use common mdio lib Quentin Schulz (3): net: phy: mscc: add support for VSC8584 PHY net: phy: mscc: factorize part of config function for VSC8584 net: phy: mscc: add support for VSC8574 PHY Stefan Roese (1): net: Add MT7628 ethernet driver arch/arm/dts/ast2500-evb.dts | 23 + arch/arm/dts/ast2500.dtsi | 1949 ++++++++++++-------- arch/arm/include/asm/ti-common/keystone_net.h | 27 - arch/arm/mach-davinci/dp83848.c | 2 +- arch/arm/mach-davinci/et1011c.c | 2 +- arch/arm/mach-davinci/ksz8873.c | 2 +- arch/arm/mach-davinci/lxt972.c | 2 +- board/ti/ks2_evm/board.c | 53 - board/ti/ks2_evm/board.h | 3 - board/ti/ks2_evm/board_k2e.c | 74 - board/ti/ks2_evm/board_k2g.c | 18 - board/ti/ks2_evm/board_k2hk.c | 42 - board/ti/ks2_evm/board_k2l.c | 42 - configs/evb-ast2500_defconfig | 8 + configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + .../net/mediatek,mt7628-eth.txt | 17 + drivers/clk/aspeed/clk_ast2500.c | 39 + drivers/net/Kconfig | 45 +- drivers/net/Makefile | 5 +- drivers/net/ftgmac100.c | 732 ++++---- drivers/net/ftgmac100.h | 158 +- drivers/net/mt7628-eth.c | 644 +++++++ drivers/net/phy/mscc.c | 995 ++++++++++ drivers/net/ti/Kconfig | 20 + drivers/net/ti/Makefile | 7 + drivers/net/{ => ti}/cpsw-common.c | 0 drivers/net/{ => ti}/cpsw.c | 146 +- drivers/net/ti/cpsw_mdio.c | 203 ++ drivers/net/ti/cpsw_mdio.h | 18 + drivers/net/{ => ti}/davinci_emac.c | 0 drivers/net/{ => ti}/davinci_emac.h | 0 drivers/net/{ => ti}/keystone_net.c | 401 +--- include/configs/ti_armv7_keystone2.h | 1 - include/netdev.h | 1 - 41 files changed, 3657 insertions(+), 2030 deletions(-) create mode 100644 doc/device-tree-bindings/net/mediatek,mt7628-eth.txt create mode 100644 drivers/net/mt7628-eth.c create mode 100644 drivers/net/ti/Kconfig create mode 100644 drivers/net/ti/Makefile rename drivers/net/{ => ti}/cpsw-common.c (100%) rename drivers/net/{ => ti}/cpsw.c (90%) create mode 100644 drivers/net/ti/cpsw_mdio.c create mode 100644 drivers/net/ti/cpsw_mdio.h rename drivers/net/{ => ti}/davinci_emac.c (100%) rename drivers/net/{ => ti}/davinci_emac.h (100%) rename drivers/net/{ => ti}/keystone_net.c (68%) Thanks! -Joe

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[U-Boot] [PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]
by Andes 06 Nov '18

06 Nov '18

From: Rick Chen <rick(a)andestech.com> AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick(a)andestech.com> Cc: Greentime Hu <greentime(a)andestech.com> --- arch/riscv/Kconfig | 8 ++++ arch/riscv/cpu/ax25/Makefile | 1 + arch/riscv/cpu/ax25/cache.c | 89 ++++++++++++++++++++++++++++++++++++++++++ arch/riscv/cpu/ax25/cpu.c | 4 ++ arch/riscv/cpu/qemu/cpu.c | 2 +- arch/riscv/cpu/start.S | 6 +++ arch/riscv/include/asm/cache.h | 9 +++++ arch/riscv/lib/cache.c | 30 +++++++++----- 8 files changed, 138 insertions(+), 11 deletions(-) create mode 100644 arch/riscv/cpu/ax25/cache.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 371921b..a356729 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -74,4 +74,12 @@ config 32BIT config 64BIT bool +config RISCV_NDS + bool "AndeStar V5 ISA support" + default n + help + Say Y here if you plan to run U-Boot on AndeStar v5 + platforms and use some specific features which are + provided by Andes Technology AndeStar V5 Families. + endmenu diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile index 2ab0342..318bacc 100644 --- a/arch/riscv/cpu/ax25/Makefile +++ b/arch/riscv/cpu/ax25/Makefile @@ -4,3 +4,4 @@ # Rick Chen, Andes Technology Corporation <rick(a)andestech.com> obj-y := cpu.o +obj-y += cache.o diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c new file mode 100644 index 0000000..e0bcaa2 --- /dev/null +++ b/arch/riscv/cpu/ax25/cache.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <rick(a)andestech.com> + */ + +#include <common.h> + +void icache_enable(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "ori t0, t1, 0x1\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +#endif +} + +void icache_disable(void) +{ +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "andi t0, t1, ~0x1\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +} + +void dcache_enable(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "ori t0, t1, 0x2\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +#endif +} + +void dcache_disable(void) +{ +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "andi t0, t1, ~0x2\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +} + +int icache_status(void) +{ + int ret = 0; + +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "andi %0, t1, 0x01\n\t" + : "=r" (ret) + : + : "memory" + ); +#endif + + return ret; +} + +int dcache_status(void) +{ + int ret = 0; + +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "andi %0, t1, 0x02\n\t" + : "=r" (ret) + : + : "memory" + ); +#endif + + return ret; +} diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index fddcc15..76689b2 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -6,6 +6,7 @@ /* CPU specific code */ #include <common.h> +#include <asm/cache.h> /* * cleanup_before_linux() is called just before we call linux @@ -18,6 +19,9 @@ int cleanup_before_linux(void) disable_interrupts(); /* turn off I/D-cache */ + cache_flush(); + icache_disable(); + dcache_disable(); return 0; } diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c index 6c7a327..25d97d0 100644 --- a/arch/riscv/cpu/qemu/cpu.c +++ b/arch/riscv/cpu/qemu/cpu.c @@ -15,7 +15,7 @@ int cleanup_before_linux(void) { disable_interrupts(); - /* turn off I/D-cache */ + cache_flush(); return 0; } diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 331a534..0e21679 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -46,6 +46,10 @@ _start: /* mask all interrupts */ csrw mie, zero +/* Enable cache */ +jal icache_enable +jal dcache_enable + /* * Set stackpointer in internal/ex RAM to call board_init_f */ @@ -181,6 +185,8 @@ clbss_l: * initialization, now running from RAM. */ call_board_init_r: + jal invalidate_icache_all + jal flush_dcache_all la t0, board_init_r mv t4, t0 /* offset of board_init_r() */ add t4, t4, t6 /* real address of board_init_r() */ diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index ca83dd6..e76ca13 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -7,6 +7,15 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +/* cache */ +int icache_status(void); +void icache_enable(void); +void icache_disable(void); +int dcache_status(void); +void dcache_enable(void); +void dcache_disable(void); +void cache_flush(void); + /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. * We use that value for aligning DMA buffers unless the board config has diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index d642a38..121db09 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -6,6 +6,15 @@ #include <common.h> +void invalidate_icache_all(void) +{ + asm volatile ("fence.i" ::: "memory"); +} + +void flush_dcache_all(void) +{ + asm volatile("fence" :::"memory"); +} void flush_dcache_range(unsigned long start, unsigned long end) { } @@ -19,41 +28,42 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); } -void invalidate_icache_all(void) +void invalidate_dcache_range(unsigned long start, unsigned long end) { - asm volatile ("fence.i" ::: "memory"); } -void invalidate_dcache_range(unsigned long start, unsigned long end) +void cache_flush(void) { + invalidate_icache_all(); + flush_dcache_all(); } -void flush_cache(unsigned long addr, unsigned long size) +__weak void flush_cache(unsigned long addr, unsigned long size) { } -void icache_enable(void) +__weak void icache_enable(void) { } -void icache_disable(void) +__weak void icache_disable(void) { } -int icache_status(void) +__weak int icache_status(void) { return 0; } -void dcache_enable(void) +__weak void dcache_enable(void) { } -void dcache_disable(void) +__weak void dcache_disable(void) { } -int dcache_status(void) +__weak int dcache_status(void) { return 0; } -- 2.7.4

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[U-Boot] SPI in U-Boot on Raspberry Pi for TPM 2.0
by Torben 06 Nov '18

06 Nov '18

Hi, does anyone know, if it is possible to use SPI in U-Boot on a Raspberry Pi 3 Model B? What I'm trying to achieve: - Connect a TPM 2.0 via SPI to the Raspberry Pi and communicate with it What I already have: - Compiled U-Boot with support for Raspberry Pi 3 Model B; I can access the console and I can boot Raspbian from the SD-card Questions / Problems: - How do I activate SPI support? I have enabled CONFIG_SPI, CONFIG_CMD_SPI and CONFIG_DM_SPI. I guess, I'd have also have to enable some Raspberry Pi specific SPI driver to make it work? -> It seems like there is no driver for it, yet? (as far as I understand this: there would need to be a bcm2835 SPI driver, right?) -> Would it be possible to alternatively use the SOFT_SPI driver (maybe that's also the easier way?)? (because it seems like one can access the GPIOs from U-Boot already, so that seems to be implemented) However, I can't find much about how this needs to be setup. BTW the U-Boot README references to the file "include/configs/sacsng.h" for an example, but that file doesn't exist anymore in the current master. Thanks! Torben

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[U-Boot] [PATCH] spi: Zap mpc8xx_spi driver
by Jagan Teki 06 Nov '18

06 Nov '18

- Driver not used by any boards - No update on 'dm conversion' Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/spi/Kconfig | 6 - drivers/spi/Makefile | 1 - drivers/spi/mpc8xx_spi.c | 336 ----------------------------------------------- 3 files changed, 343 deletions(-) delete mode 100644 drivers/spi/mpc8xx_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 235a8c7d73..fd3f115ccf 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -274,12 +274,6 @@ config LPC32XX_SSP help Enable support for SPI on LPC32xx -config MPC8XX_SPI - bool "MPC8XX SPI Driver" - depends on 8xx - help - Enable support for SPI on MPC8XX - config MPC8XXX_SPI bool "MPC8XXX SPI Driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4b6000fd9a..f104836630 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o -obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c deleted file mode 100644 index b5bd558526..0000000000 --- a/drivers/spi/mpc8xx_spi.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * <nboppuri(a)trinetcommunication.com>, - * <pmpatel(a)trinetcommunication.com> - * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen(a)icn.siemens.de> - * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de>. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8xx CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd(a)denx.de - * - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <linux/ctype.h> -#include <malloc.h> -#include <post.h> -#include <serial.h> - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0xb00 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CONFIG_SYS_SPI_INIT_OFFSET -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 -#endif - -#define CPM_SPI_BASE_RX CPM_SPI_BASE -#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t)) - -/* ------------------- - * Function prototypes - * ------------------- */ -ssize_t spi_xfer(size_t); - -/* ------------------- - * Variables - * ------------------- */ - -#define MAX_BUFFER 0x104 - -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f(void) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - -/* 1 */ - /* ------------------------------------------------ - * Initialize Port B SPI pins -> page 34-8 MPC860UM - * (we are only in Master Mode !) - * ------------------------------------------------ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO) - * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI) - * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK) - * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM) - * -------------------------------------------- */ - clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */ - - /* ---------------------------------------------- - * In/Out or per. Function 0/1 - * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO - * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI - * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK - * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM - * ---------------------------------------------- */ - setbits_be32(&cp->cp_pbdir, 0x0000000F); - - /* ---------------------------------------------- - * open drain or active output - * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO - * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI - * PBODR[30] = 0 [0x00000002] -> active output: SPICLK - * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM - * ---------------------------------------------- */ - - clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008); - - /* Initialize the parameter ram. - * We need to make sure many things are initialized to zero - */ - out_be32(&spi->spi_rstate, 0); - out_be32(&spi->spi_rdp, 0); - out_be16(&spi->spi_rbptr, 0); - out_be16(&spi->spi_rbc, 0); - out_be32(&spi->spi_rxtmp, 0); - out_be32(&spi->spi_tstate, 0); - out_be32(&spi->spi_tdp, 0); - out_be16(&spi->spi_tbptr, 0); - out_be16(&spi->spi_tbc, 0); - out_be32(&spi->spi_txtmp, 0); - -/* 3 */ - /* Set up the SPI parameters in the parameter ram */ - out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX); - out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX); - - /***********IMPORTANT******************/ - - /* - * Setting transmit and receive buffer descriptor pointers - * initially to rbase and tbase. Only the microcode patches - * documentation talks about initializing this pointer. This - * is missing from the sample I2C driver. If you dont - * initialize these pointers, the kernel hangs. - */ - out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX); - out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX); - -/* 4 */ - /* Init SPI Tx + Rx Parameters */ - while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) - ; - - out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | - CPM_CR_FLG); - while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) - ; - -/* 5 */ - /* Set SDMA configuration register */ - out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); - -/* 6 */ - /* Set to big endian. */ - out_8(&spi->spi_tfcr, SMC_EB); - out_8(&spi->spi_rfcr, SMC_EB); - -/* 7 */ - /* Set maximum receive size. */ - out_be16(&spi->spi_mrblr, MAX_BUFFER); - -/* 8 + 9 */ - /* tx and rx buffer descriptors */ - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - clrbits_be16(&tbdf->cbd_sc, BD_SC_READY); - clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY); - - /* Set the bd's rx and tx buffer address pointers */ - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - -/* 10 + 11 */ - out_8(&cp->cp_spim, 0); /* Mask all SPI events */ - out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ - - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r(void) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *)malloc(MAX_BUFFER); - txbuf = (uchar *)malloc(MAX_BUFFER); - - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) - break; - udelay(1000); - } - if (i >= 1000) - printf("*** spi_write: Time out while writing!\n"); - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer(size_t count) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - int tm; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - /* Set CS for device */ - clrbits_be32(&cp->cp_pbdat, 0x0001); - - /* Setting tx bd status and data length */ - out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP); - out_be16(&tbdf->cbd_datlen, count); - - /* Setting rx bd status and data length */ - out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); - out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */ - - clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR | - SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8)); - out_8(&cp->cp_spim, 0); /* Mask all SPI events */ - out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ - - /* start spi transfer */ - setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm = 0; tm < 1000; ++tm) { - if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */ - break; - if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0) - break; - udelay(1000); - } - if (tm >= 1000) - printf("*** spi_xfer: Time out while xferring to/from SPI!\n"); - - /* Clear CS for device */ - setbits_be32(&cp->cp_pbdat, 0x0001); - - return count; -} -- 2.14.3

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[U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2
by Michal Simek 06 Nov '18

06 Nov '18

Hi Tom, please consider to pull these patches to your tree. Buildmain for xilinx boards looks good and travis is not done yet but link is here (I have seen several timeouts recently but it was there even on clear mainline). https://travis-ci.org/michalsimek/u-boot/builds/441591781 If you don't like this please at least cherry-pick this one Revert "fdt: fdtdec_setup_memory_banksize() use livetree" (sha1: 01ac0843aeedc3c95fe68e7ce6a8f35bf1a04b23) which I need for getting SPL up and running again on zynq/zynqmp boards. Thanks, Michal The following changes since commit 15f22ac2eea5ee9f17b14a143c94e7480bbafbff: ldpaa_eth.c: Fix warning when PHYLIB is not enabled (2018-10-12 07:41:24 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.11-rc2 for you to fetch changes up to 045c62be10d64a558f56febcaa2d01b1abbcfa00: cmd: kgdb: Enable kgdb only for PPC (2018-10-15 12:36:37 +0200) ---------------------------------------------------------------- Xilinx changes for v2018.11-rc2 FPGA: - Fix SPL fpga loading from FIT ARM64: - Fix gic accesses in EL2/EL1 Xilinx: - Add dlc20 board support - Add Versal board support - Sync defconfigs - Enable MP via Kconfig - Add missing efuse node - Enable CDC for zcu100 cmd: - Fix kgdb Kconfig dependency serial-pl01x: - Add support for handling clk from DT ---------------------------------------------------------------- Michal Simek (13): spl: fpga: Implement fpga bistream loading with fpga_load arm: zynq: Enable FIT fpga loading in SPL for zc706 arm: zynq: Add support for DLC20 board Revert "fdt: fdtdec_setup_memory_banksize() use livetree" arm: zynq: Add efuse node for Zynq-7000S devices xilinx: Sync defconfigs with current Kconfig arm64: zynqmp: Enable CDC ethernet gadget for zcu100/Ultra96 arm64: gic: Do gicv3 secure initialization based on EL level arm64: versal: Add support for new Xilinx Versal ACAPs net: gem: Do not setup any clock for Xilinx SoC Versal arm64: versal: Add Xilinx Versal Virtual QEMU board arm64: zynqmp: Enable MP by default via Kconfig cmd: kgdb: Enable kgdb only for PPC Siva Durga Prasad Paladugu (3): serial: pl01x: Get clock from clock node if no clock property found arm64: zynqmp: Move TCM initialization to a separate routine arm64: zynqmp: Add new command for TCM initialization Kconfig | 2 +- MAINTAINERS | 6 ++++ arch/arm/Kconfig | 11 +++++++ arch/arm/Makefile | 1 + arch/arm/cpu/armv8/zynqmp/cpu.c | 12 +++++-- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-7000.dtsi | 5 +++ arch/arm/dts/zynq-dlc20-rev1.0.dts | 103 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-zynqmp/sys_proto.h | 3 ++ arch/arm/lib/gic_64.S | 16 +++++---- arch/arm/mach-versal/Kconfig | 44 +++++++++++++++++++++++++ arch/arm/mach-versal/Makefile | 8 +++++ arch/arm/mach-versal/clk.c | 30 +++++++++++++++++ arch/arm/mach-versal/cpu.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-versal/include/mach/gpio.h | 6 ++++ arch/arm/mach-versal/include/mach/hardware.h | 34 +++++++++++++++++++ arch/arm/mach-versal/include/mach/sys_proto.h | 6 ++++ board/xilinx/versal/MAINTAINERS | 7 ++++ board/xilinx/versal/Makefile | 7 ++++ board/xilinx/versal/board.c | 81 +++++++++++++++++++++++++++++++++++++++++++++ board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c | 280 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/xilinx/zynqmp/cmds.c | 37 ++++++++++++++++++++- cmd/Kconfig | 1 + common/spl/spl_fit.c | 34 +++++++++---------- configs/avnet_ultra96_rev1_defconfig | 8 +++-- configs/microblaze-generic_defconfig | 2 +- configs/xilinx_versal_virt_defconfig | 68 ++++++++++++++++++++++++++++++++++++++ configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_defconfig | 1 + configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 8 +++-- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - configs/zynq_dlc20_rev1_0_defconfig | 74 +++++++++++++++++++++++++++++++++++++++++ configs/zynq_zc706_defconfig | 4 +++ drivers/mmc/Kconfig | 2 +- drivers/net/Kconfig | 2 +- drivers/net/zynq_gem.c | 4 +++ drivers/serial/serial_pl01x.c | 26 +++++++++++++++ drivers/spi/Kconfig | 4 +-- env/Kconfig | 4 +-- include/configs/xilinx_versal.h | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/fdtdec.c | 44 +++++++++++++------------ 58 files changed, 1101 insertions(+), 78 deletions(-) create mode 100644 arch/arm/dts/zynq-dlc20-rev1.0.dts create mode 100644 arch/arm/mach-versal/Kconfig create mode 100644 arch/arm/mach-versal/Makefile create mode 100644 arch/arm/mach-versal/clk.c create mode 100644 arch/arm/mach-versal/cpu.c create mode 100644 arch/arm/mach-versal/include/mach/gpio.h create mode 100644 arch/arm/mach-versal/include/mach/hardware.h create mode 100644 arch/arm/mach-versal/include/mach/sys_proto.h create mode 100644 board/xilinx/versal/MAINTAINERS create mode 100644 board/xilinx/versal/Makefile create mode 100644 board/xilinx/versal/board.c create mode 100644 board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c create mode 100644 configs/xilinx_versal_virt_defconfig create mode 100644 configs/zynq_dlc20_rev1_0_defconfig create mode 100644 include/configs/xilinx_versal.h

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[U-Boot] [PATCH V2 1/4] tools: imx8image: check lseek return value
by Peng Fan 06 Nov '18

06 Nov '18

Check lseek return value. Fix Coverity CID: 184236 184235 184232 Reported-by: Coverity Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- V2: Per Fabio's comments, use ret = lseek; if (ret) < 0) coding style. tools/imx8image.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/tools/imx8image.c b/tools/imx8image.c index e6b0a146b6..03debe547e 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -301,6 +301,7 @@ static void copy_file_aligned(int ifd, const char *datafile, int offset, unsigned char *ptr; uint8_t zeros[0x4000]; int size; + int ret; if (align > 0x4000) { fprintf(stderr, "Wrong alignment requested %d\n", align); @@ -333,7 +334,13 @@ static void copy_file_aligned(int ifd, const char *datafile, int offset, } size = sbuf.st_size; - lseek(ifd, offset, SEEK_SET); + ret = lseek(ifd, offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "%s: lseek error %s\n", + __func__, strerror(errno)); + exit(EXIT_FAILURE); + } + if (write(ifd, ptr, size) != size) { fprintf(stderr, "Write error %s\n", strerror(errno)); exit(EXIT_FAILURE); @@ -359,7 +366,7 @@ static void copy_file (int ifd, const char *datafile, int pad, int offset) int tail; int zero = 0; uint8_t zeros[4096]; - int size; + int size, ret; memset(zeros, 0, sizeof(zeros)); @@ -387,7 +394,13 @@ static void copy_file (int ifd, const char *datafile, int pad, int offset) } size = sbuf.st_size; - lseek(ifd, offset, SEEK_SET); + ret = lseek(ifd, offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "%s: lseek error %s\n", + __func__, strerror(errno)); + exit(EXIT_FAILURE); + } + if (write(ifd, ptr, size) != size) { fprintf(stderr, "Write error %s\n", strerror(errno)); @@ -762,6 +775,7 @@ static int build_container(soc_type_t soc, uint32_t sector_size, char *tmp_filename = NULL; uint32_t size = 0; uint32_t file_padding = 0; + int ret; int container = -1; int cont_img_count = 0; /* indexes to arrange the container */ @@ -883,7 +897,12 @@ static int build_container(soc_type_t soc, uint32_t sector_size, } while (img_sp->option != NO_IMG); /* Add padding or skip appended container */ - lseek(ofd, file_padding, SEEK_SET); + ret = lseek(ofd, file_padding, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "%s: lseek error %s\n", + __func__, strerror(errno)); + exit(EXIT_FAILURE); + } /* Note: Image offset are not contained in the image */ tmp = flatten_container_header(&imx_header, container + 1, &size, -- 2.14.1

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[U-Boot] [PATCH v2 0/7] driver: net: ti: clean up and code optimization
by Grygorii Strashko 06 Nov '18

06 Nov '18

This series contains set of code clean up and optimizations for TI networking drivers. Patch 1 - Adds drivers/net/ti/ folder and moves all TI's networking code in this folder. Patches 2,3 - keystone2 clean up Patch 5 - introduces common TI MDIO support library as existing TI SoCs network HW IPs have similar MDIO implementation. Patches 6-7 - conversation of TI CPSW and keystone_net drivers to use common TI MDIO support library tested dhcp and kernel boot on: - k2e/g/hk/l evms - am437x-gpevm and AM5748 IDK changes in v2: - patch 5 comments fixed: use wait_for_bit, snprintf, mdelay, mdio_free TODO: TODO: As per code and documentation davinci_emac.c seems also can be re-worked to use common TI MDIO support library and network PHYs framework. Unfortunately, I have no HW to work with. Grygorii Strashko (7): driver: net: consolidate ti's code in separate folder configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig drivers: net: keystone_net: drop non dm code driver: net: ti: cpsw: update to use SPDX identifier driver: net: ti: introduce common mdio support library driver: net: ti: cpsw: switch to use common mdio lib driver: net: ti: keystone_net: switch to use common mdio lib arch/arm/include/asm/ti-common/keystone_net.h | 27 -- arch/arm/mach-davinci/dp83848.c | 2 +- arch/arm/mach-davinci/et1011c.c | 2 +- arch/arm/mach-davinci/ksz8873.c | 2 +- arch/arm/mach-davinci/lxt972.c | 2 +- board/ti/ks2_evm/board.c | 53 ---- board/ti/ks2_evm/board.h | 3 - board/ti/ks2_evm/board_k2e.c | 74 ----- board/ti/ks2_evm/board_k2g.c | 18 -- board/ti/ks2_evm/board_k2hk.c | 42 --- board/ti/ks2_evm/board_k2l.c | 42 --- configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + drivers/net/Kconfig | 13 +- drivers/net/Makefile | 4 +- drivers/net/ti/Kconfig | 20 ++ drivers/net/ti/Makefile | 7 + drivers/net/{ => ti}/cpsw-common.c | 0 drivers/net/{ => ti}/cpsw.c | 146 +--------- drivers/net/ti/cpsw_mdio.c | 201 +++++++++++++ drivers/net/ti/cpsw_mdio.h | 18 ++ drivers/net/{ => ti}/davinci_emac.c | 0 drivers/net/{ => ti}/davinci_emac.h | 0 drivers/net/{ => ti}/keystone_net.c | 401 +------------------------- include/configs/ti_armv7_keystone2.h | 1 - 31 files changed, 284 insertions(+), 802 deletions(-) create mode 100644 drivers/net/ti/Kconfig create mode 100644 drivers/net/ti/Makefile rename drivers/net/{ => ti}/cpsw-common.c (100%) rename drivers/net/{ => ti}/cpsw.c (90%) create mode 100644 drivers/net/ti/cpsw_mdio.c create mode 100644 drivers/net/ti/cpsw_mdio.h rename drivers/net/{ => ti}/davinci_emac.c (100%) rename drivers/net/{ => ti}/davinci_emac.h (100%) rename drivers/net/{ => ti}/keystone_net.c (68%) -- 2.10.5

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