October 2018 - U-Boot

[U-Boot] [PATCH v6 00/34] i.MX: Add i.MX8QXP support
by Anatolij Gustschin 07 Nov '18

07 Nov '18

This patchset is to upstream basic i.MX8QXP and MEK board support, with some drivers update to support i.MX8QXP. The information about the processor could be found under https://www.nxp.com/products/processors-and-microcontrollers/applications-p… The architecture of i.MX8QXP is different from i.MX6/7/8M, inside i.MX8QXP, there is a dedicated processor(SCU) used for power/clock/pin/ pad/resource management/thermal and etc. V6: This series was rebased on master and addresses some v5 review comments and additionally adds FEC support. Summary of the changes to v5 patches is below. Patch 08/32: - fixed error string: s/clk/iomux Patch 09/32: - minor coding style fix (dropped empty lines), added API functions for reading SCFW buildinfo and for reading MAC address from fuses Patch 18/32: - fixed typo in subject and one line over 80 chars warning Patch 19/32: - s/u-boot/U-Boot in comments Added two new patches (20/34 and 21/34) for adding uclass cpu driver and extension for reading MAC address from fuses (required for FEC driver) Extended original patch 25/32: - added support for more I2C/ENET/UART clocks, added 'clk dump' command - fixed to propagate error codes (if returned by sc_pm_* API) to the caller - fixed printf formatting in debug() - extended for clock ID range checks to differentiate between not yet supported and invalid clock IDs. Patch 28/32: - guard get_lpuart_clk_rate() by IS_ENABLED to prevent build issues Patch 30/32: - propagate error code if clk api calls fail Patch 31/32: - added FEC nodes and aliases Patch 32/32: In DTS: - added fec1 support, pca9646 switch description on i2c1 bus with i2c slaves - removed not used 'pinctrl-assert-gpios' property - s/lpi1cgrp/lpi2c1grp/ - added 'dm-pre-reloc' to cpu0 node (needed for print_cpuinfo()!) In board code: - reworked gpio init (repaced by init via properties in DTS), dropped GPIO5_9 mux init (was unused, will be added later when adding USB support) - added board_phy_config() for FEC0 support - added SCFW build info output - moved CONFIG_MXC_GPIO from board config header to defconfig - added required FEC driver options to the board config header - updated defconfig: enabled 'clk', 'cpu' and 'dm' commands, PHY, FEC, MII and MXC GPIO support V5: Addressed Lothar Waßmann's comments for patch 24 and 32. Rebased on master. V4: Add reviewed tag from Anatolij Gustschin Addressed comments from Anatolig for patch "misc: add i.MX8 misc driver" Addressed comments from Anatolig for patch "misc: imx8: add scfw api impementation" Merged the files into one Moved one error handle to patch 4 Moved patch "arm: global_data: add scu_dev for i.MX8" to patch 7 For Fabio's comments to imx-mkimage, I'll start the porting work, but needs more time, it will be not be in this patchset. V3: patch 7: use CONFIG_IMX8 patch 29: use CONFIG_IMX8 patch 32: Added README with scfw_tcm.bin link added misc: remove sc_rpc_msg_t typedef, use struct sc_rpc_msg_s in patchset. V2: In this V2 patchset, the SCFW API is replaced by uclass driver implementation, but the api name is not changed from scfw api. The related macro definitions are kept in different api.h file following SCFW API file structure. Impelemnted scu misc driver to handle the low level communication between Acore and SCU. Implemented rm/pm/pad/misc protocol code to invoke misc_call for different functionality. The dm clk/pinctrl/power and others will invokde the protocol api to communicate with SCU. The arch/arm/mach-imx/imx8/clock.c currently is only a dummy file to avoid build break for mxc_get_clock. The i2c patch and common power domain patches are removed from this patchset. The imx8 name still kept, this is because NXP marketing requires to use this name for i.MX branding. Anatolij Gustschin (2): imx8: cpu: add function for reading FEC MAC from fuse imx8: cpu: add uclass based CPU driver Peng Fan (30): dt-bindings: pinctrl: add i.MX8QXP pads definition dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QXP clocks definition dt-bindings: soc: add i.MX8QXP pm and rsrc definition imx8: add scfw macro definition imx: add Kconfig entry for i.MX8QXP arm: build mach-imx for i.MX8 arm: global_data: add scu_dev for i.MX8 misc: add i.MX8 misc driver misc: imx8: add scfw api impementation imx: boot_mode: Add FLEXSPI boot entry imx8: add imx-regs header file imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined imx: add i.MX8 cpu type armv8: add cpu core helper functions imx8: add basic cpu support imx8: add boot device detection imx8: implement mmc_get_env_dev imx8: add mmu and dram related functions imx8: add arch_cpu_init arch_cpu_init_dm imx8: add iomux configuration api imx8: add dummy clock gpio: mxc_gpio: add support for i.MX8 pinctrl: Add pinctrl driver for i.MX8 power: Add power domain driver for i.MX8 clk: imx: add clk driver for i.MX8QXP serial_lpuart: Update lpuart driver to support i.MX8 serial: lpuart: support uclass clk api mmc: fsl_esdhc: add uclass clk support arm: dts: introduce dtsi for i.MX8QXP imx: add i.MX8QXP MEK board support Ye Li (2): serial: lpuart: Enable RX and TX FIFO fsl_esdhc: Update usdhc driver to support i.MX8 arch/arm/Kconfig | 8 + arch/arm/Makefile | 2 +- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8-ca35.dtsi | 66 ++ arch/arm/dts/fsl-imx8dx.dtsi | 499 ++++++++++++ arch/arm/dts/fsl-imx8dxp.dtsi | 11 + arch/arm/dts/fsl-imx8qxp-mek.dts | 246 ++++++ arch/arm/dts/fsl-imx8qxp.dtsi | 51 ++ arch/arm/include/asm/arch-imx/cpu.h | 6 + arch/arm/include/asm/arch-imx8/clock.h | 27 + arch/arm/include/asm/arch-imx8/gpio.h | 21 + arch/arm/include/asm/arch-imx8/imx-regs.h | 46 ++ arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 + arch/arm/include/asm/arch-imx8/iomux.h | 40 + arch/arm/include/asm/arch-imx8/power-domain.h | 15 + arch/arm/include/asm/arch-imx8/sci/rpc.h | 158 ++++ arch/arm/include/asm/arch-imx8/sci/sci.h | 88 ++ .../include/asm/arch-imx8/sci/svc/misc/api.h | 30 + .../include/asm/arch-imx8/sci/svc/pad/api.h | 57 ++ .../include/asm/arch-imx8/sci/svc/pm/api.h | 44 + .../include/asm/arch-imx8/sci/svc/rm/api.h | 69 ++ arch/arm/include/asm/arch-imx8/sci/types.h | 220 +++++ arch/arm/include/asm/arch-imx8/sys_proto.h | 19 + arch/arm/include/asm/armv8/cpu.h | 26 + arch/arm/include/asm/global_data.h | 4 + arch/arm/include/asm/mach-imx/boot_mode.h | 1 + arch/arm/include/asm/mach-imx/sys_proto.h | 3 + arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8/Kconfig | 26 + arch/arm/mach-imx/imx8/Makefile | 7 + arch/arm/mach-imx/imx8/clock.c | 21 + arch/arm/mach-imx/imx8/cpu.c | 646 +++++++++++++++ arch/arm/mach-imx/imx8/iomux.c | 43 + board/freescale/imx8qxp_mek/Kconfig | 14 + board/freescale/imx8qxp_mek/MAINTAINERS | 6 + board/freescale/imx8qxp_mek/Makefile | 7 + board/freescale/imx8qxp_mek/README | 72 ++ board/freescale/imx8qxp_mek/imx8qxp_mek.c | 170 ++++ board/freescale/mx8mq_evk/README | 81 ++ configs/imx8qxp_mek_defconfig | 51 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/imx/Kconfig | 6 + drivers/clk/imx/Makefile | 5 + drivers/clk/imx/clk-imx8.c | 393 +++++++++ drivers/gpio/mxc_gpio.c | 30 +- drivers/misc/Makefile | 1 + drivers/misc/imx8/Makefile | 3 + drivers/misc/imx8/scu.c | 266 ++++++ drivers/misc/imx8/scu_api.c | 367 +++++++++ drivers/mmc/fsl_esdhc.c | 34 +- drivers/pinctrl/nxp/Kconfig | 18 + drivers/pinctrl/nxp/Makefile | 2 + drivers/pinctrl/nxp/pinctrl-imx.c | 209 ++--- drivers/pinctrl/nxp/pinctrl-imx.h | 16 + drivers/pinctrl/nxp/pinctrl-imx8.c | 40 + drivers/pinctrl/nxp/pinctrl-scu.c | 66 ++ drivers/power/domain/Kconfig | 8 +- drivers/power/domain/Makefile | 1 + drivers/power/domain/imx8-power-domain.c | 315 ++++++++ drivers/serial/serial_lpuart.c | 128 ++- include/configs/imx8qxp_mek.h | 157 ++++ include/dt-bindings/clock/imx8qxp-clock.h | 583 ++++++++++++++ include/dt-bindings/pinctrl/pads-imx8qxp.h | 757 ++++++++++++++++++ include/dt-bindings/soc/imx8_pd.h | 188 +++++ include/dt-bindings/soc/imx_rsrc.h | 557 +++++++++++++ include/fsl_lpuart.h | 2 +- 67 files changed, 6931 insertions(+), 142 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8-ca35.dtsi create mode 100644 arch/arm/dts/fsl-imx8dx.dtsi create mode 100644 arch/arm/dts/fsl-imx8dxp.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi create mode 100644 arch/arm/include/asm/arch-imx8/clock.h create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/rpc.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/types.h create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h create mode 100644 arch/arm/include/asm/armv8/cpu.h create mode 100644 arch/arm/mach-imx/imx8/Kconfig create mode 100644 arch/arm/mach-imx/imx8/Makefile create mode 100644 arch/arm/mach-imx/imx8/clock.c create mode 100644 arch/arm/mach-imx/imx8/cpu.c create mode 100644 arch/arm/mach-imx/imx8/iomux.c create mode 100644 board/freescale/imx8qxp_mek/Kconfig create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS create mode 100644 board/freescale/imx8qxp_mek/Makefile create mode 100644 board/freescale/imx8qxp_mek/README create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c create mode 100644 board/freescale/mx8mq_evk/README create mode 100644 configs/imx8qxp_mek_defconfig create mode 100644 drivers/clk/imx/Kconfig create mode 100644 drivers/clk/imx/Makefile create mode 100644 drivers/clk/imx/clk-imx8.c create mode 100644 drivers/misc/imx8/Makefile create mode 100644 drivers/misc/imx8/scu.c create mode 100644 drivers/misc/imx8/scu_api.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c create mode 100644 drivers/power/domain/imx8-power-domain.c create mode 100644 include/configs/imx8qxp_mek.h create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h create mode 100644 include/dt-bindings/soc/imx8_pd.h create mode 100644 include/dt-bindings/soc/imx_rsrc.h -- 2.17.1

5 44

[U-Boot] [PATCH v2 1/2] cpu: Add DM_FLAG_PRE_RELOC flag to various cpu drivers
by Bin Meng 06 Nov '18

06 Nov '18

It turns out commit c0434407b595 broke some boards which have DM CPU driver with CONFIG_DISPLAY_CPUINFO option on. These boards just fail to boot when print_cpuinfo() is called during boot. Fixes: c0434407b595 ("board_f: Use static print_cpuinfo if CONFIG_CPU is active") Reported-by: Stefan Roese <sr(a)denx.de> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - drop the sandbox cpu driver change arch/x86/cpu/baytrail/cpu.c | 1 + arch/x86/cpu/broadwell/cpu.c | 1 + arch/x86/cpu/cpu_x86.c | 1 + arch/x86/cpu/ivybridge/model_206ax.c | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 56e9813..2eb9172 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -203,4 +203,5 @@ U_BOOT_DRIVER(cpu_x86_baytrail_drv) = { .bind = cpu_x86_bind, .probe = cpu_x86_baytrail_probe, .ops = &cpu_x86_baytrail_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 02b3169..232fa40 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -764,4 +764,5 @@ U_BOOT_DRIVER(cpu_x86_broadwell_drv) = { .probe = cpu_x86_broadwell_probe, .ops = &cpu_x86_broadwell_ops, .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv), + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 2b6cc9f..1aaf851 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -94,4 +94,5 @@ U_BOOT_DRIVER(cpu_x86_drv) = { .of_match = cpu_x86_ids, .bind = cpu_x86_bind, .ops = &cpu_x86_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 33e5c62..6edc3e2 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -478,4 +478,5 @@ U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = { .bind = cpu_x86_bind, .probe = cpu_x86_model_206ax_probe, .ops = &cpu_x86_model_206ax_ops, + .flags = DM_FLAG_PRE_RELOC, }; -- 2.7.4

3 5

[U-Boot] [PATCH] spi: Zap mpc8xx_spi driver
by Jagan Teki 06 Nov '18

06 Nov '18

- Driver not used by any boards - No update on 'dm conversion' Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/spi/Kconfig | 6 - drivers/spi/Makefile | 1 - drivers/spi/mpc8xx_spi.c | 336 ----------------------------------------------- 3 files changed, 343 deletions(-) delete mode 100644 drivers/spi/mpc8xx_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 235a8c7d73..fd3f115ccf 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -274,12 +274,6 @@ config LPC32XX_SSP help Enable support for SPI on LPC32xx -config MPC8XX_SPI - bool "MPC8XX SPI Driver" - depends on 8xx - help - Enable support for SPI on MPC8XX - config MPC8XXX_SPI bool "MPC8XXX SPI Driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4b6000fd9a..f104836630 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o -obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c deleted file mode 100644 index b5bd558526..0000000000 --- a/drivers/spi/mpc8xx_spi.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * <nboppuri(a)trinetcommunication.com>, - * <pmpatel(a)trinetcommunication.com> - * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen(a)icn.siemens.de> - * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de>. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8xx CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd(a)denx.de - * - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <linux/ctype.h> -#include <malloc.h> -#include <post.h> -#include <serial.h> - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0xb00 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CONFIG_SYS_SPI_INIT_OFFSET -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 -#endif - -#define CPM_SPI_BASE_RX CPM_SPI_BASE -#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t)) - -/* ------------------- - * Function prototypes - * ------------------- */ -ssize_t spi_xfer(size_t); - -/* ------------------- - * Variables - * ------------------- */ - -#define MAX_BUFFER 0x104 - -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f(void) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - -/* 1 */ - /* ------------------------------------------------ - * Initialize Port B SPI pins -> page 34-8 MPC860UM - * (we are only in Master Mode !) - * ------------------------------------------------ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO) - * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI) - * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK) - * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM) - * -------------------------------------------- */ - clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */ - - /* ---------------------------------------------- - * In/Out or per. Function 0/1 - * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO - * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI - * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK - * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM - * ---------------------------------------------- */ - setbits_be32(&cp->cp_pbdir, 0x0000000F); - - /* ---------------------------------------------- - * open drain or active output - * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO - * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI - * PBODR[30] = 0 [0x00000002] -> active output: SPICLK - * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM - * ---------------------------------------------- */ - - clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008); - - /* Initialize the parameter ram. - * We need to make sure many things are initialized to zero - */ - out_be32(&spi->spi_rstate, 0); - out_be32(&spi->spi_rdp, 0); - out_be16(&spi->spi_rbptr, 0); - out_be16(&spi->spi_rbc, 0); - out_be32(&spi->spi_rxtmp, 0); - out_be32(&spi->spi_tstate, 0); - out_be32(&spi->spi_tdp, 0); - out_be16(&spi->spi_tbptr, 0); - out_be16(&spi->spi_tbc, 0); - out_be32(&spi->spi_txtmp, 0); - -/* 3 */ - /* Set up the SPI parameters in the parameter ram */ - out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX); - out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX); - - /***********IMPORTANT******************/ - - /* - * Setting transmit and receive buffer descriptor pointers - * initially to rbase and tbase. Only the microcode patches - * documentation talks about initializing this pointer. This - * is missing from the sample I2C driver. If you dont - * initialize these pointers, the kernel hangs. - */ - out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX); - out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX); - -/* 4 */ - /* Init SPI Tx + Rx Parameters */ - while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) - ; - - out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | - CPM_CR_FLG); - while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) - ; - -/* 5 */ - /* Set SDMA configuration register */ - out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); - -/* 6 */ - /* Set to big endian. */ - out_8(&spi->spi_tfcr, SMC_EB); - out_8(&spi->spi_rfcr, SMC_EB); - -/* 7 */ - /* Set maximum receive size. */ - out_be16(&spi->spi_mrblr, MAX_BUFFER); - -/* 8 + 9 */ - /* tx and rx buffer descriptors */ - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - clrbits_be16(&tbdf->cbd_sc, BD_SC_READY); - clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY); - - /* Set the bd's rx and tx buffer address pointers */ - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - -/* 10 + 11 */ - out_8(&cp->cp_spim, 0); /* Mask all SPI events */ - out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ - - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r(void) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *)malloc(MAX_BUFFER); - txbuf = (uchar *)malloc(MAX_BUFFER); - - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) - break; - udelay(1000); - } - if (i >= 1000) - printf("*** spi_write: Time out while writing!\n"); - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer(size_t count) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - int tm; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - /* Set CS for device */ - clrbits_be32(&cp->cp_pbdat, 0x0001); - - /* Setting tx bd status and data length */ - out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP); - out_be16(&tbdf->cbd_datlen, count); - - /* Setting rx bd status and data length */ - out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); - out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */ - - clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR | - SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8)); - out_8(&cp->cp_spim, 0); /* Mask all SPI events */ - out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ - - /* start spi transfer */ - setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm = 0; tm < 1000; ++tm) { - if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */ - break; - if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0) - break; - udelay(1000); - } - if (tm >= 1000) - printf("*** spi_xfer: Time out while xferring to/from SPI!\n"); - - /* Clear CS for device */ - setbits_be32(&cp->cp_pbdat, 0x0001); - - return count; -} -- 2.14.3

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[U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2
by Michal Simek 06 Nov '18

06 Nov '18

Hi Tom, please consider to pull these patches to your tree. Buildmain for xilinx boards looks good and travis is not done yet but link is here (I have seen several timeouts recently but it was there even on clear mainline). https://travis-ci.org/michalsimek/u-boot/builds/441591781 If you don't like this please at least cherry-pick this one Revert "fdt: fdtdec_setup_memory_banksize() use livetree" (sha1: 01ac0843aeedc3c95fe68e7ce6a8f35bf1a04b23) which I need for getting SPL up and running again on zynq/zynqmp boards. Thanks, Michal The following changes since commit 15f22ac2eea5ee9f17b14a143c94e7480bbafbff: ldpaa_eth.c: Fix warning when PHYLIB is not enabled (2018-10-12 07:41:24 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.11-rc2 for you to fetch changes up to 045c62be10d64a558f56febcaa2d01b1abbcfa00: cmd: kgdb: Enable kgdb only for PPC (2018-10-15 12:36:37 +0200) ---------------------------------------------------------------- Xilinx changes for v2018.11-rc2 FPGA: - Fix SPL fpga loading from FIT ARM64: - Fix gic accesses in EL2/EL1 Xilinx: - Add dlc20 board support - Add Versal board support - Sync defconfigs - Enable MP via Kconfig - Add missing efuse node - Enable CDC for zcu100 cmd: - Fix kgdb Kconfig dependency serial-pl01x: - Add support for handling clk from DT ---------------------------------------------------------------- Michal Simek (13): spl: fpga: Implement fpga bistream loading with fpga_load arm: zynq: Enable FIT fpga loading in SPL for zc706 arm: zynq: Add support for DLC20 board Revert "fdt: fdtdec_setup_memory_banksize() use livetree" arm: zynq: Add efuse node for Zynq-7000S devices xilinx: Sync defconfigs with current Kconfig arm64: zynqmp: Enable CDC ethernet gadget for zcu100/Ultra96 arm64: gic: Do gicv3 secure initialization based on EL level arm64: versal: Add support for new Xilinx Versal ACAPs net: gem: Do not setup any clock for Xilinx SoC Versal arm64: versal: Add Xilinx Versal Virtual QEMU board arm64: zynqmp: Enable MP by default via Kconfig cmd: kgdb: Enable kgdb only for PPC Siva Durga Prasad Paladugu (3): serial: pl01x: Get clock from clock node if no clock property found arm64: zynqmp: Move TCM initialization to a separate routine arm64: zynqmp: Add new command for TCM initialization Kconfig | 2 +- MAINTAINERS | 6 ++++ arch/arm/Kconfig | 11 +++++++ arch/arm/Makefile | 1 + arch/arm/cpu/armv8/zynqmp/cpu.c | 12 +++++-- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-7000.dtsi | 5 +++ arch/arm/dts/zynq-dlc20-rev1.0.dts | 103 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-zynqmp/sys_proto.h | 3 ++ arch/arm/lib/gic_64.S | 16 +++++---- arch/arm/mach-versal/Kconfig | 44 +++++++++++++++++++++++++ arch/arm/mach-versal/Makefile | 8 +++++ arch/arm/mach-versal/clk.c | 30 +++++++++++++++++ arch/arm/mach-versal/cpu.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-versal/include/mach/gpio.h | 6 ++++ arch/arm/mach-versal/include/mach/hardware.h | 34 +++++++++++++++++++ arch/arm/mach-versal/include/mach/sys_proto.h | 6 ++++ board/xilinx/versal/MAINTAINERS | 7 ++++ board/xilinx/versal/Makefile | 7 ++++ board/xilinx/versal/board.c | 81 +++++++++++++++++++++++++++++++++++++++++++++ board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c | 280 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/xilinx/zynqmp/cmds.c | 37 ++++++++++++++++++++- cmd/Kconfig | 1 + common/spl/spl_fit.c | 34 +++++++++---------- configs/avnet_ultra96_rev1_defconfig | 8 +++-- configs/microblaze-generic_defconfig | 2 +- configs/xilinx_versal_virt_defconfig | 68 ++++++++++++++++++++++++++++++++++++++ configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_defconfig | 1 + configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 8 +++-- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - configs/zynq_dlc20_rev1_0_defconfig | 74 +++++++++++++++++++++++++++++++++++++++++ configs/zynq_zc706_defconfig | 4 +++ drivers/mmc/Kconfig | 2 +- drivers/net/Kconfig | 2 +- drivers/net/zynq_gem.c | 4 +++ drivers/serial/serial_pl01x.c | 26 +++++++++++++++ drivers/spi/Kconfig | 4 +-- env/Kconfig | 4 +-- include/configs/xilinx_versal.h | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/fdtdec.c | 44 +++++++++++++------------ 58 files changed, 1101 insertions(+), 78 deletions(-) create mode 100644 arch/arm/dts/zynq-dlc20-rev1.0.dts create mode 100644 arch/arm/mach-versal/Kconfig create mode 100644 arch/arm/mach-versal/Makefile create mode 100644 arch/arm/mach-versal/clk.c create mode 100644 arch/arm/mach-versal/cpu.c create mode 100644 arch/arm/mach-versal/include/mach/gpio.h create mode 100644 arch/arm/mach-versal/include/mach/hardware.h create mode 100644 arch/arm/mach-versal/include/mach/sys_proto.h create mode 100644 board/xilinx/versal/MAINTAINERS create mode 100644 board/xilinx/versal/Makefile create mode 100644 board/xilinx/versal/board.c create mode 100644 board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c create mode 100644 configs/xilinx_versal_virt_defconfig create mode 100644 configs/zynq_dlc20_rev1_0_defconfig create mode 100644 include/configs/xilinx_versal.h

2 5

[U-Boot] [PATCH v2 0/7] driver: net: ti: clean up and code optimization
by Grygorii Strashko 06 Nov '18

06 Nov '18

This series contains set of code clean up and optimizations for TI networking drivers. Patch 1 - Adds drivers/net/ti/ folder and moves all TI's networking code in this folder. Patches 2,3 - keystone2 clean up Patch 5 - introduces common TI MDIO support library as existing TI SoCs network HW IPs have similar MDIO implementation. Patches 6-7 - conversation of TI CPSW and keystone_net drivers to use common TI MDIO support library tested dhcp and kernel boot on: - k2e/g/hk/l evms - am437x-gpevm and AM5748 IDK changes in v2: - patch 5 comments fixed: use wait_for_bit, snprintf, mdelay, mdio_free TODO: TODO: As per code and documentation davinci_emac.c seems also can be re-worked to use common TI MDIO support library and network PHYs framework. Unfortunately, I have no HW to work with. Grygorii Strashko (7): driver: net: consolidate ti's code in separate folder configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig drivers: net: keystone_net: drop non dm code driver: net: ti: cpsw: update to use SPDX identifier driver: net: ti: introduce common mdio support library driver: net: ti: cpsw: switch to use common mdio lib driver: net: ti: keystone_net: switch to use common mdio lib arch/arm/include/asm/ti-common/keystone_net.h | 27 -- arch/arm/mach-davinci/dp83848.c | 2 +- arch/arm/mach-davinci/et1011c.c | 2 +- arch/arm/mach-davinci/ksz8873.c | 2 +- arch/arm/mach-davinci/lxt972.c | 2 +- board/ti/ks2_evm/board.c | 53 ---- board/ti/ks2_evm/board.h | 3 - board/ti/ks2_evm/board_k2e.c | 74 ----- board/ti/ks2_evm/board_k2g.c | 18 -- board/ti/ks2_evm/board_k2hk.c | 42 --- board/ti/ks2_evm/board_k2l.c | 42 --- configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + drivers/net/Kconfig | 13 +- drivers/net/Makefile | 4 +- drivers/net/ti/Kconfig | 20 ++ drivers/net/ti/Makefile | 7 + drivers/net/{ => ti}/cpsw-common.c | 0 drivers/net/{ => ti}/cpsw.c | 146 +--------- drivers/net/ti/cpsw_mdio.c | 201 +++++++++++++ drivers/net/ti/cpsw_mdio.h | 18 ++ drivers/net/{ => ti}/davinci_emac.c | 0 drivers/net/{ => ti}/davinci_emac.h | 0 drivers/net/{ => ti}/keystone_net.c | 401 +------------------------- include/configs/ti_armv7_keystone2.h | 1 - 31 files changed, 284 insertions(+), 802 deletions(-) create mode 100644 drivers/net/ti/Kconfig create mode 100644 drivers/net/ti/Makefile rename drivers/net/{ => ti}/cpsw-common.c (100%) rename drivers/net/{ => ti}/cpsw.c (90%) create mode 100644 drivers/net/ti/cpsw_mdio.c create mode 100644 drivers/net/ti/cpsw_mdio.h rename drivers/net/{ => ti}/davinci_emac.c (100%) rename drivers/net/{ => ti}/davinci_emac.h (100%) rename drivers/net/{ => ti}/keystone_net.c (68%) -- 2.10.5

5 12

[U-Boot] [PATCH v1] x86: acpi: Remove redundant Offset (0x00)
by Andy Shevchenko 06 Nov '18

06 Nov '18

New ACPI assembler issues a warning: board/intel/edison/dsdt.asl.tmp 13: Offset (0x00), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Indeed, in the OperationRegion the offset is 0x00 by default. Thus, drop unneeded Offset() use as suggested by ACPI assembler. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl | 1 - arch/x86/include/asm/arch-quark/acpi/global_nvs.asl | 1 - arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl index 9b8d1895ee..aaf87f4735 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl @@ -8,7 +8,6 @@ OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) Field(GNVS, ByteAcc, NoLock, Preserve) { - Offset (0x00), PCNT, 8, /* processor count */ IURE, 8, /* internal UART enabled */ } diff --git a/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl index 44b9f12c7c..61602173f8 100644 --- a/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl +++ b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl @@ -8,6 +8,5 @@ OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) Field(GNVS, ByteAcc, NoLock, Preserve) { - Offset (0x00), PCNT, 8, /* processor count */ } diff --git a/arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl b/arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl index a6296c2cb6..895b807e96 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl @@ -10,6 +10,5 @@ OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) Field(GNVS, ByteAcc, NoLock, Preserve) { - Offset (0x00), PCNT, 8, /* processor count */ } -- 2.19.1

3 3

[U-Boot] [PATCH v3 0/7] driver: net: ti: clean up and code optimization
by Grygorii Strashko 05 Nov '18

05 Nov '18

This series contains set of code clean up and optimizations for TI networking drivers. Patch 1 - Adds drivers/net/ti/ folder and moves all TI's networking code in this folder. Patches 2,3 - keystone2 clean up Patch 5 - introduces common TI MDIO support library as existing TI SoCs network HW IPs have similar MDIO implementation. Patches 6-7 - conversation of TI CPSW and keystone_net drivers to use common TI MDIO support library tested dhcp and kernel boot on: - k2e/g/hk/l evms - am437x-gpevm and AM5748 IDK changes in v3: - patch 5 comments applied changes in v2: - patch 5 comments fixed: use wait_for_bit, snprintf, mdelay, mdio_free v2: https://patchwork.ozlabs.org/cover/991649/ v1: https://patchwork.ozlabs.org/cover/989449/ TODO: TODO: As per code and documentation davinci_emac.c seems also can be re-worked to use common TI MDIO support library and network PHYs framework. Unfortunately, I have no HW to work with. Grygorii Strashko (7): driver: net: consolidate ti's code in separate folder configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig drivers: net: keystone_net: drop non dm code driver: net: ti: cpsw: update to use SPDX identifier driver: net: ti: introduce common mdio support library driver: net: ti: cpsw: switch to use common mdio lib driver: net: ti: keystone_net: switch to use common mdio lib arch/arm/include/asm/ti-common/keystone_net.h | 27 -- arch/arm/mach-davinci/dp83848.c | 2 +- arch/arm/mach-davinci/et1011c.c | 2 +- arch/arm/mach-davinci/ksz8873.c | 2 +- arch/arm/mach-davinci/lxt972.c | 2 +- board/ti/ks2_evm/board.c | 53 ---- board/ti/ks2_evm/board.h | 3 - board/ti/ks2_evm/board_k2e.c | 74 ----- board/ti/ks2_evm/board_k2g.c | 18 -- board/ti/ks2_evm/board_k2hk.c | 42 --- board/ti/ks2_evm/board_k2l.c | 42 --- configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + drivers/net/Kconfig | 13 +- drivers/net/Makefile | 4 +- drivers/net/ti/Kconfig | 20 ++ drivers/net/ti/Makefile | 7 + drivers/net/{ => ti}/cpsw-common.c | 0 drivers/net/{ => ti}/cpsw.c | 146 +--------- drivers/net/ti/cpsw_mdio.c | 203 +++++++++++++ drivers/net/ti/cpsw_mdio.h | 18 ++ drivers/net/{ => ti}/davinci_emac.c | 0 drivers/net/{ => ti}/davinci_emac.h | 0 drivers/net/{ => ti}/keystone_net.c | 401 +------------------------- include/configs/ti_armv7_keystone2.h | 1 - 31 files changed, 286 insertions(+), 802 deletions(-) create mode 100644 drivers/net/ti/Kconfig create mode 100644 drivers/net/ti/Makefile rename drivers/net/{ => ti}/cpsw-common.c (100%) rename drivers/net/{ => ti}/cpsw.c (90%) create mode 100644 drivers/net/ti/cpsw_mdio.c create mode 100644 drivers/net/ti/cpsw_mdio.h rename drivers/net/{ => ti}/davinci_emac.c (100%) rename drivers/net/{ => ti}/davinci_emac.h (100%) rename drivers/net/{ => ti}/keystone_net.c (68%) -- 2.10.5

2 16

[U-Boot] [PATCH v2 0/3] add support for VSC8584 and VSC8574 Microsemi PHYs
by Quentin Schulz 05 Nov '18

05 Nov '18

The VSC8584 and VSC8574 PHYs are 4-port PHYs that are 10/100/1000BASE-T, 100BASE-FX, 1000BASE-X and triple-speed copper SFP capable, can communicate with the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and can set the blinking pattern of each of its 4 LEDs, supports SyncE as well as HP Auto-MDIX detection. This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the MAC. They have also an internal Intel 8051 microcontroller whose firmware needs to be patched when the PHY is reset. If the 8051's firmware has the expected CRC, its patching can be skipped. The microcontroller can be accessed from any port of the PHY, though the CRC function can only be done through the PHY that is the base PHY of the package (internal address 0) due to a limitation of the firmware. The GPIO register bank is a set of registers that are common to all PHYs in the package. So any modification in any register of this bank affects all PHYs of the package. Thanks, Quentin v2: - used BIT and GENMASK instead of hex values, - defined a few magic values, - fixed comments formatting, - added comments on register writes for analog and electrical tweaks, - fixed a redondant use of (0x8000 | 0x8000 | addr) in vsc8584_csr_write for vsc8574, Quentin Schulz (3): net: phy: mscc: add support for VSC8584 PHY net: phy: mscc: factorize part of config function for VSC8584 net: phy: mscc: add support for VSC8574 PHY drivers/net/phy/mscc.c | 994 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 994 insertions(+) -- 2.17.1

2 8

[U-Boot] [PATCH v5 00/13] Support for the Faraday ftgmac100 controller
by Cédric Le Goater 05 Nov '18

05 Nov '18

Hello, This series re-enables the Faraday ftgmac100 controller driver and its Aspeed variant as as one can find on the OpenPOWER platforms. The driver is largely reworked to support the driver model and also adds the MDIO bus and phylib support. It was tested on the AST2500 evb. Git tree available here: https://github.com/legoater/u-boot/commits/aspeed Thanks, C. Changes since v4 : - introduced a wait_for_bit macro to handle timeouts when transmitting Changes since v3 : It didn't seem necessary to remove the 'dev' argument from the ftgmac100_phy_init() and ftgmac100_phy_reset() function prototypes as the code is completely reworked in patch 5. - improved ftgmac100_mdio_init() and ftgmac100_phy_init() prototypes - introduced a ftgmac100_wait_for_txdone() function similar to the wait_for_bit_*() macros. Changes since v2 : - split changes in multiple patches to preserve git history, but the code has not changed since the reviewed v2 patchset. - included a couple more changes to sync the DTS file with Linux. Changes since v1 : - improved comments in the code - changed the type of 'iobase' to 'struct ftgmac100 *' to remove the casts in other routines. - replaced the loop in the mdio methods by a call to readl_poll_timeout() and fixed the returned value. - added a flush cache on the arrays of TX and RX descriptors in ftgmac100_start() - fixed returned value of - added a timer loop to catch transmit timeouts - introduced a clk_bulk - improved Kconfig description - introduced a udevice_id .data model - dropped is_aspeed bool - dropped MDIO interface setting for Aspeed SoC. The default is correct. - removed the clcoks which are now handled automatically in the ftgmac100 driver - introduced a fix for the D2-PLL clock setting Cédric Le Goater (13): net: ftgmac100: use the BIT() macro net: ftgmac100: use the aligned() macro net: ftgmac100: convert to driver model net: ftgmac100: use setbits_le32() in the reset method net: ftgmac100: add MDIO bus and phylib support net: ftgmac100: convert the RX/TX descriptor arrays net: ftgmac100: handle timeouts when transmitting net: ftgmac100: add clock support aspeed: ast2500: fix missing break in D2PLL clock enablement net: ftgmac100: Add support for the Aspeed SoC aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level aspeed: Activate ethernet devices on the ast2500 Eval Board aspeed: ast2500: fix D2-PLL clock setting in RGMII mode drivers/net/ftgmac100.h | 158 +-- include/netdev.h | 1 - drivers/clk/aspeed/clk_ast2500.c | 39 + drivers/net/ftgmac100.c | 732 +++++------ arch/arm/dts/ast2500-evb.dts | 23 + arch/arm/dts/ast2500.dtsi | 1949 ++++++++++++++++++------------ configs/evb-ast2500_defconfig | 8 + drivers/net/Kconfig | 26 + 8 files changed, 1707 insertions(+), 1229 deletions(-) -- 2.17.2

2 27

[U-Boot] [PATCH v6] net: Add MT7628 ethernet driver
by Stefan Roese 05 Nov '18

05 Nov '18

This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs (e.g. MT7628 and MT7688), including a minimum setup of the integrated switch. This driver is loosly based on the driver version included in this MediaTek github repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git Tested on the MT7688 LinkIt smart-gateway and on the Gardena-smart-gateway. Signed-off-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Frank Wunderlich <frankwu(a)gmx.de> Cc: Weijie Gao <hackpascal(a)gmail.com> --- v6: - Simplified MAC address assignment - Added free_pkt functions as suggested by Joe v5: - Rename driver and Kconfig and functions names again to avoid mix-up with the MT76xx ARM SoCs v4: - Rename driver and Kconfig to avoid mix-up with the MT76xx ARM SoCs v3: - Add Reviewed-by from Daniel - Address review comments from Joe: - Use more macros / defines instead of magic values, especially in the MDIO functions - Use FIELD_xxx from include/linux/bitfield.h whereever possible - Remove some unreferenced defines - Remove some unnecessary casts - Spelling fixes - Add documentation in doc/device-tree-bindings/net/ v2: - Use wait_for_bit_le32() in more places - Use syscon / regmap to access the system-controller registers needed in this driver instead of finding and mapping this area .../net/mediatek,mt7628-eth.txt | 17 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/mt7628-eth.c | 644 ++++++++++++++++++ 4 files changed, 669 insertions(+) create mode 100644 doc/device-tree-bindings/net/mediatek,mt7628-eth.txt create mode 100644 drivers/net/mt7628-eth.c diff --git a/doc/device-tree-bindings/net/mediatek,mt7628-eth.txt b/doc/device-tree-bindings/net/mediatek,mt7628-eth.txt new file mode 100644 index 0000000000..ec97504a3f --- /dev/null +++ b/doc/device-tree-bindings/net/mediatek,mt7628-eth.txt @@ -0,0 +1,17 @@ +* MediaTek Frame Engine Ethernet controller + +Required properties: +- compatible: should be "mediatek,mt7628-eth" +- reg: address and length of the register set for the frame + engine ethernet controller and the internal switch. +- syscon: phandle to the system controller + +Example: + +eth@10100000 { + compatible = "mediatek,mt7628-eth"; + reg = <0x10100000 0x10000 + 0x10110000 0x8000>; + + syscon = <&sysc>; +}; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f1f0e2d94e..fba9d7c31c 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -227,6 +227,13 @@ config MACB_ZYNQ The Cadence MACB ethernet interface was used on Zynq platform. Say Y to enable support for the MACB/GEM in Zynq chip. +config MT7628_ETH + bool "MediaTek MT7628 Ethernet Interface" + depends on ARCH_MT7620 + help + The MediaTek MT7628 ethernet interface is used on MT7628 and + MT7688 based boards. + config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" depends on DM_ETH && DM_PCI diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 48a2878071..cc0971c614 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o +obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVNETA) += mvneta.o obj-$(CONFIG_MVPP2) += mvpp2.o diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c new file mode 100644 index 0000000000..7833b2f47a --- /dev/null +++ b/drivers/net/mt7628-eth.c @@ -0,0 +1,644 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MediaTek ethernet IP driver for U-Boot + * + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + */ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <miiphy.h> +#include <net.h> +#include <regmap.h> +#include <syscon.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <linux/err.h> + +/* System controller register */ +#define MT7628_RSTCTRL_REG 0x34 +#define RSTCTRL_EPHY_RST BIT(24) + +#define MT7628_AGPIO_CFG_REG 0x3c +#define MT7628_EPHY_GPIO_AIO_EN GENMASK(20, 17) +#define MT7628_EPHY_P0_DIS BIT(16) + +#define MT7628_GPIO2_MODE_REG 0x64 + +/* Ethernet frame engine register */ +#define PDMA_RELATED 0x0800 + +#define TX_BASE_PTR0 (PDMA_RELATED + 0x000) +#define TX_MAX_CNT0 (PDMA_RELATED + 0x004) +#define TX_CTX_IDX0 (PDMA_RELATED + 0x008) +#define TX_DTX_IDX0 (PDMA_RELATED + 0x00c) + +#define RX_BASE_PTR0 (PDMA_RELATED + 0x100) +#define RX_MAX_CNT0 (PDMA_RELATED + 0x104) +#define RX_CALC_IDX0 (PDMA_RELATED + 0x108) + +#define PDMA_GLO_CFG (PDMA_RELATED + 0x204) +#define PDMA_RST_IDX (PDMA_RELATED + 0x208) +#define DLY_INT_CFG (PDMA_RELATED + 0x20c) + +#define SDM_RELATED 0x0c00 + +#define SDM_MAC_ADRL (SDM_RELATED + 0x0c) /* MAC address LSB */ +#define SDM_MAC_ADRH (SDM_RELATED + 0x10) /* MAC Address MSB */ + +#define RST_DTX_IDX0 BIT(0) +#define RST_DRX_IDX0 BIT(16) + +#define TX_DMA_EN BIT(0) +#define TX_DMA_BUSY BIT(1) +#define RX_DMA_EN BIT(2) +#define RX_DMA_BUSY BIT(3) +#define TX_WB_DDONE BIT(6) + +/* Ethernet switch register */ +#define MT7628_SWITCH_FCT0 0x0008 +#define MT7628_SWITCH_PFC1 0x0014 +#define MT7628_SWITCH_FPA 0x0084 +#define MT7628_SWITCH_SOCPC 0x008c +#define MT7628_SWITCH_POC0 0x0090 +#define MT7628_SWITCH_POC2 0x0098 +#define MT7628_SWITCH_SGC 0x009c +#define MT7628_SWITCH_PCR0 0x00c0 +#define PCR0_PHY_ADDR GENMASK(4, 0) +#define PCR0_PHY_REG GENMASK(12, 8) +#define PCR0_WT_PHY_CMD BIT(13) +#define PCR0_RD_PHY_CMD BIT(14) +#define PCR0_WT_DATA GENMASK(31, 16) + +#define MT7628_SWITCH_PCR1 0x00c4 +#define PCR1_WT_DONE BIT(0) +#define PCR1_RD_RDY BIT(1) +#define PCR1_RD_DATA GENMASK(31, 16) + +#define MT7628_SWITCH_FPA1 0x00c8 +#define MT7628_SWITCH_FCT2 0x00cc +#define MT7628_SWITCH_SGC2 0x00e4 +#define MT7628_SWITCH_BMU_CTRL 0x0110 + +/* rxd2 */ +#define RX_DMA_DONE BIT(31) +#define RX_DMA_LSO BIT(30) +#define RX_DMA_PLEN0 GENMASK(29, 16) +#define RX_DMA_TAG BIT(15) + +struct fe_rx_dma { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; +} __packed __aligned(4); + +#define TX_DMA_PLEN0 GENMASK(29, 16) +#define TX_DMA_LS1 BIT(14) +#define TX_DMA_LS0 BIT(30) +#define TX_DMA_DONE BIT(31) + +#define TX_DMA_INS_VLAN_MT7621 BIT(16) +#define TX_DMA_INS_VLAN BIT(7) +#define TX_DMA_INS_PPPOE BIT(12) +#define TX_DMA_PN GENMASK(26, 24) + +struct fe_tx_dma { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; +} __packed __aligned(4); + +#define NUM_RX_DESC 256 +#define NUM_TX_DESC 4 + +#define PADDING_LENGTH 60 + +#define MTK_QDMA_PAGE_SIZE 2048 + +#define CONFIG_MDIO_TIMEOUT 100 +#define CONFIG_DMA_STOP_TIMEOUT 100 +#define CONFIG_TX_DMA_TIMEOUT 100 + +#define LINK_DELAY_TIME 500 /* 500 ms */ +#define LINK_TIMEOUT 10000 /* 10 seconds */ + +struct mt7628_eth_dev { + void __iomem *base; /* frame engine base address */ + void __iomem *eth_sw_base; /* switch base address */ + struct regmap *sysctrl_regmap; /* system-controller reg-map */ + + struct mii_dev *bus; + + struct fe_tx_dma *tx_ring; + struct fe_rx_dma *rx_ring; + + u8 *rx_buf[NUM_RX_DESC]; + + /* Point to the next RXD DMA wants to use in RXD Ring0 */ + int rx_dma_idx; + /* Point to the next TXD in TXD Ring0 CPU wants to use */ + int tx_dma_idx; +}; + +static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set) +{ + void __iomem *base = priv->eth_sw_base; + int ret; + + ret = wait_for_bit_le32(base + MT7628_SWITCH_PCR1, mask, mask_set, + CONFIG_MDIO_TIMEOUT, false); + if (ret) { + printf("MDIO operation timeout!\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int mii_mgr_read(struct mt7628_eth_dev *priv, + u32 phy_addr, u32 phy_register, u32 *read_data) +{ + void __iomem *base = priv->eth_sw_base; + u32 status = 0; + u32 ret; + + *read_data = 0xffff; + /* Make sure previous read operation is complete */ + ret = mdio_wait_read(priv, PCR1_RD_RDY, false); + if (ret) + return ret; + + writel(PCR0_RD_PHY_CMD | + FIELD_PREP(PCR0_PHY_REG, phy_register) | + FIELD_PREP(PCR0_PHY_ADDR, phy_addr), + base + MT7628_SWITCH_PCR0); + + /* Make sure previous read operation is complete */ + ret = mdio_wait_read(priv, PCR1_RD_RDY, true); + if (ret) + return ret; + + status = readl(base + MT7628_SWITCH_PCR1); + *read_data = FIELD_GET(PCR1_RD_DATA, status); + + return 0; +} + +static int mii_mgr_write(struct mt7628_eth_dev *priv, + u32 phy_addr, u32 phy_register, u32 write_data) +{ + void __iomem *base = priv->eth_sw_base; + u32 data; + int ret; + + /* Make sure previous write operation is complete */ + ret = mdio_wait_read(priv, PCR1_WT_DONE, false); + if (ret) + return ret; + + data = FIELD_PREP(PCR0_WT_DATA, write_data) | + FIELD_PREP(PCR0_PHY_REG, phy_register) | + FIELD_PREP(PCR0_PHY_ADDR, phy_addr) | + PCR0_WT_PHY_CMD; + writel(data, base + MT7628_SWITCH_PCR0); + + return mdio_wait_read(priv, PCR1_WT_DONE, true); +} + +static int mt7628_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + u32 val; + int ret; + + ret = mii_mgr_read(bus->priv, addr, reg, &val); + if (ret) + return ret; + + return val; +} + +static int mt7628_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) +{ + return mii_mgr_write(bus->priv, addr, reg, value); +} + +static void mt7628_ephy_init(struct mt7628_eth_dev *priv) +{ + int i; + + mii_mgr_write(priv, 0, 31, 0x2000); /* change G2 page */ + mii_mgr_write(priv, 0, 26, 0x0000); + + for (i = 0; i < 5; i++) { + mii_mgr_write(priv, i, 31, 0x8000); /* change L0 page */ + mii_mgr_write(priv, i, 0, 0x3100); + + /* EEE disable */ + mii_mgr_write(priv, i, 30, 0xa000); + mii_mgr_write(priv, i, 31, 0xa000); /* change L2 page */ + mii_mgr_write(priv, i, 16, 0x0606); + mii_mgr_write(priv, i, 23, 0x0f0e); + mii_mgr_write(priv, i, 24, 0x1610); + mii_mgr_write(priv, i, 30, 0x1f15); + mii_mgr_write(priv, i, 28, 0x6111); + } + + /* 100Base AOI setting */ + mii_mgr_write(priv, 0, 31, 0x5000); /* change G5 page */ + mii_mgr_write(priv, 0, 19, 0x004a); + mii_mgr_write(priv, 0, 20, 0x015a); + mii_mgr_write(priv, 0, 21, 0x00ee); + mii_mgr_write(priv, 0, 22, 0x0033); + mii_mgr_write(priv, 0, 23, 0x020a); + mii_mgr_write(priv, 0, 24, 0x0000); + mii_mgr_write(priv, 0, 25, 0x024a); + mii_mgr_write(priv, 0, 26, 0x035a); + mii_mgr_write(priv, 0, 27, 0x02ee); + mii_mgr_write(priv, 0, 28, 0x0233); + mii_mgr_write(priv, 0, 29, 0x000a); + mii_mgr_write(priv, 0, 30, 0x0000); + + /* Fix EPHY idle state abnormal behavior */ + mii_mgr_write(priv, 0, 31, 0x4000); /* change G4 page */ + mii_mgr_write(priv, 0, 29, 0x000d); + mii_mgr_write(priv, 0, 30, 0x0500); +} + +static void rt305x_esw_init(struct mt7628_eth_dev *priv) +{ + void __iomem *base = priv->eth_sw_base; + + /* + * FC_RLS_TH=200, FC_SET_TH=160 + * DROP_RLS=120, DROP_SET_TH=80 + */ + writel(0xc8a07850, base + MT7628_SWITCH_FCT0); + writel(0x00000000, base + MT7628_SWITCH_SGC2); + writel(0x00405555, base + MT7628_SWITCH_PFC1); + writel(0x00007f7f, base + MT7628_SWITCH_POC0); + writel(0x00007f7f, base + MT7628_SWITCH_POC2); /* disable VLAN */ + writel(0x0002500c, base + MT7628_SWITCH_FCT2); + /* hashing algorithm=XOR48, aging interval=300sec */ + writel(0x0008a301, base + MT7628_SWITCH_SGC); + writel(0x02404040, base + MT7628_SWITCH_SOCPC); + + /* Ext PHY Addr=0x1f */ + writel(0x3f502b28, base + MT7628_SWITCH_FPA1); + writel(0x00000000, base + MT7628_SWITCH_FPA); + /* 1us cycle number=125 (FE's clock=125Mhz) */ + writel(0x7d000000, base + MT7628_SWITCH_BMU_CTRL); + + /* Configure analog GPIO setup */ + regmap_update_bits(priv->sysctrl_regmap, MT7628_AGPIO_CFG_REG, + MT7628_EPHY_P0_DIS, MT7628_EPHY_GPIO_AIO_EN); + + /* Reset PHY */ + regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG, + 0, RSTCTRL_EPHY_RST); + regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG, + RSTCTRL_EPHY_RST, 0); + mdelay(10); + + /* Set P0 EPHY LED mode */ + regmap_update_bits(priv->sysctrl_regmap, MT7628_GPIO2_MODE_REG, + 0x0ffc0ffc, 0x05540554); + mdelay(10); + + mt7628_ephy_init(priv); +} + +static void eth_dma_start(struct mt7628_eth_dev *priv) +{ + void __iomem *base = priv->base; + + setbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); +} + +static void eth_dma_stop(struct mt7628_eth_dev *priv) +{ + void __iomem *base = priv->base; + int ret; + + clrbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); + + /* Wait for DMA to stop */ + ret = wait_for_bit_le32(base + PDMA_GLO_CFG, + RX_DMA_BUSY | TX_DMA_BUSY, false, + CONFIG_DMA_STOP_TIMEOUT, false); + if (ret) + printf("DMA stop timeout error!\n"); +} + +static int mt7628_eth_write_hwaddr(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + u8 *addr = ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr; + u32 val; + + /* Set MAC address. */ + val = addr[0]; + val = (val << 8) | addr[1]; + writel(val, base + SDM_MAC_ADRH); + + val = addr[2]; + val = (val << 8) | addr[3]; + val = (val << 8) | addr[4]; + val = (val << 8) | addr[5]; + writel(val, base + SDM_MAC_ADRL); + + return 0; +} + +static int mt7628_eth_send(struct udevice *dev, void *packet, int length) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + int ret; + int idx; + int i; + + idx = priv->tx_dma_idx; + + /* Pad message to a minimum length */ + if (length < PADDING_LENGTH) { + char *p = (char *)packet; + + for (i = 0; i < PADDING_LENGTH - length; i++) + p[length + i] = 0; + length = PADDING_LENGTH; + } + + /* Check if buffer is ready for next TX DMA */ + ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true, + CONFIG_TX_DMA_TIMEOUT, false); + if (ret) { + printf("TX: DMA still busy on buffer %d\n", idx); + return ret; + } + + flush_dcache_range((u32)packet, (u32)packet + length); + + priv->tx_ring[idx].txd1 = CPHYSADDR(packet); + priv->tx_ring[idx].txd2 &= ~TX_DMA_PLEN0; + priv->tx_ring[idx].txd2 |= FIELD_PREP(TX_DMA_PLEN0, length); + priv->tx_ring[idx].txd2 &= ~TX_DMA_DONE; + + idx = (idx + 1) % NUM_TX_DESC; + + /* Make sure the writes executed at this place */ + wmb(); + writel(idx, base + TX_CTX_IDX0); + + priv->tx_dma_idx = idx; + + return 0; +} + +static int mt7628_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + u32 rxd_info; + int length; + int idx; + + idx = priv->rx_dma_idx; + + rxd_info = priv->rx_ring[idx].rxd2; + if ((rxd_info & RX_DMA_DONE) == 0) + return -EAGAIN; + + length = FIELD_GET(RX_DMA_PLEN0, priv->rx_ring[idx].rxd2); + if (length == 0 || length > MTK_QDMA_PAGE_SIZE) { + printf("%s: invalid length (%d bytes)\n", __func__, length); + return -EIO; + } + + *packetp = priv->rx_buf[idx]; + invalidate_dcache_range((u32)*packetp, (u32)*packetp + length); + + priv->rx_ring[idx].rxd4 = 0; + priv->rx_ring[idx].rxd2 = RX_DMA_LSO; + + /* Make sure the writes executed at this place */ + wmb(); + + return length; +} + +static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + int idx; + + idx = priv->rx_dma_idx; + + /* Move point to next RXD which wants to alloc */ + writel(idx, base + RX_CALC_IDX0); + + /* Update to Next packet point that was received */ + idx = (idx + 1) % NUM_RX_DESC; + + priv->rx_dma_idx = idx; + + return 0; +} + +static int phy_link_up(struct mt7628_eth_dev *priv) +{ + u32 val; + + mii_mgr_read(priv, 0x00, MII_BMSR, &val); + return !!(val & BMSR_LSTATUS); +} + +static int mt7628_eth_start(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + uchar packet[MTK_QDMA_PAGE_SIZE]; + uchar *packetp; + int i; + + for (i = 0; i < NUM_RX_DESC; i++) { + memset((void *)&priv->rx_ring[i], 0, sizeof(priv->rx_ring[0])); + priv->rx_ring[i].rxd2 |= RX_DMA_LSO; + priv->rx_ring[i].rxd1 = CPHYSADDR(priv->rx_buf[i]); + } + + for (i = 0; i < NUM_TX_DESC; i++) { + memset((void *)&priv->tx_ring[i], 0, sizeof(priv->tx_ring[0])); + priv->tx_ring[i].txd2 = TX_DMA_LS0 | TX_DMA_DONE; + priv->tx_ring[i].txd4 = FIELD_PREP(TX_DMA_PN, 1); + } + + priv->rx_dma_idx = 0; + priv->tx_dma_idx = 0; + + /* Make sure the writes executed at this place */ + wmb(); + + /* disable delay interrupt */ + writel(0, base + DLY_INT_CFG); + + clrbits_le32(base + PDMA_GLO_CFG, 0xffff0000); + + /* Tell the adapter where the TX/RX rings are located. */ + writel(CPHYSADDR(&priv->rx_ring[0]), base + RX_BASE_PTR0); + writel(CPHYSADDR((u32)&priv->tx_ring[0]), base + TX_BASE_PTR0); + + writel(NUM_RX_DESC, base + RX_MAX_CNT0); + writel(NUM_TX_DESC, base + TX_MAX_CNT0); + + writel(priv->tx_dma_idx, base + TX_CTX_IDX0); + writel(RST_DTX_IDX0, base + PDMA_RST_IDX); + + writel(NUM_RX_DESC - 1, base + RX_CALC_IDX0); + writel(RST_DRX_IDX0, base + PDMA_RST_IDX); + + /* Make sure the writes executed at this place */ + wmb(); + eth_dma_start(priv); + + /* Check if link is not up yet */ + if (!phy_link_up(priv)) { + /* Wait for link to come up */ + + printf("Waiting for link to come up ."); + for (i = 0; i < (LINK_TIMEOUT / LINK_DELAY_TIME); i++) { + mdelay(LINK_DELAY_TIME); + if (phy_link_up(priv)) { + mdelay(100); /* Ensure all is ready */ + break; + } + + printf("."); + } + + if (phy_link_up(priv)) + printf(" done\n"); + else + printf(" timeout! Trying anyways\n"); + } + + /* + * The integrated switch seems to queue some received ethernet + * packets in some FIFO. Lets read the already queued packets + * out by using the receive routine, so that these old messages + * are dropped before the new xfer starts. + */ + packetp = &packet[0]; + while (mt7628_eth_recv(dev, 0, &packetp) != -EAGAIN) + mt7628_eth_free_pkt(dev, packetp, 0); + + return 0; +} + +static void mt7628_eth_stop(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + + eth_dma_stop(priv); +} + +static int mt7628_eth_probe(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + struct udevice *syscon; + struct mii_dev *bus; + int ret; + int i; + + /* Save frame-engine base address for later use */ + priv->base = dev_remap_addr_index(dev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + /* Save switch base address for later use */ + priv->eth_sw_base = dev_remap_addr_index(dev, 1); + if (IS_ERR(priv->eth_sw_base)) + return PTR_ERR(priv->eth_sw_base); + + /* Get system controller regmap */ + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, + "syscon", &syscon); + if (ret) { + pr_err("unable to find syscon device\n"); + return ret; + } + + priv->sysctrl_regmap = syscon_get_regmap(syscon); + if (!priv->sysctrl_regmap) { + pr_err("unable to find regmap\n"); + return -ENODEV; + } + + /* Put rx and tx rings into KSEG1 area (uncached) */ + priv->tx_ring = (struct fe_tx_dma *) + KSEG1ADDR(memalign(ARCH_DMA_MINALIGN, + sizeof(*priv->tx_ring) * NUM_TX_DESC)); + priv->rx_ring = (struct fe_rx_dma *) + KSEG1ADDR(memalign(ARCH_DMA_MINALIGN, + sizeof(*priv->rx_ring) * NUM_RX_DESC)); + + for (i = 0; i < NUM_RX_DESC; i++) + priv->rx_buf[i] = memalign(PKTALIGN, MTK_QDMA_PAGE_SIZE); + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = mt7628_mdio_read; + bus->write = mt7628_mdio_write; + snprintf(bus->name, sizeof(bus->name), dev->name); + bus->priv = (void *)priv; + + ret = mdio_register(bus); + if (ret) + return ret; + + /* Switch configuration */ + rt305x_esw_init(priv); + + return 0; +} + +static const struct eth_ops mt7628_eth_ops = { + .start = mt7628_eth_start, + .send = mt7628_eth_send, + .recv = mt7628_eth_recv, + .free_pkt = mt7628_eth_free_pkt, + .stop = mt7628_eth_stop, + .write_hwaddr = mt7628_eth_write_hwaddr, +}; + +static const struct udevice_id mt7628_eth_ids[] = { + { .compatible = "mediatek,mt7628-eth" }, + { } +}; + +U_BOOT_DRIVER(mt7628_eth) = { + .name = "mt7628_eth", + .id = UCLASS_ETH, + .of_match = mt7628_eth_ids, + .probe = mt7628_eth_probe, + .ops = &mt7628_eth_ops, + .priv_auto_alloc_size = sizeof(struct mt7628_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; -- 2.19.1

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