October 2018 - U-Boot

[U-Boot] [PATCH] gpio: pca953x: Clear the polarity invert register at init
by Anatolij Gustschin 17 Nov '18

17 Nov '18

From: Ye Li <ye.li(a)nxp.com> The pca953x_gpio driver uses default value of polarity inversion register. For some devices like PCA9557 and MAX7310, their polarity inversion register default value is 0xf0. So for high 4 ports, when reading their values, the values are inverted as the actual level. This patch clears the polarity inversion register to 0 at init, so that the port read and write values are aligned. Signed-off-by: Ye Li <ye.li(a)nxp.com> Acked-by: Fugang Duan <fugang.duan(a)nxp.com> Acked-by: Peng Fan <peng.fan(a)nxp.com> Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- drivers/gpio/pca953x_gpio.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index 0bb484498a..341527acc5 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -130,6 +130,25 @@ static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val) return ret; } +static int pca953x_write_regs(struct udevice *dev, int reg, u8 *val) +{ + struct pca953x_info *info = dev_get_platdata(dev); + int ret = 0; + + if (info->gpio_count <= 8) { + ret = dm_i2c_write(dev, reg, val, 1); + } else if (info->gpio_count <= 16) { + ret = dm_i2c_write(dev, reg << 1, val, info->bank_count); + } else if (info->gpio_count == 40) { + /* Auto increment */ + ret = dm_i2c_write(dev, (reg << 3) | 0x80, val, info->bank_count); + } else { + return -EINVAL; + } + + return ret; +} + static int pca953x_is_output(struct udevice *dev, int offset) { struct pca953x_info *info = dev_get_platdata(dev); @@ -251,6 +270,7 @@ static int pca953x_probe(struct udevice *dev) int ret; int size; const u8 *tmp; + u8 val[MAX_BANK]; addr = dev_read_addr(dev); if (addr == 0) @@ -296,6 +316,14 @@ static int pca953x_probe(struct udevice *dev) snprintf(name, sizeof(name), "gpio@%x_", info->addr); } + /* Clear the polarity registers to no invert */ + memset(val, 0, MAX_BANK); + ret = pca953x_write_regs(dev, PCA953X_INVERT, val); + if (ret < 0) { + dev_err(dev, "Error writing invert register\n"); + return ret; + } + str = strdup(name); if (!str) return -ENOMEM; -- 2.17.1

2 1

[U-Boot] [PATCH] clk: Allow clock defaults to be set also during re-reloc state
by Lokesh Vutla 17 Nov '18

17 Nov '18

From: Andreas Dannenberg <dannenberg(a)ti.com> The earlier commit f4fcba5c5ba ("clk: implement clk_set_defaults()") which introduced the functionality for setting clock defaults such as rates and parents will skip the processing when executing in a re-reloc state. This for example can prevent the assigning of clock parents when running in SPL code. Go ahead and remove this limitation. Signed-off-by: Andreas Dannenberg <dannenberg(a)ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- - This was introduced to skip assigned-clock-rates in SPL. Instead CONFIG_OF_SPL_REMOVE_PROPS should be used to remove not needed properties in SPL. drivers/clk/clk-uclass.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 2b15978e14..04b369aa5a 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -243,10 +243,6 @@ int clk_set_defaults(struct udevice *dev) { int ret; - /* If this is running pre-reloc state, don't take any action. */ - if (!(gd->flags & GD_FLG_RELOC)) - return 0; - debug("%s(%s)\n", __func__, dev_read_name(dev)); ret = clk_set_default_parents(dev); -- 2.19.1

2 1

[U-Boot] [PATCH 1/3] serial: bcm6858: add serial support
by Philippe Reynes 17 Nov '18

17 Nov '18

This driver add the support of serial on bcm6858. It's based on serial for bcm6345. Signed-off-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- drivers/serial/Kconfig | 6 + drivers/serial/Makefile | 1 + drivers/serial/serial_bcm6858.c | 300 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 307 insertions(+) create mode 100644 drivers/serial/serial_bcm6858.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 5fa2725..4d094c3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -479,6 +479,12 @@ config BCM6345_SERIAL help Select this to enable UART on BCM6345 SoCs. +config BCM6858_SERIAL + bool "Support for BCM6858 UART" + depends on DM_SERIAL && ARCH_BCM6858 + help + Select this to enable UART on BCM6358 SoCs. + config FSL_LINFLEXUART bool "Freescale Linflex UART support" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 03dc29e..a48458f 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o +obj-$(CONFIG_BCM6858_SERIAL) += serial_bcm6858.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o diff --git a/drivers/serial/serial_bcm6858.c b/drivers/serial/serial_bcm6858.c new file mode 100644 index 0000000..8aa3705 --- /dev/null +++ b/drivers/serial/serial_bcm6858.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes <philippe.reynes(a)softathome.com> + * + * Derived from linux/drivers/tty/serial/bcm63xx_uart.c: + * Copyright (C) 2008 Maxime Bizon <mbizon(a)freebox.fr> + * Derived from linux/drivers/tty/serial/serial_bcm6345.c + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari(a)gmail.com> + */ + +#include <clk.h> +#include <dm.h> +#include <debug_uart.h> +#include <errno.h> +#include <serial.h> +#include <asm/io.h> +#include <asm/types.h> + +/* UART Control register */ +#define UART_CTL_REG 0x0 +#define UART_CTL_RXTIMEOUT_MASK 0x1f +#define UART_CTL_RXTIMEOUT_5 0x5 +#define UART_CTL_RSTRXFIFO_SHIFT 6 +#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) +#define UART_CTL_RSTTXFIFO_SHIFT 7 +#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) +#define UART_CTL_STOPBITS_SHIFT 8 +#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) +#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) +#define UART_CTL_BITSPERSYM_SHIFT 12 +#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) +#define UART_CTL_BITSPERSYM_8 (0x3 << UART_CTL_BITSPERSYM_SHIFT) +#define UART_CTL_XMITBRK_SHIFT 14 +#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) +#define UART_CTL_RSVD_SHIFT 15 +#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) +#define UART_CTL_RXPAREVEN_SHIFT 16 +#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) +#define UART_CTL_RXPAREN_SHIFT 17 +#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) +#define UART_CTL_TXPAREVEN_SHIFT 18 +#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) +#define UART_CTL_TXPAREN_SHIFT 19 +#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) +#define UART_CTL_LOOPBACK_SHIFT 20 +#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) +#define UART_CTL_RXEN_SHIFT 21 +#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) +#define UART_CTL_TXEN_SHIFT 22 +#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) +#define UART_CTL_BRGEN_SHIFT 23 +#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) + +/* UART Baudword register */ +#define UART_BAUD_REG 0x4 + +/* UART FIFO Config register */ +#define UART_FIFO_CFG_REG 0x8 +#define UART_FIFO_CFG_RX_SHIFT 8 +#define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT) +#define UART_FIFO_CFG_RX_4 (0x4 << UART_FIFO_CFG_RX_SHIFT) +#define UART_FIFO_CFG_TX_SHIFT 12 +#define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT) +#define UART_FIFO_CFG_TX_4 (0x4 << UART_FIFO_CFG_TX_SHIFT) + +/* UART Interrupt register */ +#define UART_IR_REG 0x10 +#define UART_IR_STAT(x) (1 << (x)) +#define UART_IR_TXEMPTY 5 +#define UART_IR_RXOVER 7 +#define UART_IR_RXNOTEMPTY 11 + +/* UART FIFO register */ +#define UART_FIFO_REG 0x14 +#define UART_FIFO_VALID_MASK 0xff +#define UART_FIFO_FRAMEERR_SHIFT 8 +#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) +#define UART_FIFO_PARERR_SHIFT 9 +#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) +#define UART_FIFO_BRKDET_SHIFT 10 +#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) +#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ + UART_FIFO_PARERR_MASK | \ + UART_FIFO_BRKDET_MASK) + +struct bcm6858_serial_priv { + void __iomem *base; + ulong uartclk; +}; + +/* enable rx & tx operation on uart */ +static void bcm6858_serial_enable(void __iomem *base) +{ + setbits_le32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | + UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); +} + +/* disable rx & tx operation on uart */ +static void bcm6858_serial_disable(void __iomem *base) +{ + clrbits_le32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | + UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); +} + +/* clear all unread data in rx fifo and unsent data in tx fifo */ +static void bcm6858_serial_flush(void __iomem *base) +{ + /* empty rx and tx fifo */ + setbits_le32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | + UART_CTL_RSTTXFIFO_MASK); + + /* read any pending char to make sure all irq status are cleared */ + readl(base + UART_FIFO_REG); +} + +static int bcm6858_serial_init(void __iomem *base, ulong clk, u32 baudrate) +{ + u32 val; + + /* mask all irq and flush port */ + bcm6858_serial_disable(base); + bcm6858_serial_flush(base); + + /* set uart control config */ + clrsetbits_le32(base + UART_CTL_REG, + /* clear rx timeout */ + UART_CTL_RXTIMEOUT_MASK | + /* clear stop bits */ + UART_CTL_STOPBITS_MASK | + /* clear bits per symbol */ + UART_CTL_BITSPERSYM_MASK | + /* clear xmit break */ + UART_CTL_XMITBRK_MASK | + /* clear reserved bit */ + UART_CTL_RSVD_MASK | + /* disable parity */ + UART_CTL_RXPAREN_MASK | + UART_CTL_TXPAREN_MASK | + /* disable loopback */ + UART_CTL_LOOPBACK_MASK, + /* set timeout to 5 */ + UART_CTL_RXTIMEOUT_5 | + /* set 8 bits/symbol */ + UART_CTL_BITSPERSYM_8 | + /* set 1 stop bit */ + UART_CTL_STOPBITS_1 | + /* set parity to even */ + UART_CTL_RXPAREVEN_MASK | + UART_CTL_TXPAREVEN_MASK); + + /* set uart fifo config */ + clrsetbits_le32(base + UART_FIFO_CFG_REG, + /* clear fifo config */ + UART_FIFO_CFG_RX_MASK | + UART_FIFO_CFG_TX_MASK, + /* set fifo config to 4 */ + UART_FIFO_CFG_RX_4 | + UART_FIFO_CFG_TX_4); + + /* set baud rate */ + val = ((clk / baudrate) >> 4); + if (val & 0x1) + val = (val >> 1); + else + val = (val >> 1) - 1; + writel(val, base + UART_BAUD_REG); + + /* clear interrupts */ + writel(0, base + UART_IR_REG); + + /* enable uart */ + bcm6858_serial_enable(base); + + return 0; +} + +static int bcm6858_serial_pending(struct udevice *dev, bool input) +{ + struct bcm6858_serial_priv *priv = dev_get_priv(dev); + u32 val = readl(priv->base + UART_IR_REG); + + if (input) + return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)); + else + return !(val & UART_IR_STAT(UART_IR_TXEMPTY)); +} + +static int bcm6858_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct bcm6858_serial_priv *priv = dev_get_priv(dev); + + return bcm6858_serial_init(priv->base, priv->uartclk, baudrate); +} + +static int bcm6858_serial_putc(struct udevice *dev, const char ch) +{ + struct bcm6858_serial_priv *priv = dev_get_priv(dev); + u32 val; + + val = readl(priv->base + UART_IR_REG); + if (!(val & UART_IR_STAT(UART_IR_TXEMPTY))) + return -EAGAIN; + + writel(ch, priv->base + UART_FIFO_REG); + + return 0; +} + +static int bcm6858_serial_getc(struct udevice *dev) +{ + struct bcm6858_serial_priv *priv = dev_get_priv(dev); + u32 val; + + val = readl(priv->base + UART_IR_REG); + if (val & UART_IR_STAT(UART_IR_RXOVER)) + setbits_le32(priv->base + UART_CTL_REG, + UART_CTL_RSTRXFIFO_MASK); + + if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY))) + return -EAGAIN; + + val = readl(priv->base + UART_FIFO_REG); + if (val & UART_FIFO_ANYERR_MASK) + return -EAGAIN; + + return val & UART_FIFO_VALID_MASK; +} + +static int bcm6858_serial_probe(struct udevice *dev) +{ + struct bcm6858_serial_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; + + /* get address */ + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + + /* get clock rate */ + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + priv->uartclk = clk_get_rate(&clk); + clk_free(&clk); + + /* initialize serial */ + return bcm6858_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE); +} + +static const struct dm_serial_ops bcm6858_serial_ops = { + .putc = bcm6858_serial_putc, + .pending = bcm6858_serial_pending, + .getc = bcm6858_serial_getc, + .setbrg = bcm6858_serial_setbrg, +}; + +static const struct udevice_id bcm6858_serial_ids[] = { + { .compatible = "brcm,bcm6858-uart" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6858_serial) = { + .name = "bcm6858-uart", + .id = UCLASS_SERIAL, + .of_match = bcm6858_serial_ids, + .probe = bcm6858_serial_probe, + .priv_auto_alloc_size = sizeof(struct bcm6858_serial_priv), + .ops = &bcm6858_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#ifdef CONFIG_DEBUG_UART_BCM6858 +static inline void _debug_uart_init(void) +{ + void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + + bcm6858_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); +} + +static inline void wait_xfered(void __iomem *base) +{ + do { + u32 val = readl(base + UART_IR_REG); + if (val & UART_IR_STAT(UART_IR_TXEMPTY)) + break; + } while (1); +} + +static inline void _debug_uart_putc(int ch) +{ + void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + + wait_xfered(base); + writel(ch, base + UART_FIFO_REG); + wait_xfered(base); +} + +DEBUG_UART_FUNCS +#endif -- 2.7.4

2 5

[U-Boot] [PATCH 1/1] cmd/bdinfo: correct output of numerical values
by Heinrich Schuchardt 17 Nov '18

17 Nov '18

Display all digits on 64bit systems. Currently we print only the lower 32 bits. Examples of values that can exceed 32 bits are the size and start of memory banks. For fdt_blob use the same output method as for other values. This avoids misalignment. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- cmd/bdinfo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 60b438766d..cbeba6ba28 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR; __maybe_unused static void print_num(const char *name, ulong value) { - printf("%-12s= 0x%08lX\n", name, value); + printf("%-12s= 0x%0*lx\n", name, 2 * (int)sizeof(value), value); } __maybe_unused @@ -348,7 +348,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, CONFIG_VAL(SYS_MALLOC_F_LEN)); #endif if (gd->fdt_blob) - printf("fdt_blob = %p\n", gd->fdt_blob); + print_num("fdt_blob", (ulong)gd->fdt_blob); return 0; } -- 2.19.1

2 1

[U-Boot] [PATCH v3] arm: at91: wdt: Convert watchdog driver to dm/dt
by Prasanthi Chellakumar 17 Nov '18

17 Nov '18

Convert the Watchdog driver for AT91SAM9x processors to support the driver model and device tree. Changes "CONFIG_AT91SAM9_WATCHDOG" to new "CONFIG_WDT_AT91" Kconfig option. Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar(a)microchip.com> --- arch/arm/dts/at91sam9260-smartweb.dts | 1 + arch/arm/dts/at91sam9g20-taurus.dts | 1 + arch/arm/mach-at91/include/mach/at91_wdt.h | 6 +- arch/arm/mach-at91/spl.c | 2 +- arch/arm/mach-at91/spl_at91.c | 2 +- arch/arm/mach-at91/spl_atmel.c | 2 +- common/board_f.c | 2 +- configs/picosam9g45_defconfig | 4 ++ configs/smartweb_defconfig | 3 + configs/taurus_defconfig | 3 + doc/README.at91 | 2 +- doc/README.watchdog | 2 +- drivers/watchdog/Kconfig | 10 +++ drivers/watchdog/Makefile | 2 +- drivers/watchdog/at91sam9_wdt.c | 104 ++++++++++++++++++++++------- include/configs/picosam9g45.h | 4 -- include/configs/smartweb.h | 7 -- include/configs/taurus.h | 7 -- scripts/config_whitelist.txt | 1 - 19 files changed, 114 insertions(+), 51 deletions(-) diff --git a/arch/arm/dts/at91sam9260-smartweb.dts b/arch/arm/dts/at91sam9260-smartweb.dts index e59781b..a22de2d 100644 --- a/arch/arm/dts/at91sam9260-smartweb.dts +++ b/arch/arm/dts/at91sam9260-smartweb.dts @@ -89,6 +89,7 @@ }; watchdog@fffffd40 { + timeout-sec = <15>; status = "okay"; }; diff --git a/arch/arm/dts/at91sam9g20-taurus.dts b/arch/arm/dts/at91sam9g20-taurus.dts index 7931c0a..cee228b 100644 --- a/arch/arm/dts/at91sam9g20-taurus.dts +++ b/arch/arm/dts/at91sam9g20-taurus.dts @@ -98,6 +98,7 @@ }; watchdog@fffffd40 { + timeout-sec = <15>; status = "okay"; }; diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index 99b0cc8..cd22723 100644 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -4,7 +4,7 @@ * * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. + * Copyright (C) 2018 Microchip Technology Inc. * * Watchdog Timer (WDT) - System peripherals regsters. * Based on AT91SAM9261 datasheet revision D. @@ -27,9 +27,13 @@ typedef struct at91_wdt { #endif +/* Watchdog Control Register */ +#define AT91_WDT_CR 0x00 #define AT91_WDT_CR_WDRSTT 1 #define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ +/* Watchdog Mode Register*/ +#define AT91_WDT_MR 0X04 #define AT91_WDT_MR_WDV(x) (x & 0xfff) #define AT91_WDT_MR_WDFIEN 0x00001000 #define AT91_WDT_MR_WDRSTEN 0x00002000 diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index 8bfb2a4..6da6d41 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -11,7 +11,7 @@ #include <asm/arch/clk.h> #include <spl.h> -#if !defined(CONFIG_AT91SAM9_WATCHDOG) +#if !defined(CONFIG_WDT_AT91) void at91_disable_wdt(void) { struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index 8c36804..23ebaa9 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -76,7 +76,7 @@ void __weak spl_board_init(void) void board_init_f(ulong dummy) { lowlevel_clock_init(); -#if !defined(CONFIG_AT91SAM9_WATCHDOG) +#if !defined(CONFIG_WDT_AT91) at91_disable_wdt(); #endif diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 597ff8c..ef745c9 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -98,7 +98,7 @@ void board_init_f(ulong dummy) configure_2nd_sram_as_l2_cache(); #endif -#if !defined(CONFIG_AT91SAM9_WATCHDOG) +#if !defined(CONFIG_WDT_AT91) /* disable watchdog */ at91_disable_wdt(); #endif diff --git a/common/board_f.c b/common/board_f.c index 213d044..02223db 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -91,7 +91,7 @@ static int init_func_watchdog_init(void) { # if defined(CONFIG_HW_WATCHDOG) && \ (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ - defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ + defined(CONFIG_SH) || \ defined(CONFIG_DESIGNWARE_WATCHDOG) || \ defined(CONFIG_IMX_WATCHDOG)) hw_watchdog_init(); diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig index 0b6234f..be9cb5c 100644 --- a/configs/picosam9g45_defconfig +++ b/configs/picosam9g45_defconfig @@ -39,3 +39,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LCD=y CONFIG_OF_LIBFDT=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_WDT=y +CONFIG_WDT_AT91=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index b0bb18a..3204211 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -60,3 +60,6 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_SPL_TINY_MEMSET=y # CONFIG_EFI_LOADER is not set +CONFIG_WDT=y +CONFIG_WDT_AT91=y +CONFIG_AT91_HW_WDT_TIMEOUT=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index bafd8ab..8925d85 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -62,3 +62,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0908 CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USE_TINY_PRINTF=y +CONFIG_WDT=y +CONFIG_WDT_AT91=y +CONFIG_AT91_HW_WDT_TIMEOUT=y diff --git a/doc/README.at91 b/doc/README.at91 index 6741213..39dd563 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -171,4 +171,4 @@ III. Watchdog support your code (make sure not to disable it in AT91Bootstrap for instance). In the U-Boot configuration, the AT91 watchdog support is enabled using - the CONFIG_AT91SAM9_WATCHDOG and CONFIG_HW_WATCHDOG options. + the CONFIG_WDT and CONFIG_WDT_AT91 options. diff --git a/doc/README.watchdog b/doc/README.watchdog index 7097c87..f23c923 100644 --- a/doc/README.watchdog +++ b/doc/README.watchdog @@ -14,7 +14,7 @@ CONFIG_WATCHDOG_TIMEOUT_MSECS If not given, will default to maximum timeout. This would be 128000 msec for i.mx31/35/5x/6x. -CONFIG_AT91SAM9_WATCHDOG +CONFIG_WDT_AT91 Available for AT91SAM9 to service the watchdog. CONFIG_FTWDT010_WATCHDOG diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index d545b3e..276d6c4 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -111,4 +111,14 @@ config XILINX_TB_WATCHDOG Select this to enable Xilinx Axi watchdog timer, which can be found on some Xilinx Microblaze Platforms. +config WDT_AT91 + bool "AT91 watchdog timer support" + depends on WDT + help + Select this to enable Microchip watchdog timer, which can be found on + some AT91 devices. + +config AT91_HW_WDT_TIMEOUT + bool "AT91 watchdog timeout specified" + depends on WDT_AT91 endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 08406ca..a5c27b0 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2008 # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o +obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610)) obj-y += imx_watchdog.o diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index fca2849..13f8772 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -2,7 +2,7 @@ /* * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c] * - * Watchdog driver for Atmel AT91SAM9x processors. + * Watchdog driver for AT91SAM9x processors. * * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> * Copyright (C) 2008 Renaud CERRATO r.cerrato(a)til-technologies.fr @@ -14,38 +14,47 @@ * write to this register. Inform Linux to it too */ -#include <common.h> -#include <watchdog.h> -#include <asm/arch/hardware.h> #include <asm/io.h> #include <asm/arch/at91_wdt.h> +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <wdt.h> + +DECLARE_GLOBAL_DATA_PTR; /* * AT91SAM9 watchdog runs a 12bit counter @ 256Hz, * use this to convert a watchdog - * value from/to milliseconds. + * value from seconds. */ -#define ms_to_ticks(t) (((t << 8) / 1000) - 1) -#define ticks_to_ms(t) (((t + 1) * 1000) >> 8) +#define WDT_SEC2TICKS(s) (((s) << 8) - 1) /* Hardware timeout in seconds */ -#if !defined(CONFIG_AT91_HW_WDT_TIMEOUT) -#define WDT_HW_TIMEOUT 2 -#else -#define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT -#endif +#define WDT_MAX_TIMEOUT 16 +#define WDT_MIN_TIMEOUT 0 +#define WDT_DEFAULT_TIMEOUT 2 + +struct at91_wdt_priv { + void __iomem *regs; + u32 regval; + u32 timeout; +}; /* * Set the watchdog time interval in 1/256Hz (write-once) * Counter is 12 bit. */ -static int at91_wdt_settimeout(unsigned int timeout) +static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags) { - unsigned int reg; - at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; + struct at91_wdt_priv *priv = dev_get_priv(dev); + u32 timeout = WDT_SEC2TICKS(timeout_s); + + if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT) + timeout = priv->timeout; /* Check if disabled */ - if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { + if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) { printf("sorry, watchdog is disabled\n"); return -1; } @@ -57,24 +66,71 @@ static int at91_wdt_settimeout(unsigned int timeout) * 4096 / 256 = 16 seconds. */ - reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ + priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ | AT91_WDT_MR_WDV(timeout); /* timer value */ - writel(reg, &wd->mr); + writel(priv->regval, priv->regs + AT91_WDT_MR); + + return 0; +} + +static int at91_wdt_stop(struct udevice *dev) +{ + struct at91_wdt_priv *priv = dev_get_priv(dev); + + /* Disable Watchdog Timer */ + priv->regval |= AT91_WDT_MR_WDDIS; + writel(priv->regval, priv->regs + AT91_WDT_MR); return 0; } -void hw_watchdog_reset(void) +static int at91_wdt_reset(struct udevice *dev) { - at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; - writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr); + struct at91_wdt_priv *priv = dev_get_priv(dev); + + writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, priv->regs + AT91_WDT_CR); + + return 0; } -void hw_watchdog_init(void) +static const struct wdt_ops at91_wdt_ops = { + .start = at91_wdt_start, + .stop = at91_wdt_stop, + .reset = at91_wdt_reset, +}; + +static const struct udevice_id at91_wdt_ids[] = { + { .compatible = "atmel,at91sam9260-wdt" }, + {} +}; + +static int at91_wdt_probe(struct udevice *dev) { - /* 16 seconds timer, resets enabled */ - at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000)); + struct at91_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = dev_remap_addr(dev); + if (!priv->regs) + return -EINVAL; + +#ifdef CONFIG_AT91_HW_WDT_TIMEOUT + priv->timeout = dev_read_u32_default(dev, "timeout-sec", + WDT_DEFAULT_TIMEOUT); + debug("%s: timeout %d", __func__, priv->timeout); +#endif + + debug("%s: Probing wdt%u\n", __func__, dev->seq); + + return 0; } + +U_BOOT_DRIVER(at91_wdt) = { + .name = "at91_wdt", + .id = UCLASS_WDT, + .of_match = at91_wdt_ids, + .priv_auto_alloc_size = sizeof(struct at91_wdt_priv), + .ops = &at91_wdt_ops, + .probe = at91_wdt_probe, +}; diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h index 0b240e7..c2882e6 100644 --- a/include/configs/picosam9g45.h +++ b/include/configs/picosam9g45.h @@ -57,10 +57,6 @@ */ #define CONFIG_BOOTP_BOOTFILESIZE -/* Enable the watchdog */ -#define CONFIG_AT91SAM9_WATCHDOG -#define CONFIG_HW_WATCHDOG - /* * Command line configuration. */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 114b87e..28af575 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -112,13 +112,6 @@ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \ "dhcp" -/* Enable the watchdog */ -#define CONFIG_AT91SAM9_WATCHDOG -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_HW_WATCHDOG -#endif -#define CONFIG_AT91_HW_WDT_TIMEOUT 15 - #if !defined(CONFIG_SPL_BUILD) /* USB configuration */ #define CONFIG_USB_ATMEL diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 4fdb0dd..f283ab7 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -85,13 +85,6 @@ #define CONFIG_RMII #define CONFIG_AT91_WANTS_COMMON_PHY -#define CONFIG_AT91SAM9_WATCHDOG -#define CONFIG_AT91_HW_WDT_TIMEOUT 15 -#if !defined(CONFIG_SPL_BUILD) -/* Enable the watchdog */ -#define CONFIG_HW_WATCHDOG -#endif - /* USB */ #if defined(CONFIG_BOARD_TAURUS) #define CONFIG_USB_ATMEL diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e805b1e..72f3d29 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -82,7 +82,6 @@ CONFIG_AT91SAM9G20EK_2MMC CONFIG_AT91SAM9G45EKES CONFIG_AT91SAM9G45_LCD_BASE CONFIG_AT91SAM9M10G45EK -CONFIG_AT91SAM9_WATCHDOG CONFIG_AT91_CAN CONFIG_AT91_EFLASH CONFIG_AT91_GPIO_PULLUP -- 2.7.4

2 1

[U-Boot] [PATCH v1 0/3] Enable all asynchronous abort exceptions taken to EL3
by chee.hong.ang＠intel.com 17 Nov '18

17 Nov '18

From: "Ang, Chee Hong" <chee.hong.ang(a)intel.com> This patchset allow PSCI exception vectors to handle all external abort and SError exception from all exception levels. This will allow EL3 to handle asynchronous abort exceptions such as ECC DBE (Double Bit Error) taken from OS running at lower exception level. Chee Hong Ang (3): ARMv8: Enable all asynchronous abort exceptions taken to EL3 ARMv8: Add EL3 exception handling for ARMv8's Kconfig ARMv8: SError exception handling in PSCI exception vectors arch/arm/cpu/armv8/Kconfig | 7 +++++++ arch/arm/cpu/armv8/psci.S | 26 ++++++++++++++++++++++++++ arch/arm/include/asm/macro.h | 4 ++++ arch/arm/include/asm/system.h | 1 + 4 files changed, 38 insertions(+) -- 2.7.4

2 6

[U-Boot] [RFC][PATCH] ARM: at91: lds: add test SPL binary size and bbs size
by Eugen.Hristev＠microchip.com 16 Nov '18

16 Nov '18

From: Wenyou Yang <wenyou.yang(a)atmel.com> Add the test for the SPL binary size and the bbs section size. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- Hello, This patch from our at91 tree will check for the SPL size and BSS size, however, with this check, build will fail for some old platforms. The solution would be to disable SPL for these failing platform, where SPL cannot work anyway (too big for the SRAM where it's supposed to be loaded) or work through the SPL to make it smaller (remove some support from it). Which is the best approach we should pursue ? The check would be good anyway to avoid oversizing the SPL. Any thoughts? Thanks, Eugen arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index eca78f8..82098dc 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -48,3 +48,13 @@ SECTIONS __bss_end = .; } >.sdram } + +#if defined(CONFIG_SPL_MAX_SIZE) +ASSERT(__image_copy_end - __image_copy_start < (CONFIG_SPL_MAX_SIZE), \ + "SPL image too big"); +#endif + +#if defined(CONFIG_SPL_BSS_MAX_SIZE) +ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \ + "SPL image BSS too big"); +#endif -- 2.7.4

2 1

[U-Boot] [PATCH v3 0/8] Improvements for the dwc3_generic driver
by Jean-Jacques Hiblot 16 Nov '18

16 Nov '18

This series aims at bringing improvements to the dwc3_generic driver so that it can be used by most of the platforms using the dwc3 controller. I tested this on with DRA7 and AM57x platforms for both Peripheral and Host operations. The code to enable DM USB host & dev support for those platforms will be submitted in a separate series. Michal Simek has tested this series: " I have tested it on zcu100 with usb stick, usb to ethernet converter and also dfu. Tested-by: Michal Simek <michal.simek(a)xilinx.com>" Enhancements: - use separate Kconfig option for DM USB Periphal and DM USB Host. This allow platforms to keep their non-DM USB peripheral code and use the DM USB host. - fixes the bind/probe confusion in dwc3_generic. The probe is done when the USB device is first needed. - handles PHYs when in the peripheral mode. The code to handle the PHYs is shared with the host side - handles clock and reset - bind host controller to the more generic driver 'xhci-dwc3' Changes in v3: - fixes bug dwc3_setup_phy(): the phy arrays wasn't returned. This was visible only when the device is removed. - Stub the DWC3 PHY operations if CONFIG_IS_ENABLED(PHY) is false. This fixes all build issues but one (evb-rk3328). - Fix build issue with evb-rk3328 by enabling CONFIG_USB_DWC3. This has little impact on the footprint and should not break the runtime as the xhci-rockchip driver has its own probe function. Nevertheless this was !!! NOT TESTED !!! by lack of hw Changes in v2: - Updated commit log - Fixed typo in thordown.c - select DM_USB_DEV by default for zynqmp platforms Jean-Jacques Hiblot (8): usb: gadget: Do not call board_usb_xxx() directly in USB gadget drivers usb: introduce a separate config option for DM USB device usb: udc: implement DM versions of usb_gadget_initialize()/_release()/_handle_interrupt() dwc3_generic: do not probe the USB device driver when it's bound dwc3: move phy operation to core.c configs: evb-rk3328: Enable CONFIG_USB_DWC3 dwc3-generic: Handle the PHYs, the clocks and the reset lines dwc3-generic: Add select_dr_mode operation arch/arm/Kconfig | 2 + cmd/fastboot.c | 4 +- cmd/rockusb.c | 4 +- cmd/thordown.c | 4 +- cmd/usb_gadget_sdp.c | 4 +- cmd/usb_mass_storage.c | 4 +- common/dfu.c | 6 +- configs/evb-rk3328_defconfig | 1 + drivers/usb/Kconfig | 6 ++ drivers/usb/dwc3/Kconfig | 7 +- drivers/usb/dwc3/core.c | 89 +++++++++++++++- drivers/usb/dwc3/dwc3-generic.c | 207 +++++++++++++++++++++++++++++--------- drivers/usb/dwc3/ep0.c | 1 - drivers/usb/gadget/ether.c | 38 +------ drivers/usb/gadget/udc/udc-core.c | 44 +++++++- drivers/usb/host/xhci-dwc3.c | 95 ++--------------- include/dwc3-uboot.h | 19 ++++ include/linux/usb/gadget.h | 18 ++++ 18 files changed, 367 insertions(+), 186 deletions(-) -- 2.7.4

7 24

[U-Boot] [PATCH v2 1/2] power: regulator: add driver for the FAN53555 family
by Philipp Tomsich 16 Nov '18

16 Nov '18

This adds a driver for the FAN53555 family of regulators. While these devices support a 'normal' and 'suspend' mode (controlled via an external pin) to switch between two programmable voltages, this incarnation of the driver assumes that the device is always operating in 'normal' mode. Only setting/reading the programmed voltage is supported at this time and the following device functionality remains unsupported: - switching the selected voltage (via a GPIO) - disabling the voltage output via software-control This matches the functionality of the Linux driver. Tested on a RK3399-Q7 (with 'option 5' devices): setting voltages from the U-Boot shell and verifying output voltages on the board. Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger(a)theobroma-systems.com> --- Changes in v2: - adapted documentation on the device-tree binding from Linux doc/device-tree-bindings/regulator/fan53555.txt | 23 +++ drivers/power/regulator/Kconfig | 14 ++ drivers/power/regulator/Makefile | 1 + drivers/power/regulator/fan53555.c | 255 ++++++++++++++++++++++++ 4 files changed, 293 insertions(+) create mode 100644 doc/device-tree-bindings/regulator/fan53555.txt create mode 100644 drivers/power/regulator/fan53555.c diff --git a/doc/device-tree-bindings/regulator/fan53555.txt b/doc/device-tree-bindings/regulator/fan53555.txt new file mode 100644 index 0000000..b183738 --- /dev/null +++ b/doc/device-tree-bindings/regulator/fan53555.txt @@ -0,0 +1,23 @@ +Binding for Fairchild FAN53555 regulators + +Required properties: + - compatible: "fcs,fan53555" + - reg: I2C address + +Optional properties: + - fcs,suspend-voltage-selector: declare which of the two available + voltage selector registers should be used for the suspend + voltage. The other one is used for the runtime voltage setting + Possible values are either <0> or <1> + - vin-supply: regulator supplying the vin pin + +Example: + + regulator@40 { + compatible = "fcs,fan53555"; + regulator-name = "fan53555"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&parent_reg>; + fcs,suspend-voltage-selector = <1>; + }; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 8892fa1..c26a765 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -69,6 +69,20 @@ config DM_REGULATOR_MAX77686 features for REGULATOR MAX77686. The driver implements get/set api for: value, enable and mode. +config DM_REGULATOR_FAN53555 + bool "Enable Driver Model for REGULATOR FAN53555" + depends on DM_REGULATOR && DM_I2C + ---help--- + This config enables implementation of driver-model regulator uclass + features for the FAN53555 regulator. The FAN53555 is a (family of) + single-output regulators that supports transitioning between two + different output voltages based on an voltage selection pin. + + The driver implements a get/set api for the voltage of the 'normal + mode' voltage only. Switching to 'suspend mode' (i.e. the alternate + voltage), disabling output via software, or switching the mode is + not supported by this driver (at this time). + config DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value" depends on DM_REGULATOR diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 6c149a9..21040ea 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o diff --git a/drivers/power/regulator/fan53555.c b/drivers/power/regulator/fan53555.c new file mode 100644 index 0000000..3f0b4e9 --- /dev/null +++ b/drivers/power/regulator/fan53555.c @@ -0,0 +1,255 @@ +/* + * (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <bitfield.h> +#include <errno.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <power/pmic.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The voltage ramp (i.e. minimum voltage and step) is defined by the + * combination of 2 nibbles: DIE_ID and DIE_REV. + * + * See http://www.onsemi.com/pub/Collateral/FAN53555-D.pdf for details. + */ +static const struct { + u8 die_id; + u8 die_rev; + u32 vsel_min; + u32 vsel_step; +} ic_types[] = { + { 0x0, 0x3, 600000, 10000 }, /* Option 00 */ + { 0x0, 0xf, 800000, 10000 }, /* Option 13 */ + { 0x0, 0xc, 600000, 12500 }, /* Option 23 */ + { 0x1, 0x3, 600000, 10000 }, /* Option 01 */ + { 0x3, 0x3, 600000, 10000 }, /* Option 03 */ + { 0x4, 0xf, 603000, 12826 }, /* Option 04 */ + { 0x5, 0x3, 600000, 10000 }, /* Option 05 */ + { 0x8, 0x1, 600000, 10000 }, /* Option 08 */ + { 0x8, 0xf, 600000, 10000 }, /* Option 08 */ + { 0xc, 0xf, 603000, 12826 }, /* Option 09 */ +}; + +/* I2C-accessible byte-sized registers */ +enum { + /* Voltage setting */ + FAN53555_VSEL0 = 0x00, + FAN53555_VSEL1, + /* Control register */ + FAN53555_CONTROL, + /* IC Type */ + FAN53555_ID1, + /* IC mask version */ + FAN53555_ID2, + /* Monitor register */ + FAN53555_MONITOR, +}; + +struct fan53555_platdata { + /* Voltage setting register */ + unsigned int vol_reg; + unsigned int sleep_reg; + +}; + +struct fan53555_priv { + /* IC Vendor */ + unsigned int vendor; + /* IC Type and Rev */ + unsigned int die_id; + unsigned int die_rev; + /* Voltage range and step(linear) */ + unsigned int vsel_min; + unsigned int vsel_step; + /* Voltage slew rate limiting */ + unsigned int slew_rate; + /* Sleep voltage cache */ + unsigned int sleep_vol_cache; +}; + +static int fan53555_write(struct udevice *dev, uint reg, u8 *buff, int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) { + debug("%s: %s() failed to read reg %d\n", + dev->name, __func__, reg); + return ret; + } + + return 0; +} + +static int fan53555_read(struct udevice *dev, uint reg, u8 *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) { + debug("%s: %s() failed to read reg %d\n", + dev->name, __func__, reg); + return ret; + } + + return 0; +} + +static int fan53555_regulator_ofdata_to_platdata(struct udevice *dev) +{ + struct fan53555_platdata *dev_pdata = dev_get_platdata(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + u32 sleep_vsel; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + /* This is a buck regulator */ + uc_pdata->type = REGULATOR_TYPE_BUCK; + + sleep_vsel = dev_read_u32_default(dev, "fcs,suspend-voltage-selector", + FAN53555_VSEL1); + + /* + * Depending on the device-tree settings, the 'normal mode' + * voltage is either controlled by VSEL0 or VSEL1. + */ + switch (sleep_vsel) { + case FAN53555_VSEL0: + dev_pdata->sleep_reg = FAN53555_VSEL0; + dev_pdata->vol_reg = FAN53555_VSEL1; + break; + case FAN53555_VSEL1: + dev_pdata->sleep_reg = FAN53555_VSEL1; + dev_pdata->vol_reg = FAN53555_VSEL0; + break; + default: + pr_err("%s: invalid vsel id %d\n", dev->name, sleep_vsel); + return -EINVAL; + } + + return 0; +} + +static int fan53555_regulator_get_value(struct udevice *dev) +{ + struct fan53555_platdata *pdata = dev_get_platdata(dev); + struct fan53555_priv *priv = dev_get_priv(dev); + u8 vol; + int voltage; + + /* We only support a single voltage selector (i.e. 'normal' mode). */ + fan53555_read(dev, pdata->vol_reg, &vol, 1); + voltage = priv->vsel_min + (vol & 0x3f) * priv->vsel_step; + + debug("%s: %d uV\n", __func__, voltage); + return voltage; +} + +static int fan53555_regulator_set_value(struct udevice *dev, int uV) +{ + struct fan53555_platdata *pdata = dev_get_platdata(dev); + struct fan53555_priv *priv = dev_get_priv(dev); + u8 vol, oldbits, newbits; + + vol = (uV - priv->vsel_min) / priv->vsel_step; + fan53555_read(dev, pdata->vol_reg, &oldbits, 1); + newbits = bitfield_replace(oldbits, 0, 6, vol); + fan53555_write(dev, pdata->vol_reg, &newbits, 1); + + debug("%s: uV=%d; reg %d: %02x -> %02x\n", + __func__, uV, pdata->vol_reg, oldbits, newbits); + + return 0; +} + +static int fan53555_voltages_setup(struct udevice *dev) +{ + struct fan53555_priv *priv = dev_get_priv(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + int i; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + /* Init voltage range and step */ + for (i = 0; i < ARRAY_SIZE(ic_types); ++i) { + if (ic_types[i].die_id != priv->die_id) + continue; + + if (ic_types[i].die_rev != priv->die_rev) + continue; + + priv->vsel_min = ic_types[i].vsel_min; + priv->vsel_step = ic_types[i].vsel_step; + + return 0; + } + + pr_err("%s: %s: die id %d rev %d not supported!\n", + dev->name, __func__, priv->die_id, priv->die_rev); + return -EINVAL; +} + +enum { + DIE_ID_SHIFT = 0, + DIE_ID_WIDTH = 4, + DIE_REV_SHIFT = 0, + DIE_REV_WIDTH = 4, +}; + + +static int fan53555_probe(struct udevice *dev) +{ + struct fan53555_priv *priv = dev_get_priv(dev); + u8 id1, id2; + + /* read chip id: vendor, die-id and die-revision */ + fan53555_read(dev, FAN53555_ID1, &id1, 1); + fan53555_read(dev, FAN53555_ID2, &id2, 1); + + priv->vendor = bitfield_extract(id1, 5, 3); + priv->die_id = id1 & GENMASK(3, 0); + priv->die_rev = id2 & GENMASK(3, 0); + + if (fan53555_voltages_setup(dev) < 0) + return -ENODATA; + + debug("%s: FAN53555 option %d rev %d detected\n", + __func__, priv->die_id, priv->die_rev); + + return 0; +} + +static const struct dm_regulator_ops fan53555_regulator_ops = { + .get_value = fan53555_regulator_get_value, + .set_value = fan53555_regulator_set_value, +}; + +static const struct udevice_id fan53555_regulator_ids[] = { + { .compatible = "fcs,fan53555" }, + { }, +}; + +U_BOOT_DRIVER(fan53555_regulator) = { + .name = "fan53555 regulator", + .id = UCLASS_REGULATOR, + .ops = &fan53555_regulator_ops, + .of_match = fan53555_regulator_ids, + .ofdata_to_platdata = fan53555_regulator_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct fan53555_platdata), + .priv_auto_alloc_size = sizeof(struct fan53555_priv), + .probe = fan53555_probe, +}; -- 2.1.4

4 7

[U-Boot] [PATCH v1 0/2] ACPI: Generate SPCR table
by Andy Shevchenko 15 Nov '18

15 Nov '18

This is a WIP series (I have no time to continue with it, so, that's why WIP) to enable SPCR table generation in U-Boot. This table is useful to get early console in Linux for debugging purposes. The benefit of using it is not only for x86, but also for arm64 community (actually they introduced support in Linux kernel). This PoC implementation has been tested on Intel Edison with enabled ACPI support. Known issues: - there is no ->getconfig() callback, thus some data is hard coded - if serial parameters are changed at run time, SPCR is not regenerated, thus, might not produce what user excepts (this is more likely design issue of U-Boot itself) - implementation is not final and might not utilize best practices in U-Boot So, if there is any interest, I would be happy to help, but as I mentioned above I have no capacity to continue this myself. The patches would be also available through my U-Boot tree on GH. Andy Shevchenko (2): WIP: serial: Introduce ->getinfo() callback WIP: x86: acpi: Generate SPCR table arch/x86/include/asm/acpi_table.h | 25 ++++++++++ arch/x86/lib/acpi_table.c | 82 +++++++++++++++++++++++++++++++ drivers/serial/ns16550.c | 14 ++++++ drivers/serial/serial-uclass.c | 21 ++++++++ include/common.h | 3 ++ include/serial.h | 14 ++++++ 6 files changed, 159 insertions(+) -- 2.18.0

4 9