October 2018 - U-Boot

[U-Boot] [PATCH v2] ARM: mvebu: dts: add Clearfog GT-8K
by Baruch Siach 20 Nov '18

20 Nov '18

From: Rabeeh Khoury <rabeeh(a)solid-run.com> The SolidRun Clearfog GT-8K is based on Armada 8040. https://wiki.solid-run.com/doku.php?id=products:a8040:clearfoggt8k The config file is identical to the Macchiatobin one (mvebu_mcbin-88f8040_defconfig) with only the default device-tree changed. Signed-off-by: Rabeeh Khoury <rabeeh(a)solid-run.com> Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- v2: * Change top board compatible string to match the kernel one * Add "spi-flash" compatible string (Chris Packham) * Add defconfig file (Stefan Roese) --- arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 315 ++++++++++++++++++++ configs/clearfog_gt_8k_defconfig | 75 +++++ 3 files changed, 391 insertions(+) create mode 100644 arch/arm/dts/armada-8040-clearfog-gt-8k.dts create mode 100644 configs/clearfog_gt_8k_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 44ebc50bfab1..c9a23ea68450 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -99,6 +99,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-7040-db-nand.dtb \ armada-8040-db.dtb \ armada-8040-mcbin.dtb \ + armada-8040-clearfog-gt-8k.dtb \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts new file mode 100644 index 000000000000..498105f25f05 --- /dev/null +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 SolidRun ltd + */ + +#include "armada-8040.dtsi" + +/ { + model = "ClearFog-GT-8K"; + compatible = "solidrun,clearfog-gt-8k", + "marvell,armada8040"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &cpm_i2c0; + i2c1 = &cpm_i2c1; + spi0 = &cps_spi1; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + simple-bus { + compatible = "simple-bus"; + + reg_usb3h0_vbus: usb3-vbus0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_xhci_vbus_pins>; + regulator-name = "reg-usb3h0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <300000>; + shutdown-delay-us = <500000>; + regulator-force-boot-off; + gpio = <&cpm_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */ + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&ap_pinctl { + /* + * MPP Bus: + * eMMC [0-10] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 3 0 0 0 0 0 0 0 3 >; +}; + +/* on-board eMMC */ +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&cpm_pinctl { + /* + * MPP Bus: + * [0-31] = 0xff: Keep default CP0_shared_pins: + * [11] CLKOUT_MPP_11 (out) + * [23] LINK_RD_IN_CP2CP (in) + * [25] CLKOUT_MPP_25 (out) + * [29] AVS_FB_IN_CP2CP (in) + * [32, 33, 34] pci0/1/2 reset + * [35-38] CP0 I2C1 and I2C0 + * [39] GPIO reset button + * [40,41] LED0 and LED1 + * [43] 1512 phy reset + * [47] USB VBUS EN (active low) + * [48] FAN PWM + * [49] SFP+ present signal + * [50] TPM interrupt + * [51] WLAN0 disable + * [52] WLAN1 disable + * [53] LTE disable + * [54] NFC reset + * [55] Micro SD card detect + * [56-61] Micro SD + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0 0 0 0 2 2 2 2 0 + 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0xe 0xe 0xe 0xe + 0xe 0xe 0 >; + + cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + marvell,pins = < 47 >; + marvell,function = <0>; + }; + + cps_1g_phy_reset: cps-1g-phy-reset { + marvell,pins = < 43 >; + marvell,function = <0>; + }; +}; + +/* uSD slot */ +&cpm_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_sdhci_pins>; + bus-width = <4>; + status = "okay"; +}; + +&cpm_pcie0 { + num-lanes = <1>; + status = "okay"; +}; + +&cpm_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpm_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_i2c1_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpm_sata0 { + status = "okay"; +}; + +&cpm_comphy { + /* + * CP0 Serdes Configuration: + * Lane 0: PCIe0 (x1) + * Lane 1: Not connected + * Lane 2: SFI (10G) + * Lane 3: Not connected + * Lane 4: USB 3.0 host port1 (can be PCIe) + * Lane 5: Not connected + */ + phy0 { + phy-type = <PHY_TYPE_PEX0>; + }; + phy1 { + phy-type = <PHY_TYPE_UNCONNECTED>; + }; + phy2 { + phy-type = <PHY_TYPE_SFI>; + }; + phy3 { + phy-type = <PHY_TYPE_UNCONNECTED>; + }; + phy4 { + phy-type = <PHY_TYPE_USB3_HOST1>; + }; + phy5 { + phy-type = <PHY_TYPE_UNCONNECTED>; + }; +}; + +&cpm_ethernet { + pinctrl-names = "default"; + status = "okay"; +}; + +/* 10G SFI SFP */ +&cpm_eth0 { + status = "okay"; + phy-mode = "sfi"; +}; + +&cps_sata0 { + status = "okay"; +}; + +&cps_usb3_0 { + vbus-supply = <&reg_usb3h0_vbus>; + status = "okay"; +}; + +&cps_utmi0 { + status = "okay"; +}; + +&cps_pinctl { + /* + * MPP Bus: + * [0-5] TDM + * [6] VHV Enable + * [7] CP1 SPI0 CSn1 (FXS) + * [8] CP1 SPI0 CSn0 (TPM) + * [9.11]CP1 SPI0 MOSI/MISO/CLK + * [13] CP1 SPI1 MISO (TDM and SPI ROM shared) + * [14] CP1 SPI1 CS0n (64Mb SPI ROM) + * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared) + * [16] CP1 SPI1 CLK (TDM and SPI ROM shared) + * [24] Topaz switch reset + * [26] Buzzer + * [27] CP1 SMI MDIO + * [28] CP1 SMI MDC + * [29] CP0 10G SFP TX Disable + * [30] WPS button + * [31] Front panel button + * [32-62] = 0xff: Keep default CP1_shared_pins: + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x4 0x4 0x4 + 0x4 0x4 0x0 0x3 0x3 0x3 0x3 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x8 0x8 0x0 + 0x0 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff>; +}; + +&cps_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cps_spi1_pins>; + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor", "spi-flash"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "Filesystem"; + reg = <0x200000 0xce0000>; + }; + }; + }; +}; + +&cps_comphy { + /* + * CP1 Serdes Configuration: + * Lane 0: SATA 1 (RX swapped). Can be PCIe0 + * Lane 1: Not used + * Lane 2: USB HOST 0 + * Lane 3: SGMII1 - Connected to 1512 port + * Lane 4: Not used + * Lane 5: SGMII2 - Connected to Topaz switch + */ + phy0 { + phy-type = <PHY_TYPE_SATA1>; + phy-invert = <PHY_POLARITY_RXD_INVERT>; + }; + phy1 { + phy-type = <PHY_TYPE_UNCONNECTED>; + }; + phy2 { + phy-type = <PHY_TYPE_USB3_HOST0>; + }; + phy3 { + phy-type = <PHY_TYPE_SGMII1>; + phy-speed = <PHY_SPEED_1_25G>; + }; + phy4 { + phy-type = <PHY_TYPE_UNCONNECTED>; + }; + phy5 { + phy-type = <PHY_TYPE_SGMII2>; + phy-speed = <PHY_SPEED_3_125G>; + }; +}; + +&cps_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cps_ethernet { + pinctrl-names = "default"; + pinctrl-0 = <&cps_1g_phy_reset>; + status = "okay"; +}; + +/* 1G SGMII */ +&cps_eth1 { + status = "okay"; + phy-mode = "sgmii"; + phy = <&phy0>; + phy-reset-gpios = <&cpm_gpio1 11 GPIO_ACTIVE_LOW>; +}; + +/* 2.5G to Topaz switch */ +&cps_eth2 { + status = "okay"; + phy-mode = "sgmii"; + phy-speed = <2500>; + phy-reset-gpios = <&cps_gpio0 24 GPIO_ACTIVE_LOW>; +}; diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig new file mode 100644 index 000000000000..6cd1f89b230f --- /dev/null +++ b/configs/clearfog_gt_8k_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_MVEBU_ARMADA_8K=y +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEFAULT_DEVICE_TREE="armada-8040-clearfog-gt-8k" +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MAC_PARTITION=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_AHCI_MVEBU=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_DM_REGULATOR_FIXED=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_SMBIOS_MANUFACTURER="" -- 2.19.1

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[U-Boot] [PATCH] configs: add SolidRun Clearfog GT 8K
by Baruch Siach 20 Nov '18

20 Nov '18

This config is mostly identical to the Macchiatobin one (mvebu_mcbin-88f8040_defconfig) with only the default device-tree changed. Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- This patch depends on the Clearfog GT 8K DT patch. https://patchwork.ozlabs.org/patch/985828/ --- configs/clearfog_gt_8k_defconfig | 75 ++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 configs/clearfog_gt_8k_defconfig diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig new file mode 100644 index 000000000000..6cd1f89b230f --- /dev/null +++ b/configs/clearfog_gt_8k_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_MVEBU_ARMADA_8K=y +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEFAULT_DEVICE_TREE="armada-8040-clearfog-gt-8k" +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MAC_PARTITION=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_AHCI_MVEBU=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_DM_REGULATOR_FIXED=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_SMBIOS_MANUFACTURER="" -- 2.19.1

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[U-Boot] [PATCH u-boot-marvell v2 00/12] Updates for Turris Mox
by Marek Behún 20 Nov '18

20 Nov '18

This is second version of updates for Turris Mox. The first version was sent three months ago, on 16th May. Sorry :). It would be great if this got to 2018.09 release, but I will understand if it does not. I changed the first patch, "phy: marvell: Support changing SERDES map in board file", according to Stefan's suggestions. The other patches have changed, since I have reworked the system of how U-Boot tells kernel about the different Mox modules. Previously the board code created a variable module_topology, which then was used by boot script to load correct device tree. There were many device trees, one for each correct module topology. Now there is only one device tree, and U-Boot patches the device tree in ft_board_setup, according to which modules are connected. Patch 2 adds code to peripheral clocks, so that their parents/rates can be changed. Patch 3 fixes watchdog setup. Patch 4 adds fixup for U-Boot's device tree according to module topology (enables PCIe node if PCIe device is connected). Patches 5 and 10 add configs to defcofnig. Patch 6 is cosmetic. Patch 7 adds comphy_update_map which updates SERDES lane 1 speed according to module topology. Patch 8 adds check for module topology, if it is correct and so on, then adds configuration of switch modules via SPI and finally some fancy switch LED blinking. Patch 9 adds the code which patches Linux's device tree according to module topology. Patch 11 changes the Mox's U-Boot device tree. Patch 12 creates a new config variable to support 1 GB RAM version of Mox (and adds a -u-boot.dtsi to support the change). Marek

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[U-Boot] [PATCH v3 1/3] configs: kirkwood: ds109: switch to DM_I2C
by Chris Packham 20 Nov '18

20 Nov '18

Enable DM_I2C and I2C_MVTSWI for the ds109 board. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- Changes in v3: None Changes in v2: - new configs/ds109_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index c9207433b374..fd10e6e3c36e 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -18,6 +18,8 @@ CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MVSATA_IDE=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 2.18.0

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[U-Boot] [PATCH 00/19] Marvell PXA3XX NAND driver fixes and extensions
by kostap＠marvell.com 20 Nov '18

20 Nov '18

From: Konstantin Porotchkin <kostap(a)marvell.com> This patch series introduces the PXA3XX NAND driver changes and extensions accumulated in Marvell LSP sources. Beside the bug fixes the driver is extended to support 2K page 8-bit ECC flash devices (tested with Toshiba TC58NVG1S3ETA00 chip) and 8K page 4/8 bit ECC devices (tested with Micron MT29F32G08ABAAAWP chip) Boris Brezillon (1): mtd: nand: pxa3xx: Fix READOOB implementation David Sniatkiwicz (1): fix: nand: pxa3xx: Add WA for eliminating flash ready timeout Igal Liberman (1): fix: nand: pxa3xx: Add SoC-specific enable function Konstantin Porotchkin (4): mtd: nand: pxa3xx: add support for Toshiba flash fix: nand: Replace hardcoded page chunk size with calculated one nand: pxa3xx: cosmetic: add comments to the timing layout structures nand: pxa3xx: Add support for 8KB page 4 and 8 bit ECC NAND Ofer Heifetz (10): mtd: nand: pxa3xx_nand: Increase initial buffer size mtd: nand: pxa3xx_nand: use nand_to_mtd() mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing() mtd: nand: pxa3xx_nand: fix early spurious interrupt mtd: nand: pxa3xx-nand: fix random command timeouts nand: pxa3xx: Increase READ_ID buffer and make the size static mtd: pxa3xx_nand: Increase the initial chunk size mtd: pxa3xx_nand: Fix initial controller configuration mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan mtd: nand: pxa3xx_nand: add support for partial chunks Victor Axelrod (1): mtd: nand: pxa3xx: add support for 2KB 8-bit flash zachary zhang (1): a70x0: a80x0: add soc type and revision printing in boot log arch/arm/dts/armada-cp110-master.dtsi | 7 +- arch/arm/mach-mvebu/armada8k/Makefile | 1 + arch/arm/mach-mvebu/armada8k/cpu.c | 21 +- arch/arm/mach-mvebu/armada8k/soc.c | 160 ++++++++++ arch/arm/mach-mvebu/cpu.c | 12 +- arch/arm/mach-mvebu/include/mach/cpu.h | 3 +- arch/arm/mach-mvebu/include/mach/soc.h | 3 + common/board_f.c | 6 +- drivers/mtd/nand/pxa3xx_nand.c | 521 +++++++++++++++++++++++---------- 9 files changed, 564 insertions(+), 170 deletions(-) create mode 100644 arch/arm/mach-mvebu/armada8k/soc.c -- 2.7.4

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[U-Boot] [PATCH][v2] armv8: lx2160ardb : Add support for LX2160ARDB platform
by Priyanka Jain 20 Nov '18

20 Nov '18

LX2160ARDB is an evaluation board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan(a)nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur(a)nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma(a)nxp.com> Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> Signed-off-by: Pankit Garg <pankit.garg(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v2: Rebased on top of test_qoriq branch of u-boot-fsl-qoriq.git Corrected line seria01.clock = get_serial_clock -> serial1.clock = get_serial_clock(); Corrected CONFIG_ENV_OFFSET to 0x500000 [Thanks to Ashish K for pointing this] Depends on below patches[sequence in increasing order] 1)https://patchwork.ozlabs.org/patch/982258/ 2)https://patchwork.ozlabs.org/patch/975541/ 3)https://patchwork.ozlabs.org/patch/962408/ 4)https://patchwork.ozlabs.org/patch/982259/ 5)https://patchwork.ozlabs.org/patch/982237/ 6)https://patchwork.ozlabs.org/patch/990088/ 7)https://patchwork.ozlabs.org/patch/990093/ arch/arm/Kconfig | 14 ++ arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/fsl-lx2160a-rdb.dts | 20 +++ board/freescale/common/qixis.c | 4 + board/freescale/lx2160a/Kconfig | 16 ++ board/freescale/lx2160a/MAINTAINERS | 8 + board/freescale/lx2160a/Makefile | 9 + board/freescale/lx2160a/README | 79 +++++++++ board/freescale/lx2160a/ddr.c | 20 +++ board/freescale/lx2160a/eth_lx2160ardb.c | 210 +++++++++++++++++++++++ board/freescale/lx2160a/lx2160a.c | 279 +++++++++++++++++++++++++++++++ configs/lx2160ardb_tfa_defconfig | 74 ++++++++ include/configs/lx2160a_common.h | 214 ++++++++++++++++++++++++ include/configs/lx2160ardb.h | 102 +++++++++++ 15 files changed, 1052 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2160a-rdb.dts create mode 100644 board/freescale/lx2160a/Kconfig create mode 100644 board/freescale/lx2160a/MAINTAINERS create mode 100644 board/freescale/lx2160a/Makefile create mode 100644 board/freescale/lx2160a/README create mode 100644 board/freescale/lx2160a/ddr.c create mode 100644 board/freescale/lx2160a/eth_lx2160ardb.c create mode 100644 board/freescale/lx2160a/lx2160a.c create mode 100644 configs/lx2160ardb_tfa_defconfig create mode 100644 include/configs/lx2160a_common.h create mode 100644 include/configs/lx2160ardb.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ccf2a84..28a81e7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1027,6 +1027,19 @@ config TARGET_LS2081ARDB development platform that supports the QorIQ LS2081A/LS2041A Layerscape Architecture processor. +config TARGET_LX2160ARDB + bool "Support lx2160ardb" + select ARCH_LX2160A + select ARCH_MISC_INIT + select ARM64 + select ARMV8_MULTIENTRY + select BOARD_LATE_INIT + help + Support for NXP LX2160ARDB platform. + The lx2160ardb (LX2160A Reference design board (RDB) + is a high-performance development platform that supports the + QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. + config TARGET_HIKEY bool "Support HiKey 96boards Consumer Edition Platform" select ARM64 @@ -1488,6 +1501,7 @@ source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" +source "board/freescale/lx2160a/Kconfig" source "board/freescale/mx35pdk/Kconfig" source "board/freescale/s32v234evb/Kconfig" source "board/grinn/chiliboard/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index c8bebab..aac3aeb 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -105,7 +105,7 @@ config PSCI_RESET !TARGET_LS1012AFRWY && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ - !TARGET_LS2081ARDB && \ + !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB help Most armv8 systems have PSCI support enabled in EL3, either through diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 44ebc50..25cd773 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -226,7 +226,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2081a-rdb.dtb \ fsl-ls2088a-rdb-qspi.dtb \ fsl-ls1088a-rdb.dtb \ - fsl-ls1088a-qds.dtb + fsl-ls1088a-qds.dtb \ + fsl-lx2160a-rdb.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts new file mode 100644 index 0000000..08201b5 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160ARDB device tree source + * + * Author: Priyanka Jain <priyanka.jain(a)nxp.com> + * Sriram Dash <sriram.dash(a)nxp.com> + * + * Copyright 2018 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2160ARDB Board"; + compatible = "fsl,lx2160ardb", "fsl,lx2160a"; + +}; diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index af3dc59..f1b98bc 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -227,8 +227,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar #ifdef QIXIS_LBMAP_SD QIXIS_WRITE(rst_ctl, 0x30); QIXIS_WRITE(rcfg_ctl, 0); +#ifdef NON_EXTENDED_DUTCFG + QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD); +#else set_lbmap(QIXIS_LBMAP_SD); set_rcw_src(QIXIS_RCW_SRC_SD); +#endif QIXIS_WRITE(rcfg_ctl, 0x20); QIXIS_WRITE(rcfg_ctl, 0x21); #else diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig new file mode 100644 index 0000000..5562c3e --- /dev/null +++ b/board/freescale/lx2160a/Kconfig @@ -0,0 +1,16 @@ +if TARGET_LX2160ARDB + +config SYS_BOARD + default "lx2160a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "lx2160ardb" + +source "board/freescale/common/Kconfig" +endif diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS new file mode 100644 index 0000000..b4dd842 --- /dev/null +++ b/board/freescale/lx2160a/MAINTAINERS @@ -0,0 +1,8 @@ +LX2160ARDB BOARD +M: Priyanka Jain <priyanka.jain(a)nxp.com> +S: Maintained +F: board/freescale/lx2160a/ +F: include/configs/lx2160a_common.h +F: include/configs/lx2160ardb.h +F: configs/lx2160ardb_defconfig +F: arch/arm/dts/fsl-lx2160a-rdb.dts diff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile new file mode 100644 index 0000000..be3709d --- /dev/null +++ b/board/freescale/lx2160a/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2018 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lx2160a.o +obj-y += ddr.o +obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o diff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README new file mode 100644 index 0000000..618c40b --- /dev/null +++ b/board/freescale/lx2160a/README @@ -0,0 +1,79 @@ +Overview +-------- +The LX2160A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LX2160A +Layerscape Architecture processor and its personalities. + +LX2160A SoC Overview +-------------------------------------- +For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +LX2160ARDB board Overview +---------------------- +DDR Memory + Two ports of 72-bits (8-bits ECC) DDR4. + Each port supports four chip-selects and two DIMM + connectors. Data rate upto 3.2 GT/s. + +SERDES ports + Thress serdes controllers (24 lanes) + Serdes1: Supports two USXGMII connectors, each connected through + Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi + IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi + CS4223 phy. + + Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0 + connectors + + Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector + +eSDHC + eSDHC1: Supports a SD connector for connecting SD cards + eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC + +Octal SPI (XSPI) + Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator + for off-board emulation + +I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer + Serial Ports + +USB 3.0 + Two high speed USB 3.0 ports. First USB 3.0 port configured as + Host with Type-A connector, second USB 3.0 port configured as OTG + with micro-AB connector + +Serial Ports Two UART ports +Ethernet Two RGMII interfaces +Debug ARM JTAG support + +Booting Options +--------------- +a) Flexspi boot +b) SD boot + +Memory map for Flexspi flash +---------------------------- +Image Flash Offset +bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00100000 +Boot firmware Environment 0x00500000 +DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 +DPAA2 MC Firmware 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +Memory map for sd card +---------------------------- +Image SD card Offset +bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00800 +Boot firmware Environment 0x02800 +DDR PHY Firmware (fip_ddr_all.bin) 0x04000 +DPAA2 MC Firmware 0x05000 +DPAA2 DPL 0x06800 +DPAA2 DPC 0x07000 +Kernel.itb 0x08000 diff --git a/board/freescale/lx2160a/ddr.c b/board/freescale/lx2160a/ddr.c new file mode 100644 index 0000000..cd422bf --- /dev/null +++ b/board/freescale/lx2160a/ddr.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c new file mode 100644 index 0000000..ab75582 --- /dev/null +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <malloc.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <exports.h> +#include <asm/arch/fsl_serdes.h> +#include <fsl-mc/fsl_mc.h> +#include <fsl-mc/ldpaa_wriop.h> + +DECLARE_GLOBAL_DATA_PTR; + +static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad) +{ + int phy_reg; + u32 phy_id; + + phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); + phy_id = (phy_reg & 0xffff) << 16; + + phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); + phy_id |= (phy_reg & 0xffff); + + if (phy_id == PHY_UID_IN112525_S03) + return true; + else + return false; +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FSL_MC_ENET) + struct memac_mdio_info mdio_info; + struct memac_mdio_controller *reg; + int i, interface; + struct mii_dev *dev; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; + + /* Register the EMI 1 */ + fm_memac_mdio_init(bis, &mdio_info); + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; + + /* Register the EMI 2 */ + fm_memac_mdio_init(bis, &mdio_info); + + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + switch (srds_s1) { + case 19: + wriop_set_phy_address(WRIOP1_DPMAC2, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC3, + AQR107_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC4, + AQR107_PHY_ADDR2); + if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { + wriop_set_phy_address(WRIOP1_DPMAC5, + INPHI_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, + INPHI_PHY_ADDR1); + } + wriop_set_phy_address(WRIOP1_DPMAC17, + RGMII_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC18, + RGMII_PHY_ADDR2); + break; + + case 18: + wriop_set_phy_address(WRIOP1_DPMAC7, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC8, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC9, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC10, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC3, + AQR107_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC4, + AQR107_PHY_ADDR2); + if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { + wriop_set_phy_address(WRIOP1_DPMAC5, + INPHI_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, + INPHI_PHY_ADDR1); + } + wriop_set_phy_address(WRIOP1_DPMAC17, + RGMII_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC18, + RGMII_PHY_ADDR2); + break; + + default: + printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n", + srds_s1); + goto next; + } + + for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) { + interface = wriop_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + case PHY_INTERFACE_MODE_25G_AUI: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + wriop_set_mdio(i, dev); + break; + case PHY_INTERFACE_MODE_XLAUI: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) { + interface = wriop_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + +next: + cpu_eth_init(bis); +#endif /* CONFIG_FSL_MC_ENET */ + +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + return pci_eth_init(bis); +} + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +#if defined(CONFIG_FSL_MC_ENET) + mc_env_boot(); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ + +int fdt_fixup_board_phy(void *fdt) +{ + int mdio_offset; + int ret; + struct mii_dev *dev; + + ret = 0; + + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { + mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000"); + + if (mdio_offset < 0) + mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000"); + + if (mdio_offset < 0) { + printf("mdio@0x8B9700 node not found in dts\n"); + return mdio_offset; + } + + ret = fdt_setprop_string(fdt, mdio_offset, "status", + "disabled"); + if (ret) { + printf("Could not set disable mdio@0x8B97000 %s\n", + fdt_strerror(ret)); + return ret; + } + } + + return ret; +} diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c new file mode 100644 index 0000000..a62222e --- /dev/null +++ b/board/freescale/lx2160a/lx2160a.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <dm.h> +#include <dm/platform_data/serial_pl01x.h> +#include <i2c.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <fsl_ddr.h> +#include <fsl_sec.h> +#include <asm/io.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <fsl-mc/fsl_mc.h> +#include <environment.h> +#include <efi_loader.h> +#include <asm/arch/mmu.h> +#include <hwconfig.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include "../common/qixis.h" +#include "../common/vid.h" +#include <fsl_immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct pl01x_serial_platdata serial0 = { +#if CONFIG_CONS_INDEX == 0 + .base = CONFIG_SYS_SERIAL0, +#elif CONFIG_CONS_INDEX == 1 + .base = CONFIG_SYS_SERIAL1, +#else +#error "Unsupported console index value." +#endif + .type = TYPE_PL011, +}; + +U_BOOT_DEVICE(nxp_serial0) = { + .name = "serial_pl01x", + .platdata = &serial0, +}; + +static struct pl01x_serial_platdata serial1 = { + .base = CONFIG_SYS_SERIAL1, + .type = TYPE_PL011, +}; + +U_BOOT_DEVICE(nxp_serial1) = { + .name = "serial_pl01x", + .platdata = &serial1, +}; + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +static void uart_get_clock(void) +{ + serial0.clock = get_serial_clock(); + serial1.clock = get_serial_clock(); +} + +int board_early_init_f(void) +{ +#ifdef CONFIG_SYS_I2C_EARLY_INIT + i2c_early_init_f(); +#endif + /* get required clock for UART IP */ + uart_get_clock(); + + fsl_lsch3_early_init_f(); + return 0; +} + +int esdhc_status_fixup(void *blob, const char *compat) +{ + /* Enable both esdhc DT nodes for LX2160ARDB */ + do_fixup_by_compat(blob, compat, "status", "okay", + sizeof("okay"), 1); + + return 0; +} + +#if defined(CONFIG_VID) +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + +#endif + +int checkboard(void) +{ + enum boot_src src = get_boot_src(); + char buf[64]; + u8 sw; + + cpu_name(buf); + printf("Board: %s-RDB, ", buf); + + sw = QIXIS_READ(arch); + printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A'); + + if (src == BOOT_SOURCE_SD_MMC) { + puts("SD\n"); + } else { + sw = QIXIS_READ(brdcfg[0]); + sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; + switch (sw) { + case 0: + case 4: + puts("FlexSPI DEV#0\n"); + break; + case 1: + puts("FlexSPI DEV#1\n"); + break; + case 2: + case 3: + puts("FlexSPI EMU\n"); + break; + default: + printf("invalid setting, xmap: %d\n", sw); + break; + } + } + printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); + + puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); + puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); + puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n"); + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + return 100000000; +} + +unsigned long get_board_ddr_clk(void) +{ + return 100000000; +} + +int board_init(void) +{ +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + int i; + u64 ddr_size = 0; + + puts("\nDDR "); + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + ddr_size += gd->bd->bi_dram[i].size; + print_size(ddr_size, ""); + print_ddr_info(0); +} + +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_FSL_MC_ENET +extern int fdt_fixup_board_phy(void *fdt); + +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl-mc"); + + if (offset < 0) { + printf("%s: fsl-mc node not found in device tree (error %d)\n", + __func__, offset); + return; + } + + if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) { + fdt_status_okay(fdt, offset); + fdt_fixup_board_phy(fdt); + } else { + fdt_status_fail(fdt, offset); + } +} + +void board_quiesce_devices(void) +{ + fsl_mc_ldpaa_exit(gd->bd); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP + +int ft_board_setup(void *blob, bd_t *bd) +{ + int i; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + ft_cpu_setup(blob, bd); + + /* fixup DT for the three GPP DDR banks */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + base[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; + else if (gd->arch.resv_ram >= base[2] && + gd->arch.resv_ram < base[2] + size[2]) + size[2] = gd->arch.resv_ram - base[2]; +#endif + + fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); + +#ifdef CONFIG_USB + fsl_fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_FSL_MC_ENET + fdt_fsl_mc_fixup_iommu_map_entry(blob); + fdt_fixup_board_enet(blob); +#endif + + return 0; +} +#endif + +void qixis_dump_switch(void) +{ + int i, nr_of_cfgsw; + + QIXIS_WRITE(cms[0], 0x00); + nr_of_cfgsw = QIXIS_READ(cms[1]); + + puts("DIP switch settings dump:\n"); + for (i = 1; i <= nr_of_cfgsw; i++) { + QIXIS_WRITE(cms[0], i); + printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); + } +} diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig new file mode 100644 index 0000000..fb1102e --- /dev/null +++ b/configs/lx2160ardb_tfa_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2160ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" +CONFIG_NR_DRAM_BANKS=3 +CONFIG_DM=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_SERIAL=y +CONFIG_CONS_INDEX=0 +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_USE_4K_SECTORS=n +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_NXP_FSPI=y +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_SYS_FSPI_AHB_INIT=y +CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_PHY_GIGE=y +CONFIG_CMD_NET=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_NET=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +# CONFIG_SYS_FSL_DDR_PHY is not set +CONFIG_SYS_GEN2_DDR_PHY=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_PHYLIB_10G=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_INPHI=y +CONFIG_INPHI_25G=y +CONFIG_HUSH_PARSER=y +CONFIG_EMC2305=y diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h new file mode 100644 index 0000000..5c08c87 --- /dev/null +++ b/include/configs/lx2160a_common.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __LX2_COMMON_H +#define __LX2_COMMON_H + +#include <asm/arch/stream_id_lsch3.h> +#include <asm/arch/config.h> +#include <asm/arch/soc.h> + +#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 +#define CONFIG_FSL_MEMAC + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_BASE 0x20000000 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 + +/* DDR */ +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 +#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +#define CONFIG_SYS_MONITOR_LEN (936 * 1024) + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Generic Timer Definitions */ +/* + * This is not an accurate number. It is used in start.S. The frequency + * will be udpated later when get_bus_freq(0) is available. + */ + +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* Serial Port */ +#define CONFIG_PL01X_SERIAL +#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) +#define CONFIG_SYS_SERIAL0 0x21c0000 +#define CONFIG_SYS_SERIAL1 0x21d0000 +#define CONFIG_SYS_SERIAL2 0x21e0000 +#define CONFIG_SYS_SERIAL3 0x21f0000 +/*below might needs to be removed*/ +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2, \ + (void *)CONFIG_SYS_SERIAL3 } +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* MC firmware */ +#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +/* Define phy_reset function to boot the MC based on mcinitcmd. + * This happens late enough to properly fixup u-boot env MAC addresses. + */ +#define CONFIG_RESET_PHY_R + +/* + * Carve out a DDR region which will not be used by u-boot/Linux + * + * It will be used by MC and Debug Server. The MC region must be + * 512MB aligned, so the min size to hide is 512MB. + */ +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#endif + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* RTC */ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Qixis */ +#define CONFIG_FSL_QIXIS +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 + +/* PCI */ +#ifdef CONFIG_PCI +#define CONFIG_SYS_PCI_64BIT +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + +/* SATA */ + +#ifdef CONFIG_SCSI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* USB */ +#ifdef CONFIG_USB +#define CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +/* FlexSPI */ +#ifdef CONFIG_NXP_FSPI +#define NXP_FSPI_FLASH_SIZE SZ_64M +#define NXP_FSPI_FLASH_NUM 1 +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x500000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ + CONFIG_ENV_OFFSET) + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* Initial environment variables */ +#define XSPI_NOR_BOOTCOMMAND "fsl_mc apply dpl 0x20d00000;" \ + "sf probe 0:0;" \ + "sf read 0xa0000000 0x1000000 0x3000000;" \ + "bootm 0xa0000000" + +#define SD_BOOTCOMMAND "mmc read 0xa0000000 0x6800 0xA0;" \ + "fsl_mc apply dpl 0xa0000000;" \ + "mmc read 0xb0000000 0x8000 0x1d000;" \ + "bootm 0xb0000000" + +#define XSPI_MC_INIT_CMD \ + "fsl_mc start mc 0x20a00000 0x20e00000\0" + +#define SD_MC_INIT_CMD \ + "mmc read 0x80000000 0x5000 0x800;" \ + "mmc read 0x80100000 0x7000 0x800;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" + +#endif /* __LX2_COMMON_H */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h new file mode 100644 index 0000000..67d214d --- /dev/null +++ b/include/configs/lx2160ardb.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __LX2_RDB_H +#define __LX2_RDB_H + +#include "lx2160a_common.h" + +/* Qixis */ +#define QIXIS_XMAP_MASK 0x07 +#define QIXIS_XMAP_SHIFT 5 +#define QIXIS_RST_CTL_RESET_EN 0x30 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x20 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SD +#define QIXIS_RCW_SRC_SD 0x08 +#define NON_EXTENDED_DUTCFG + +/* VID */ + +#define I2C_MUX_CH_VOL_MONITOR 0xA +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv" +#define CONFIG_VID + +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 855 + +/* PM Bus commands code for LTC3882*/ +#define PMBUS_CMD_PAGE 0x0 +#define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 +#define PMBUS_CMD_VOUT_COMMAND 0x21 +#define PWM_CHANNEL0 0x0 + +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 4 + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "DPMAC1@xgmii" + +#define AQR107_PHY_ADDR1 0x04 +#define AQR107_PHY_ADDR2 0x05 + +#define CORTINA_NO_FW_UPLOAD +#define CORTINA_PHY_ADDR1 0x0 +#define INPHI_PHY_ADDR1 0x0 + +#define RGMII_PHY_ADDR1 0x01 +#define RGMII_PHY_ADDR2 0x02 + +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x21000000\0" \ + "lx2160ardb_vdd_mv=800\0" \ + "mcmemsize=0x40000000\0" + +#include <asm/fsl_secure_boot.h> + +#endif /* __LX2_RDB_H */ -- 2.7.4

3 3

[U-Boot] [PATCH v3 6/6] spi: kirkwood: Full dm conversion
by Jagan Teki 20 Nov '18

20 Nov '18

kirkwood now support dt along with platform data, respective boards need to switch into dm for the same. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v3: - rebased master - Move kconfig option if DM_SPI drivers/spi/Kconfig | 12 +- drivers/spi/kirkwood_spi.c | 240 ++++++-------------------------- include/dm/platform_data/spi_kirkwood.h | 15 ++ 3 files changed, 62 insertions(+), 205 deletions(-) create mode 100644 include/dm/platform_data/spi_kirkwood.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 73dd33f716..64567cf6e9 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -105,6 +105,12 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config KIRKWOOD_SPI + bool "Marvell Kirkwood SPI Driver" + help + Enable support for SPI on various Marvell SoCs, such as + Kirkwood and Armada 375. + config MPC8XXX_SPI bool "MPC8XXX SPI Driver" help @@ -283,12 +289,6 @@ config SH_QSPI Enable the Renesas Quad SPI controller driver. This driver can be used on Renesas SoCs. -config KIRKWOOD_SPI - bool "Marvell Kirkwood SPI Driver" - help - Enable support for SPI on various Marvell SoCs, such as - Kirkwood and Armada 375. - config LPC32XX_SSP bool "LPC32XX SPI Driver" help diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 4850a2b955..3b65b9221b 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -14,31 +14,41 @@ #include <spi.h> #include <asm/io.h> #include <asm/arch/soc.h> -#ifdef CONFIG_KIRKWOOD -#include <asm/arch/mpp.h> -#endif #include <asm/arch-mvebu/spi.h> -static void _spi_cs_activate(struct kwspi_registers *reg) +#include <dm/platform_data/spi_kirkwood.h> + +struct mvebu_spi_dev { + bool is_errata_50mhz_ac; +}; + +struct mvebu_spi_priv { + struct kwspi_registers *spireg; +}; + +static void spi_cs_activate(struct kwspi_registers *reg) { setbits_le32(&reg->ctrl, KWSPI_CSN_ACT); } -static void _spi_cs_deactivate(struct kwspi_registers *reg) +static void spi_cs_deactivate(struct kwspi_registers *reg) { clrbits_le32(&reg->ctrl, KWSPI_CSN_ACT); } -static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { + struct udevice *bus = dev->parent; + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + struct kwspi_registers *reg = plat->spireg; unsigned int tmpdout, tmpdin; int tm, isread = 0; - debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen); + debug("%s: dout %p din %p bitlen %u\n", __func__, dout, din, bitlen); if (flags & SPI_XFER_BEGIN) - _spi_cs_activate(reg); + spi_cs_activate(reg); /* * handle data in 8-bit chunks @@ -56,8 +66,8 @@ static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ); writel(tmpdout, &reg->dout); /* Write the data out */ - debug("*** spi_xfer: ... %08x written, bitlen %d\n", - tmpdout, bitlen); + debug("%s: ... %08x written, bitlen %d\n", + __func__, tmpdout, bitlen); /* * Wait for SPI transmit to get out @@ -68,8 +78,8 @@ static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) { isread = 1; tmpdin = readl(&reg->din); - debug("spi_xfer: din %p..%08x read\n", - din, tmpdin); + debug("%s: din %p..%08x read\n", + __func__, din, tmpdin); if (din) { *((u8 *)din) = (u8)tmpdin; @@ -83,179 +93,17 @@ static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, break; } if (tm >= KWSPI_TIMEOUT) - printf("*** spi_xfer: Time out during SPI transfer\n"); + printf("%s: Time out during SPI transfer\n", __func__); debug("loopend bitlen %d\n", bitlen); } if (flags & SPI_XFER_END) - _spi_cs_deactivate(reg); + spi_cs_deactivate(reg); return 0; } -#ifndef CONFIG_DM_SPI - -static struct kwspi_registers *spireg = - (struct kwspi_registers *)MVEBU_SPI_BASE; - -#ifdef CONFIG_KIRKWOOD -static u32 cs_spi_mpp_back[2]; -#endif - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct spi_slave *slave; - u32 data; -#ifdef CONFIG_KIRKWOOD - static const u32 kwspi_mpp_config[2][2] = { - { MPP0_SPI_SCn, 0 }, /* if cs == 0 */ - { MPP7_SPI_SCn, 0 } /* if cs != 0 */ - }; -#endif - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - slave = spi_alloc_slave_base(bus, cs); - if (!slave) - return NULL; - - writel(KWSPI_SMEMRDY, &spireg->ctrl); - - /* calculate spi clock prescaller using max_hz */ - data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10; - data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data; - data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data; - - /* program spi clock prescaller using max_hz */ - writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg); - debug("data = 0x%08x\n", data); - - writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause); - writel(KWSPI_IRQMASK, &spireg->irq_mask); - -#ifdef CONFIG_KIRKWOOD - /* program mpp registers to select SPI_CSn */ - kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back); -#endif - - return slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ -#ifdef CONFIG_KIRKWOOD - kirkwood_mpp_conf(cs_spi_mpp_back, NULL); -#endif - free(slave); -} - -#if defined(CONFIG_SYS_KW_SPI_MPP) -u32 spi_mpp_backup[4]; -#endif - -__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave) -{ - return 0; -} - -int spi_claim_bus(struct spi_slave *slave) -{ -#if defined(CONFIG_SYS_KW_SPI_MPP) - u32 config; - u32 spi_mpp_config[4]; - - config = CONFIG_SYS_KW_SPI_MPP; - - if (config & MOSI_MPP6) - spi_mpp_config[0] = MPP6_SPI_MOSI; - else - spi_mpp_config[0] = MPP1_SPI_MOSI; - - if (config & SCK_MPP10) - spi_mpp_config[1] = MPP10_SPI_SCK; - else - spi_mpp_config[1] = MPP2_SPI_SCK; - - if (config & MISO_MPP11) - spi_mpp_config[2] = MPP11_SPI_MISO; - else - spi_mpp_config[2] = MPP3_SPI_MISO; - - spi_mpp_config[3] = 0; - spi_mpp_backup[3] = 0; - - /* set new spi mpp and save current mpp config */ - kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup); -#endif - - return board_spi_claim_bus(slave); -} - -__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave) -{ -} - -void spi_release_bus(struct spi_slave *slave) -{ -#if defined(CONFIG_SYS_KW_SPI_MPP) - kirkwood_mpp_conf(spi_mpp_backup, NULL); -#endif - - board_spi_release_bus(slave); -} - -#ifndef CONFIG_SPI_CS_IS_VALID -/* - * you can define this function board specific - * define above CONFIG in board specific config file and - * provide the function in board specific src file - */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && (cs == 0 || cs == 1); -} -#endif - -void spi_init(void) -{ -} - -void spi_cs_activate(struct spi_slave *slave) -{ - _spi_cs_activate(spireg); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - _spi_cs_deactivate(spireg); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - return _spi_xfer(spireg, bitlen, dout, din, flags); -} - -#else - -/* Here now the DM part */ - -struct mvebu_spi_dev { - bool is_errata_50mhz_ac; -}; - -struct mvebu_spi_platdata { - struct kwspi_registers *spireg; - bool is_errata_50mhz_ac; -}; - -struct mvebu_spi_priv { - struct kwspi_registers *spireg; -}; - static int mvebu_spi_set_speed(struct udevice *bus, uint hz) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); @@ -330,15 +178,6 @@ static int mvebu_spi_set_mode(struct udevice *bus, uint mode) return 0; } -static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct udevice *bus = dev->parent; - struct mvebu_spi_platdata *plat = dev_get_platdata(bus); - - return _spi_xfer(plat->spireg, bitlen, dout, din, flags); -} - static int mvebu_spi_claim_bus(struct udevice *dev) { struct udevice *bus = dev->parent; @@ -352,6 +191,17 @@ static int mvebu_spi_claim_bus(struct udevice *dev) return 0; } +static const struct dm_spi_ops mvebu_spi_ops = { + .claim_bus = mvebu_spi_claim_bus, + .xfer = mvebu_spi_xfer, + .set_speed = mvebu_spi_set_speed, + .set_mode = mvebu_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + static int mvebu_spi_probe(struct udevice *bus) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); @@ -364,6 +214,7 @@ static int mvebu_spi_probe(struct udevice *bus) return 0; } +#if CONFIG_IS_ENABLED(OF_CONTROL) static int mvebu_spi_ofdata_to_platdata(struct udevice *bus) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); @@ -376,17 +227,6 @@ static int mvebu_spi_ofdata_to_platdata(struct udevice *bus) return 0; } -static const struct dm_spi_ops mvebu_spi_ops = { - .claim_bus = mvebu_spi_claim_bus, - .xfer = mvebu_spi_xfer, - .set_speed = mvebu_spi_set_speed, - .set_mode = mvebu_spi_set_mode, - /* - * cs_info is not needed, since we require all chip selects to be - * in the device tree explicitly - */ -}; - static const struct mvebu_spi_dev armada_xp_spi_dev_data = { .is_errata_50mhz_ac = false, }; @@ -414,15 +254,17 @@ static const struct udevice_id mvebu_spi_ids[] = { }, { } }; +#endif U_BOOT_DRIVER(mvebu_spi) = { .name = "mvebu_spi", .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) .of_match = mvebu_spi_ids, - .ops = &mvebu_spi_ops, .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata), +#endif + .ops = &mvebu_spi_ops, .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv), .probe = mvebu_spi_probe, }; -#endif diff --git a/include/dm/platform_data/spi_kirkwood.h b/include/dm/platform_data/spi_kirkwood.h new file mode 100644 index 0000000000..ae9b2783a9 --- /dev/null +++ b/include/dm/platform_data/spi_kirkwood.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2018 Jagan Teki <jagan(a)amarulasolutions.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __spi_kirkwood_h +#define __spi_kirkwood_h + +struct mvebu_spi_platdata { + struct kwspi_registers *spireg; + bool is_errata_50mhz_ac; +}; + +#endif /* __spi_kirkwood_h */ -- 2.14.3

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[U-Boot] [PULL] Please pull u-boot-imx
by Stefano Babic 19 Nov '18

19 Nov '18

Hi Tom, a new PR. I dropped the patches causing breakages on PowerPC boards, as well as the issue on GE boards. It ran on travis successfully. The following changes since commit 11ed312896c5f5814064c5d45dcb2f53dc121437: configs: am57xx: change default board name to beagle_x15 (2018-08-26 12:26:16 -0400) are available in the Git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to c1d1543ebc6e1fb026d0d7ac96d865faa7567555: mx7dsabresd: Add the qspi target to the list of supported defconfigs (2018-09-04 08:47:23 +0200) ---------------------------------------------------------------- Alex Kiernan (1): Cleanup CONFIG_BOOTDELAY on cl-som-imx7 Anson Huang (3): imx: mx7: psci: improve cpu hotplug flow imx: mx7: add gpc initialization for low power mode imx: mx7: add system suspend/resume support Fabio Estevam (1): mx7dsabresd: Add the qspi target to the list of supported defconfigs Martin Kaiser (1): watchdog: mx25: use the imx_watchdog driver for mx25 Stefan Agner (2): board: toradex: common: fail gracefully on missing NAND chip colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module support Stefano Babic (1): imx: missing CONFIG_MII in mx7dsabresd_qspi_defconfig Ye Li (6): imx: imx6sx-sdb: Enable DM QSPI driver imx: imx6sx-sabreauto: convert to use DM QSPI driver imx: imx7d-sdb: Add DM QSPI support dts: imx6ul: Update alias to support DM dts: imx6ul_evk: Add DTS files for 14x14 EVK and 9x9 EVK boards imx: imx6ul_evk: Enable DM driver for iMX6UL EVK u-boot arch/arm/dts/Makefile | 7 ++- arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi | 16 +++++ arch/arm/dts/imx6sx-sabreauto.dts | 40 +++++++++++++ arch/arm/dts/imx6sx-sdb-u-boot.dtsi | 16 +++++ arch/arm/dts/imx6sx.dtsi | 12 ++-- arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi | 10 ++++ arch/arm/dts/imx6ul-14x14-evk.dts | 427 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi | 10 ++++ arch/arm/dts/imx6ul-9x9-evk.dts | 471 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6ul.dtsi | 13 ++-- arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi | 10 ++++ arch/arm/dts/imx7d-sdb-qspi.dts | 44 ++++++++++++++ arch/arm/dts/imx7d-sdb.dts | 6 +- arch/arm/dts/imx7d.dtsi | 12 ++++ arch/arm/dts/imx7s.dtsi | 22 +++++-- arch/arm/include/asm/arch-mx25/imx-regs.h | 1 + arch/arm/mach-imx/mx7/Makefile | 2 +- arch/arm/mach-imx/mx7/psci-mx7.c | 472 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- arch/arm/mach-imx/mx7/psci-suspend.S | 67 +++++++++++++++++++++ arch/arm/mach-imx/mx7/soc.c | 103 ++++++++++++++++++++++++++++++++ board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 24 -------- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 25 -------- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 208 +++++++++++++--------------------------------------------------- board/freescale/mx7dsabresd/MAINTAINERS | 1 + board/freescale/mx7dsabresd/mx7dsabresd.c | 16 ----- board/toradex/colibri_imx7/Kconfig | 42 ++++++++++++- board/toradex/colibri_imx7/MAINTAINERS | 4 ++ board/toradex/colibri_imx7/colibri_imx7.c | 41 +++++++++++-- board/toradex/common/tdx-cfg-block.c | 7 ++- configs/mx6sxsabreauto_defconfig | 2 + configs/mx6sxsabresd_defconfig | 7 +++ configs/mx6ul_14x14_evk_defconfig | 17 +++++- configs/mx6ul_9x9_evk_defconfig | 20 ++++++- configs/mx7dsabresd_qspi_defconfig | 84 ++++++++++++++++++++++++++ drivers/watchdog/Makefile | 2 +- include/configs/cl-som-imx7.h | 2 - include/configs/colibri_imx7.h | 90 ++++++++++++++++++++++------ include/configs/mx6sxsabresd.h | 4 ++ include/configs/mx6ul_14x14_evk.h | 13 ++-- include/configs/mx7dsabresd.h | 4 +- 40 files changed, 2079 insertions(+), 295 deletions(-) create mode 100644 arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi create mode 100644 arch/arm/dts/imx6sx-sdb-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-14x14-evk.dts create mode 100644 arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-9x9-evk.dts create mode 100644 arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi create mode 100644 arch/arm/dts/imx7d-sdb-qspi.dts create mode 100644 arch/arm/mach-imx/mx7/psci-suspend.S create mode 100644 configs/mx7dsabresd_qspi_defconfig -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[U-Boot] [PATCH] x86: make X86IRQ per Kconfig switchable
by Hannes Schmelzer 19 Nov '18

19 Nov '18

This commit creates the freedom for boards to do nothing with the whole IRQ stuff on x86 during u-boot. This is especially important on older systems which have many legacy irq and no ACPI support within BIOS, they get in trouble if, for example, u-boot does mask all the interrupts on a PIC. Signed-off-by: Hannes Schmelzer <oe5hpm(a)oevsv.at> --- arch/x86/Kconfig | 8 ++++++++ arch/x86/lib/Makefile | 2 +- include/_exports.h | 2 +- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 00b69c6..d2b691f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -736,6 +736,14 @@ config I8259_PIC slave) interrupt controllers. Include this to have U-Boot set up the interrupt correctly. +config X86IRQ + bool + default y + help + Provide basic IRQ initialization with dummy handlers and spurious IRQ + catching. Provide also some exported high-level API for standalone + applications (see doc/README.standalone). + config APIC bool default y diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 1e8efcc..57cb87d 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_SEABIOS) += coreboot_table.o obj-y += early_cmos.o obj-y += e820.o obj-y += init_helpers.o -obj-y += interrupts.o +obj-$(CONFIG_X86IRQ) += interrupts.o obj-y += lpc-uclass.o obj-y += mpspec.o obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o diff --git a/include/_exports.h b/include/_exports.h index 5416041..39e3e32 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -13,7 +13,7 @@ EXPORT_FUNC(putc, void, putc, const char) EXPORT_FUNC(puts, void, puts, const char *) EXPORT_FUNC(printf, int, printf, const char*, ...) -#if (defined(CONFIG_X86) && !defined(CONFIG_X86_64)) || defined(CONFIG_PPC) +#if (defined(CONFIG_X86IRQ) && !defined(CONFIG_X86_64)) || defined(CONFIG_PPC) EXPORT_FUNC(irq_install_handler, void, install_hdlr, int, interrupt_handler_t, void*) -- 2.7.4

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[U-Boot] [PATCH] x86: make the LAPIC / IOAPIC construct switchable with Kconfig
by Hannes Schmelzer 18 Nov '18

18 Nov '18

There are still systems running which do not have any LAPIC or even IOAPIC, furthermore the MSRs for that aren't existing and the systems are crashing on trying setup LAPIC. So this commit makes the APIC stuff able to switch off for those boards which dont' have a LAPIC / IOAPIC. Signed-off-by: Hannes Schmelzer <oe5hpm(a)oevsv.at> --- arch/x86/Kconfig | 9 +++++++++ arch/x86/cpu/Makefile | 2 +- arch/x86/cpu/i386/interrupt.c | 3 ++- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a1c18d2..00b69c6 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -736,6 +736,15 @@ config I8259_PIC slave) interrupt controllers. Include this to have U-Boot set up the interrupt correctly. +config APIC + bool + default y + help + The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible + for catching interrupts and distributing them to one one more CPU + cores. In most cases there is some LAPIC (local) for each core and one + I/O APIC. This conjunction is found on most modern x86 systems. + config PINCTRL_ICH6 bool help diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index f862d8c..54668aa 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -35,7 +35,7 @@ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ -obj-y += lapic.o ioapic.o +obj-$(CONFIG_APIC) += lapic.o ioapic.o obj-y += irq.o ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += mp_init.o diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index ed8423e..2744e2e 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -264,8 +264,9 @@ int interrupt_init(void) i8259_init(); #endif +#ifdef CONFIG_APIC lapic_setup(); - +#endif /* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts(); -- 2.7.4

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