January 2018 - U-Boot

Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA
by Goldschmidt Simon 05 Jan '18

05 Jan '18

+ Vignesh + Jason On Wed, 03/01/2018 16:57, Goldschmidt Simon wrote: > On Wed, 03/01/2018 14:51, Jagan Teki wrote: > >> There were already patches posted on this list by me and others, but > >> unfortunately they haven't made it into the repository, yet. > >> > >> Jagan, could you comment on the status of these fixes? I can search > >> for the patchwork items related if you want me to. > > > > 2 out of 1 of this[1] have some discussion still going is it? > > > > [1] https://patchwork.ozlabs.org/patch/838195/ > > No, that series should be dropped. I don't know if I can do anything about that in > patchwork though? > > Let me check the patches from my upstreaming queue when I'm back at work > tomorrow. I'll send a list of patchwork items I needed to get QSPI running on > mach-socfpga. OK, so I need these patches to get qspi work on socfpga: - Series "spi: cadence_spi: Adopt Linux DT bindings" (v4) from Jason Rush: https://patchwork.ozlabs.org/project/uboot/list/?series=13864 - Patch "Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible" (v2) https://patchwork.ozlabs.org/patch/838871/ All patches were discussed with Vignesh in November. Could we make sure these make it into 2018.03 now that we missed 2018.01? Aside from that, I have this patch running which ensures my QSPI (that does not have a reset line) is put into 3 byte address mode that U-Boot needs. This would be *very* helpful, too: https://patchwork.ozlabs.org/patch/826919/ Thanks, Simon

2 1

[U-Boot] FIT nand boot fail to load U-Boot proper
by Jagan Teki 05 Jan '18

05 Jan '18

I have not debugged much on this, just to check whether the same feature work for others or not? SPL is unable to load U-Boot proper, which is fit formatted of two dtb bundle, but normal U-Boot proper loads fine. Log: ---- >>spl:board_init_r() spl_early_init() Trying to boot from NAND : 512 MiB nand_spl_load_image offset:0x00200000 len:64 page:512 Found FIT nand_spl_load_image offset:0x00200000 len:1052 page:512 fit read sector 200000, sectors=1052, dst=177ff980, count=1052 Selecting config 'imx6q-icore'firmware: 'firmware@1' nand_spl_load_image offset:0x0020041c len:510672 page:512 image: dst=17800000, offset=41c, size=7cad0 Selecting config 'imx6q-icore'fdt: 'fdt@1' nand_spl_load_image offset:0x0027ceec len:30884 page:636 image: dst=1787cb00, offset=7ceec, size=78a4 Selecting config 'imx6q-icore'cannot find property 'loadables': -1 if entry = 0x0, load = 0x17800000 entry = 0x17800000, load = 0x17800000 Jumping to U-Boot loaded - jumping to U-Boot... image entry point: 0x17800000 << hang >> thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.

1 0

[U-Boot] [PATCH 01/03] spmi: msm: display the PMIC Arb version (debug)
by Jorge Ramirez-Ortiz 05 Jan '18

05 Jan '18

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz(a)linaro.org> --- drivers/spmi/spmi-msm.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c index c226913..e9bfbb0 100644 --- a/drivers/spmi/spmi-msm.c +++ b/drivers/spmi/spmi-msm.c @@ -17,6 +17,11 @@ DECLARE_GLOBAL_DATA_PTR; + +/* PMIC Arbiter configuration registers */ +#define PMIC_ARB_VERSION 0x0000 +#define PMIC_ARB_VERSION_V2_MIN 0x20010000 + #define ARB_CHANNEL_OFFSET(n) (0x4 * (n)) #define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000) @@ -148,6 +153,8 @@ static int msm_spmi_probe(struct udevice *dev) struct udevice *parent = dev->parent; struct msm_spmi_priv *priv = dev_get_priv(dev); int node = dev_of_offset(dev); + u32 hw_ver; + bool is_v1; int i; priv->arb_chnl = devfdt_get_addr(dev); @@ -155,6 +162,12 @@ static int msm_spmi_probe(struct udevice *dev) dev_of_offset(parent), node, "reg", 1, NULL, false); priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, dev_of_offset(parent), node, "reg", 2, NULL, false); + + hw_ver = readl(priv->arb_chnl + PMIC_ARB_VERSION - 0x800); + is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN); + + dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), hw_ver); + if (priv->arb_chnl == FDT_ADDR_T_NONE || priv->spmi_core == FDT_ADDR_T_NONE || priv->spmi_obs == FDT_ADDR_T_NONE) -- 2.7.4

1 2

[U-Boot] [RFC PATCH 0/1] Add Rockchip SFC driver under mtd/spi-nor framework
by Andy Yan 05 Jan '18

05 Jan '18

Hi: Jagan, very glad to see the update of your SNI-NOR series. So I send the Rockchip SFC(Serial Flash Controller) driver base on it. Comments are appreciate. Andy Yan (1): mtd: spi-nor: add rockchip sfc driver drivers/mtd/spi-nor/Kconfig | 8 + drivers/mtd/spi-nor/Makefile | 1 + drivers/mtd/spi-nor/rockchip_sfc.c | 432 +++++++++++++++++++++++++++++++++++++ 3 files changed, 441 insertions(+) create mode 100644 drivers/mtd/spi-nor/rockchip_sfc.c -- 2.7.4

1 1

[U-Boot] [PATCH 2/3] arm: i.MX6: fix nand boot device slection
by Jagan Teki 05 Jan '18

05 Jan '18

from i.MX6QDRM.pdf, Table 8-7 nand boot device selection on i.MX6QDL not only depends on bit 7 of BOOT_CFG1 but other three bits are don't care like BOOT_CFG1[7:4] should be 1xxx So, check BOOT_CFG1[7:4] values from 8 to 0xf for nand boot device selection in spl_boot_device Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- arch/arm/include/asm/mach-imx/sys_proto.h | 1 + arch/arm/mach-imx/spl.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 5184e00..92c953b 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -82,6 +82,7 @@ enum imx6_bmode { IMX6_BMODE_MMC, IMX6_BMODE_EMMC, IMX6_BMODE_NAND, + IMX6_BMODE_NANDxxx = 0xf, }; static inline u8 imx6_is_bmode_from_gpr9(void) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index d0d1b73..2bd9048 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -90,8 +90,8 @@ u32 spl_boot_device(void) case IMX6_BMODE_MMC: case IMX6_BMODE_EMMC: return BOOT_DEVICE_MMC1; - /* NAND Flash: 8.5.2, Table 8-10 */ - case IMX6_BMODE_NAND: + /* NAND Flash: 8.5.2, Table 8-10, Table 8-7 CFG1[7:4] = 1xxx */ + case IMX6_BMODE_NAND ... IMX6_BMODE_NANDxxx: return BOOT_DEVICE_NAND; } return BOOT_DEVICE_NONE; -- 2.7.4

1 0

[U-Boot] [PATCH 1/3] board: engicam: Fix to remove legacy board/icorem6_rqs
by Jagan Teki 05 Jan '18

05 Jan '18

board/icorem6_rqs/ is forgot to remove while moving common board files together in (sha1: 52aaddd6f415397bb2eae0d68a8cc1c5c4a98bb3) "i..MX6: engicam: Add imx6q/imx6ul boards for existing boards" Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- board/engicam/icorem6_rqs/icorem6_rqs.c | 48 --------------------------------- 1 file changed, 48 deletions(-) delete mode 100644 board/engicam/icorem6_rqs/icorem6_rqs.c diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c deleted file mode 100644 index a55a754..0000000 --- a/board/engicam/icorem6_rqs/icorem6_rqs.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - * Author: Jagan Teki <jagan(a)amarulasolutions.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/arch/sys_proto.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_ENV_IS_IN_MMC -int board_mmc_get_env_dev(int devno) -{ - return devno - 1; -} -#endif - -#ifdef CONFIG_SPL_BUILD -#include <spl.h> - -#ifdef CONFIG_ENV_IS_IN_MMC -void board_boot_order(u32 *spl_boot_list) -{ - u32 bmode = imx6_src_get_boot_mode(); - u8 boot_dev = BOOT_DEVICE_MMC1; - - switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { - case IMX6_BMODE_SD: - case IMX6_BMODE_ESD: - /* SD/eSD - BOOT_DEVICE_MMC1 */ - break; - case IMX6_BMODE_MMC: - case IMX6_BMODE_EMMC: - /* MMC/eMMC */ - boot_dev = BOOT_DEVICE_MMC2; - break; - default: - /* Default - BOOT_DEVICE_MMC1 */ - printf("Wrong board boot order\n"); - break; - } - - spl_boot_list[0] = boot_dev; -} -#endif -#endif /* CONFIG_SPL_BUILD */ -- 2.7.4

1 2

[U-Boot] [RFC 0/5] sf: Update spi-nor framework
by Prabhakar Kushwaha 05 Jan '18

05 Jan '18

SPI-NOR framework currently supports- - (1-1-1, 1-1-2, 1-1-4) read protocols - read latency(dummy bytes) are hardcoded with the assumption that the flash would support it. - No support of mode bits. - No support of flash size above 128Mib This patch set add support of 1-2-2, 1-4-4 read protocols. It ports Linux commits "mtd: spi-nor: add a stateless method to support memory size above 128Mib" and "mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables". It enables 4byte address opcode and run time flash parameters discovery including dummy cycle and mode cycle. Finally it update fsl-quadspi driver to store(set_mode) spi bus mode and provision for run-time LUTs creation. Note: This patch-set is only **compliation** tested. Sending RFC to get early feed-back on the approach. Prabhakar Kushwaha (5): sf: Add support of 1-2-2, 1-4-4 IO READ protocols sf: add method to support memory size above 128Mib sf: parse Serial Flash Discoverable Parameters (SFDP) tables sf: fsl_qspi: Add support of fsl_qspi_set_mode sf: fsl_quadspi: Configue LUT based on padding information drivers/mtd/spi/sf_internal.h | 230 +++++++++++++++- drivers/mtd/spi/spi_flash.c | 574 +++++++++++++++++++++++++++++++++++++++- drivers/spi/fsl_qspi.c | 85 +++++- include/spi_flash.h | 2 + 5 files changed, 875 insertions(+), 18 deletions(-) -- 2.7.4

5 17

[U-Boot] [PATCH] crypto/fsl: fix BLOB encapsulation and decapsulation
by Clemens Gruber 04 Jan '18

04 Jan '18

The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command" To ensure coherency, we allocate aligned memory to store the data passed to/from CAAM and flush/invalidate the memory regions. Blobs can now be encapsulated and decapsulated with the blob cmd as well as from board code by calling blob_encap and blob_decap directly. Tested on an i.MX6Q board. Signed-off-by: Clemens Gruber <clemens.gruber(a)pqgruber.com> --- drivers/crypto/fsl/fsl_blob.c | 99 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 83 insertions(+), 16 deletions(-) diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index 38c6f9486b..65ce21f4af 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -7,6 +7,7 @@ #include <common.h> #include <malloc.h> +#include <memalign.h> #include <fsl_sec.h> #include <linux/errno.h> #include "jobdesc.h" @@ -15,56 +16,122 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) { - int ret, i = 0; + ALLOC_CACHE_ALIGN_BUFFER(u8, aligned_key_mod, 16); + u8 *aligned_src, *aligned_dst; + int ret, size, i = 0; u32 *desc; printf("\nDecapsulating blob to get data\n"); - desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); + desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); - return -1; + return -ENOMEM; } - inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len); + aligned_src = malloc_cache_aligned(BLOB_SIZE(len)); + aligned_dst = malloc_cache_aligned(len); + if (!aligned_src || !aligned_dst) { + debug("Not enough memory for blob allocations\n"); + return -ENOMEM; + } + + memcpy(aligned_key_mod, key_mod, 16); + size = ALIGN(16, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)aligned_key_mod, + (unsigned long)aligned_key_mod + size); + + memcpy(aligned_src, src, BLOB_SIZE(len)); + size = ALIGN(BLOB_SIZE(len), ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)aligned_src, + (unsigned long)aligned_src + size); + + inline_cnstr_jobdesc_blob_decap(desc, aligned_key_mod, aligned_src, + aligned_dst, len); debug("Descriptor dump:\n"); for (i = 0; i < 14; i++) debug("Word[%d]: %08x\n", i, *(desc + i)); + + size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + size); + ret = run_descriptor_jr(desc); - if (ret) - printf("Error in Decapsulation %d\n", ret); - else - printf("Decapsulation Success\n"); + if (ret) { + printf("Error in blob decapsulation: %d\n", ret); + } else { + size = ALIGN(len, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)aligned_dst, + (unsigned long)aligned_dst + size); + memcpy(dst, aligned_dst, len); + + puts("Blob decapsulation successful.\n"); + } + free(aligned_dst); + free(aligned_src); free(desc); return ret; } int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) { - int ret, i = 0; + ALLOC_CACHE_ALIGN_BUFFER(u8, aligned_key_mod, 16); + u8 *aligned_src, *aligned_dst; + int ret, size, i = 0; u32 *desc; printf("\nEncapsulating data to form blob\n"); - desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); + desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); - return -1; + return -ENOMEM; } - inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len); + aligned_src = malloc_cache_aligned(len); + aligned_dst = malloc_cache_aligned(BLOB_SIZE(len)); + if (!aligned_src || !aligned_dst) { + debug("Not enough memory for blob allocations\n"); + return -ENOMEM; + } + + memcpy(aligned_key_mod, key_mod, 16); + size = ALIGN(16, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)aligned_key_mod, + (unsigned long)aligned_key_mod + size); + + memcpy(aligned_src, src, len); + size = ALIGN(len, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)aligned_src, + (unsigned long)aligned_src + size); + + inline_cnstr_jobdesc_blob_encap(desc, aligned_key_mod, aligned_src, + aligned_dst, len); debug("Descriptor dump:\n"); for (i = 0; i < 14; i++) debug("Word[%d]: %08x\n", i, *(desc + i)); + + size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + size); + ret = run_descriptor_jr(desc); - if (ret) - printf("Error in Encapsulation %d\n", ret); - else - printf("Encapsulation Success\n"); + if (ret) { + printf("Error in blob encapsulation: %d\n", ret); + } else { + size = ALIGN(BLOB_SIZE(len), ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)aligned_dst, + (unsigned long)aligned_dst + size); + memcpy(dst, aligned_dst, BLOB_SIZE(len)); + + puts("Blob encapsulation successful.\n"); + } + free(aligned_dst); + free(aligned_src); free(desc); return ret; } -- 2.15.1

5 10

[U-Boot] [PATCH] ARM: Tegra186: don't map memory not in RAM banks
by Stephen Warren 04 Jan '18

04 Jan '18

From: Stephen Warren <swarren(a)nvidia.com> Tegra186 currently restricts its DRAM usage to entries in the /memory node in the DTB passed to it. However, the MMU configuration always maps the entire first 2GB of RAM. This could allow the CPU to speculatively access RAM that isn't part of the in-use banks. This patch switches to runtime construction of the table that's used to construct the MMU translation tables, and thus prevents access to RAM that's not part of a valid bank. Note: This patch is intended to prevent access to RAM regions which U-Boot does not need to access, with the primary purpose of avoiding theoretical speculative access to physical regions for which the HW will throw errors (e.g. carve-outs that the CPU has no permission to access at a bus level, bad ECC pages, etc.). In particular, this patch is not deliberately related to the speculation-related security issues that were recently announced. The apparent similarity is a coincidence. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- This series relies (at the very least for diff context) on the previous series I sent Jan 3: ARM: Tegra186: mem parsing fixes from downstream ... ARM: tegra: p2771-000: increase max DRAM bank count. --- arch/arm/mach-tegra/arm64-mmu.c | 3 +- arch/arm/mach-tegra/tegra186/nvtboot_mem.c | 78 ++++++++++++++++++++---------- 2 files changed, 55 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index a79a5192e076..3a126bdec4cc 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -12,7 +12,8 @@ #include <asm/system.h> #include <asm/armv8/mmu.h> -static struct mm_region tegra_mem_map[] = { +/* size: IO + NR_DRAM_BANKS + terminator */ +struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = { { .virt = 0x0UL, .phys = 0x0UL, diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c index 33e331f4ca87..2ca59747d4ca 100644 --- a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c +++ b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c @@ -8,6 +8,7 @@ #include <fdt_support.h> #include <fdtdec.h> #include <asm/arch/tegra.h> +#include <asm/armv8/mmu.h> #define SZ_4G 0x100000000ULL @@ -28,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; extern unsigned long nvtboot_boot_x0; +extern struct mm_region tegra_mem_map[]; /* * These variables are written to before relocation, and hence cannot be @@ -36,12 +38,6 @@ extern unsigned long nvtboot_boot_x0; * also has the nice side-effect of the content being valid after relocation. */ -/* A parsed version of /memory/reg from the DTB passed to U-Boot in x0 */ -static struct { - u64 start; - u64 size; -} ram_banks[CONFIG_NR_DRAM_BANKS] __attribute__((section(".data"))); - /* The number of valid entries in ram_banks[] */ static int ram_bank_count __attribute__((section(".data"))); @@ -62,8 +58,6 @@ int dram_init(void) int node, len, i; const u32 *prop; - memset(ram_banks, 0, sizeof(ram_banks)); - na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2); ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2); @@ -81,36 +75,70 @@ int dram_init(void) /* Calculate the true # of base/size pairs to read */ len /= 4; /* Convert bytes to number of cells */ len /= (na + ns); /* Convert cells to number of banks */ - if (len > ARRAY_SIZE(ram_banks)) - len = ARRAY_SIZE(ram_banks); - ram_bank_count = len; + if (len > CONFIG_NR_DRAM_BANKS) + len = CONFIG_NR_DRAM_BANKS; + /* Parse the /memory node, and save useful entries */ gd->ram_size = 0; - for (i = 0; i < ram_bank_count; i++) { - u64 bank_end, usable_bank_size; + ram_bank_count = 0; + for (i = 0; i < len; i++) { + u64 bank_start, bank_end, bank_size, usable_bank_size; - ram_banks[i].start = fdt_read_number(prop, na); + /* Extract raw memory region data from DTB */ + bank_start = fdt_read_number(prop, na); prop += na; - ram_banks[i].size = fdt_read_number(prop, ns); + bank_size = fdt_read_number(prop, ns); prop += ns; - gd->ram_size += ram_banks[i].size; - debug("Bank %d: start: %llx size: %llx\n", i, - ram_banks[i].start, ram_banks[i].size); - - bank_end = ram_banks[i].start + ram_banks[i].size; - debug(" end %llx\n", bank_end); + gd->ram_size += bank_size; + bank_end = bank_start + bank_size; + debug("Bank %d: %llx..%llx (+%llx)\n", i, + bank_start, bank_end, bank_size); + + /* + * Align the bank to MMU section size. This is not strictly + * necessary, since the translation table construction code + * handles page granularity without issue. However, aligning + * the MMU entries reduces the size and number of levels in the + * page table, so is worth it. + */ + bank_start = ROUND(bank_start, SZ_2M); + bank_end = bank_end & ~(SZ_2M - 1); + bank_size = bank_end - bank_start; + debug(" aligned: %llx..%llx (+%llx)\n", + bank_start, bank_end, bank_size); + if (bank_end <= bank_start) + continue; + + /* Record data used to create MMU translation tables */ + ram_bank_count++; + /* Index below is deliberately 1-based to skip MMIO entry */ + tegra_mem_map[ram_bank_count].virt = bank_start; + tegra_mem_map[ram_bank_count].phys = bank_start; + tegra_mem_map[ram_bank_count].size = bank_size; + tegra_mem_map[ram_bank_count].attrs = + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; + + /* Determine best bank to relocate U-Boot into */ if (bank_end > SZ_4G) bank_end = SZ_4G; debug(" end %llx (usable)\n", bank_end); - usable_bank_size = bank_end - ram_banks[i].start; + usable_bank_size = bank_end - bank_start; debug(" size %llx (usable)\n", usable_bank_size); if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) && (bank_end > ram_top)) { ram_top = bank_end; - region_base = ram_banks[i].start; + region_base = bank_start; debug("ram top now %llx\n", ram_top); } } + + /* Ensure memory map contains the desired sentinel entry */ + tegra_mem_map[ram_bank_count + 1].virt = 0; + tegra_mem_map[ram_bank_count + 1].phys = 0; + tegra_mem_map[ram_bank_count + 1].size = 0; + tegra_mem_map[ram_bank_count + 1].attrs = 0; + + /* Error out if a relocation target couldn't be found */ if (!ram_top) { pr_err("Can't find a usable RAM top"); hang(); @@ -129,8 +157,8 @@ int dram_init_banksize(void) } for (i = 0; i < ram_bank_count; i++) { - gd->bd->bi_dram[i].start = ram_banks[i].start; - gd->bd->bi_dram[i].size = ram_banks[i].size; + gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; + gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; } #ifdef CONFIG_PCI -- 2.15.1

1 0

[U-Boot] [PATCH v1] x86: tangier: Use actual GPIO hardware numbers
by Andy Shevchenko 04 Jan '18

04 Jan '18

The recent commit 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") in the Linux kernel reveals the issue we have in ACPI tables here, i.e. we must use hardware numbers for GPIO resources and, taking into consideration that GPIO and pin control are *different* IPs on Intel Tangier, we need to supply numbers properly. Besides that, it improves user experience since the official documentation for Intel Edison board is referring to GPIO hardware numbering scheme. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- Bin, this is kinda urgent fix. I wouldn't like to have a release with wrong numbering scheme, although there is none users yet, only couple amateurs that are experimenting with the code. arch/x86/include/asm/arch-tangier/acpi/southcluster.asl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index 288b57cb80..8162df59b5 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -173,13 +173,13 @@ Device (PCI0) Name (RBUF, ResourceTemplate() { GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, - "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 91 } + "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 110 } GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, - "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 92 } + "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 111 } GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, - "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 93 } + "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 112 } GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, - "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 94 } + "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 113 } }) Method (_CRS, 0, NotSerialized) @@ -245,7 +245,7 @@ Device (PCI0) { Connection ( GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, - "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 56 } + "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 96 } ), WFD3, 1, } -- 2.15.1

1 0