January 2018 - U-Boot

[U-Boot] [PATCH 4/4] serial: ns16550: use 13x oversampling when available
by Matthijs van Duin 08 Jan '18

08 Jan '18

This allows much higher baudrates in the standard series to be used, up to 32 * 115200 = 3686400 bps with 0.16% deviation. Signed-off-by: Matthijs van Duin <matthijsvanduin(a)gmail.com> --- drivers/serial/ns16550.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 41eb098c847e..a131d1658bd4 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -140,7 +140,11 @@ static u32 ns16550_getfcr(NS16550_t port) int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) { +#ifdef UART_MDR1_13X + const unsigned int mode_x_div = 13; +#else const unsigned int mode_x_div = 16; +#endif return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); } @@ -181,9 +185,9 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(ns16550_getfcr(com_port), &com_port->fcr); if (baud_divisor != -1) NS16550_setbrg(com_port, baud_divisor); -#ifdef CONFIG_NS16550_OMAP - /* /16 is proper to hit 115200 with 48MHz */ - serial_out(UART_MDR1_16X, &com_port->mdr1); +#ifdef UART_MDR1_13X + /* /13 is proper to hit 115200*{1,2,4,8,16,32} with 48MHz */ + serial_out(UART_MDR1_13X, &com_port->mdr1); #endif #ifdef CONFIG_NS16550_C6X serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->pwr_mgmt); @@ -297,7 +301,7 @@ static inline void _debug_uart_init(void) serial_dout(&com_port->dll, baud_divisor & 0xff); serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); serial_dout(&com_port->lcr, UART_LCRVAL); - serial_dout(&com_port->mdr1, UART_MDR1_16X); + serial_dout(&com_port->mdr1, UART_MDR1_13X); } static inline void _debug_uart_putc(int ch) -- 2.11.0

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[U-Boot] [PATCH 3/4] serial: ns16550: add definitions for register mdr1
by Matthijs van Duin 08 Jan '18

08 Jan '18

Signed-off-by: Matthijs van Duin <matthijsvanduin(a)gmail.com> --- drivers/serial/ns16550.c | 10 +++++----- include/ns16550.h | 14 ++++++++++++++ 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 5ac2469b5760..41eb098c847e 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -166,7 +166,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) == UART_LSR_THRE) { if (baud_divisor != -1) NS16550_setbrg(com_port, baud_divisor); - serial_out(0, &com_port->mdr1); + serial_out(UART_MDR1_16X, &com_port->mdr1); } #endif @@ -175,7 +175,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); #ifdef CONFIG_NS16550_OMAP - serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ + serial_out(UART_MDR1_DISABLE, &com_port->mdr1); #endif serial_out(UART_MCRVAL, &com_port->mcr); serial_out(ns16550_getfcr(com_port), &com_port->fcr); @@ -183,7 +183,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) NS16550_setbrg(com_port, baud_divisor); #ifdef CONFIG_NS16550_OMAP /* /16 is proper to hit 115200 with 48MHz */ - serial_out(0, &com_port->mdr1); + serial_out(UART_MDR1_16X, &com_port->mdr1); #endif #ifdef CONFIG_NS16550_C6X serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->pwr_mgmt); @@ -289,7 +289,7 @@ static inline void _debug_uart_init(void) baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); - serial_dout(&com_port->mdr1, 0x7); + serial_dout(&com_port->mdr1, UART_MDR1_DISABLE); serial_dout(&com_port->mcr, UART_MCRVAL); serial_dout(&com_port->fcr, UART_FCR_DEFVAL); @@ -297,7 +297,7 @@ static inline void _debug_uart_init(void) serial_dout(&com_port->dll, baud_divisor & 0xff); serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); serial_dout(&com_port->lcr, UART_LCRVAL); - serial_dout(&com_port->mdr1, 0x0); + serial_dout(&com_port->mdr1, UART_MDR1_16X); } static inline void _debug_uart_putc(int ch) diff --git a/include/ns16550.h b/include/ns16550.h index 4a87ab9c8e71..540337258c1e 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -208,6 +208,20 @@ typedef struct NS16550 *NS16550_t; /* useful defaults for LCR */ #define UART_LCR_8N1 0x03 +/* + * These are the definitions for Mode Definition Register 1 + */ +#if defined(CONFIG_NS16550_C6X) +#define UART_MDR1_16X 0x00 /* 16x oversampling (default) */ +#define UART_MDR1_13X 0x01 /* 13x oversampling */ +#elif defined(CONFIG_NS16550_OMAP) +#define UART_MDR1_16X 0x00 /* 16x oversampling */ +#define UART_MDR1_16X_AUTOBAUD 0x02 /* 16x oversampling, auto-baud */ +#define UART_MDR1_13X 0x03 /* 13x oversampling */ +#define UART_MDR1_DISABLE 0x07 /* disable uart (default) */ +/* other values/bits are for infrared modes */ +#endif + void NS16550_init(NS16550_t com_port, int baud_divisor); void NS16550_putc(NS16550_t com_port, char c); char NS16550_getc(NS16550_t com_port); -- 2.11.0

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[U-Boot] [PATCH 2/4] serial: ns16550: centralize identification of uart variants
by Matthijs van Duin 08 Jan '18

08 Jan '18

Signed-off-by: Matthijs van Duin <matthijsvanduin(a)gmail.com> --- drivers/serial/ns16550.c | 8 ++++---- include/ns16550.h | 11 +++++++++-- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 9cec58c887c8..5ac2469b5760 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif #endif /* !CONFIG_DM_SERIAL */ -#if defined(CONFIG_SOC_KEYSTONE) || defined(CONFIG_SOC_DA8XX) +#ifdef CONFIG_NS16550_C6X #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) #undef UART_MCRVAL @@ -174,18 +174,18 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) ; serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); -#if defined(CONFIG_ARCH_OMAP2PLUS) +#ifdef CONFIG_NS16550_OMAP serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif serial_out(UART_MCRVAL, &com_port->mcr); serial_out(ns16550_getfcr(com_port), &com_port->fcr); if (baud_divisor != -1) NS16550_setbrg(com_port, baud_divisor); -#if defined(CONFIG_ARCH_OMAP2PLUS) +#ifdef CONFIG_NS16550_OMAP /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); #endif -#if defined(CONFIG_SOC_KEYSTONE) || defined(CONFIG_SOC_DA8XX) +#ifdef CONFIG_NS16550_C6X serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->pwr_mgmt); #endif } diff --git a/include/ns16550.h b/include/ns16550.h index a988d297e144..4a87ab9c8e71 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -45,6 +45,13 @@ unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; #endif +/* Identify major NS16550 variants */ +#if defined(CONFIG_SOC_KEYSTONE) || defined(CONFIG_SOC_DA8XX) +#define CONFIG_NS16550_C6X 1 +#elif defined(CONFIG_ARCH_OMAP2PLUS) +#define CONFIG_NS16550_OMAP 1 +#endif + /** * struct ns16550_platdata - information about a NS16550 port * @@ -71,14 +78,14 @@ struct NS16550 { UART_REG(lsr); /* 5 */ UART_REG(msr); /* 6 */ UART_REG(spr); /* 7 */ -#if defined(CONFIG_SOC_KEYSTONE) || defined(CONFIG_SOC_DA8XX) +#if defined(CONFIG_NS16550_C6X) UART_REG(reg8); /* 8 */ UART_REG(reg9); /* 9 */ UART_REG(revid1); /* A */ UART_REG(revid2); /* B */ UART_REG(pwr_mgmt); /* C */ UART_REG(mdr1); /* D */ -#else +#elif defined(CONFIG_NS16550_OMAP) UART_REG(mdr1); /* 8 */ UART_REG(reg9); /* 9 */ UART_REG(regA); /* A */ -- 2.11.0

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[U-Boot] [PATCH 0/4] serial: ns16550: cleanups and 13x oversampling
by Matthijs van Duin 08 Jan '18

08 Jan '18

This is a small patch set we've been using internally for a while now, and I figured it may be useful for mainline. It originated from the desire of running the linux console at a higher bitrate, and therefore also the u-boot console for consistency's sake. When using 16x oversampling and an 48 MHz reference clock, the standard rate 115200 requires a /26 divider, which also means that the only higher standard rate available is 230400 (/13 divider). In contrast, if 13x oversampling is used then the divider for 115200 is /32, which yields a much greater range of standard rates to be used. This patch set consists of three cleanup patches related to TI OMAP and TI C6x style uarts, and finally one patch that configures 13x oversampling on both of them. -- Matthijs van Duin

1 0

[U-Boot] [BUG] x86: incorrect dram definition in dram_init_banksize().
by Heinrich Schuchardt 08 Jan '18

08 Jan '18

Function efi_add_known_memory uses the configured DRAM banks (gd->bd->bi_dram) to define the memory that an EFI application may use. For qemu-x86_defconfig this will result in the first 1 MB of physical memory being available. Here we find the BIOS, interrupt vectors and the VGA memory (0xA0000-0xBFFFF). As a result grubia32.efi writes unknowingly to the video memory. For reference: In function install_e820_map() we block [ISA_START_ADDRESS, ISA_END_ADDRESS[. The problem seems to stem from file arch/x86/cpu/qemu/dram.c, function dram_init_banksize(): gd->bd->bi_dram[0].start = 0; gd->bd->bi_dram[0].size = gd->ram_size; Probably exluding [ISA_START_ADDRESS, ISA_END_ADDRESS[ is not sufficient as this does not protect interrupt vectors. Could you, please, provide reasonable values. Maybe a better idea would be to define reserved memory like the ones that we find in the device trees, e.g. reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; /* 16 MiB reserved for Hardware ROM Firmware */ hwrom_reserved: hwrom@0 { reg = <0x0 0x0 0x0 0x1000000>; no-map; }; But U-Boot does not yet support the concept of reserved memory. Best regards Heinrich

2 2

[U-Boot] [PATCH v3] mx6ull: Handle the CONFIG_MX6ULL cases correctly
by Fabio Estevam 08 Jan '18

08 Jan '18

Since commit 051ba9e082f7 ("Kconfig: mx6ull: Deselect MX6UL from CONFIG_MX6ULL") CONFIG_MX6ULL does not select CONFIG_MX6UL anymore, so take this into consideration in all the checks for CONFIG_MX6UL. This fixes a boot regression. Reported-by: Stefan Agner <stefan(a)agner.ch> Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> Reviewed-by: Stefan Agner <stefan(a)agner.ch> Tested-by: Breno Lima <breno.lima(a)nxp.com> Tested-by: Peng Fan <peng.fan(a)nxp.com> --- Changes since v2: - Also fix include/configs/imx6_spl.h (Stefano) arch/arm/include/asm/arch-mx6/imx-regs.h | 23 +++++++++++++---------- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 +- arch/arm/include/asm/arch-mx6/mx6ul-ddr.h | 2 +- arch/arm/include/asm/mach-imx/iomux-v3.h | 4 ++-- arch/arm/include/asm/mach-imx/regs-lcdif.h | 19 +++++++++++++------ arch/arm/mach-imx/mx6/Kconfig | 2 +- arch/arm/mach-imx/mx6/ddr.c | 2 +- drivers/gpio/mxc_gpio.c | 4 ++-- include/configs/imx6_spl.h | 3 ++- include/configs/mx6_common.h | 7 ++++--- 10 files changed, 40 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 7736b6a..4be7aab 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -17,7 +17,7 @@ #define GPU_2D_ARB_END_ADDR 0x02203FFF #define OPENVG_ARB_BASE_ADDR 0x02204000 #define OPENVG_ARB_END_ADDR 0x02207FFF -#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) +#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_END_ADDR 0x00107FFF #define GPU_ARB_BASE_ADDR 0x01800000 @@ -46,7 +46,8 @@ #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) /* GPV - PL301 configuration ports */ -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ +#if (defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)) #define GPV2_BASE_ADDR 0x00D00000 #define GPV3_BASE_ADDR 0x00E00000 @@ -88,7 +89,7 @@ #define QSPI0_AMBA_END 0x6FFFFFFF #define QSPI1_AMBA_BASE 0x70000000 #define QSPI1_AMBA_END 0x7FFFFFFF -#elif defined(CONFIG_MX6UL) +#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define WEIM_ARB_BASE_ADDR 0x50000000 #define WEIM_ARB_END_ADDR 0x57FFFFFF #define QSPI0_AMBA_BASE 0x60000000 @@ -109,7 +110,8 @@ #endif #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ - defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) + defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define MMDC0_ARB_BASE_ADDR 0x80000000 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF #define MMDC1_ARB_BASE_ADDR 0xC0000000 @@ -262,7 +264,7 @@ #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) /* i.MX6SL/SLL */ #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#ifdef CONFIG_MX6UL +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) #else /* i.MX6SX */ @@ -288,7 +290,7 @@ #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) #endif #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#ifdef CONFIG_MX6UL +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #elif defined(CONFIG_MX6SX) @@ -337,7 +339,7 @@ #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) -#elif defined(CONFIG_MX6ULL) +#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) @@ -354,7 +356,8 @@ #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ +#if !(defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)) #define IRAM_SIZE 0x00040000 #else @@ -573,7 +576,7 @@ struct src { #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) struct iomuxc { -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) u8 reserved[0x4000]; #endif u32 gpr[14]; @@ -700,7 +703,7 @@ struct cspi_regs { #define MXC_CSPICON_SSPOL 12 /* SS polarity */ #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ - defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) + defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ ECSPI2_BASE_ADDR, \ diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 2a8d443..19d2f1d 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -16,7 +16,7 @@ #ifdef CONFIG_MX6SX #include "mx6sx-ddr.h" #else -#ifdef CONFIG_MX6UL +#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) #include "mx6ul-ddr.h" #else #ifdef CONFIG_MX6SL diff --git a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h index ed11c4b..518b812 100644 --- a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h @@ -7,7 +7,7 @@ #ifndef __ASM_ARCH_MX6UL_DDR_H__ #define __ASM_ARCH_MX6UL_DDR_H__ -#ifndef CONFIG_MX6UL +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #error "wrong CPU" #endif diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index ad35e01..ed75e9c 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -127,7 +127,7 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_ODE (1 << 11) -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) #define PAD_CTL_SPEED_LOW (0 << 6) #else #define PAD_CTL_SPEED_LOW (1 << 6) @@ -253,7 +253,7 @@ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \ imx_iomux_v3_setup_pad(MX6Q_##def); #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) -#elif defined(CONFIG_MX6UL) +#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) #define IOMUX_PADS(x) MX6_##x #define SETUP_IOMUX_PAD(def) \ imx_iomux_v3_setup_pad(MX6_##def); diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h index 4de401b..c6cf03b 100644 --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -19,8 +19,11 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ -#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) + +#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX7) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -55,8 +58,10 @@ struct mxs_lcdif_regs { #endif mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ -#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) +#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX7) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ @@ -64,8 +69,10 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */ mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */ mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */ -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) +#if defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX7) mxs_reg_32(hw_lcdif_thres) mxs_reg_32(hw_lcdif_as_ctrl) mxs_reg_32(hw_lcdif_as_buf) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 18e1e67..2552a50 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -8,7 +8,7 @@ config MX6_SMP bool config MX6 - select ARM_ERRATA_743622 if !MX6UL + select ARM_ERRATA_743622 if !MX6UL && !MX6ULL bool default y imply CMD_FUSE diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 0cf391e..52a9a25 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -631,7 +631,7 @@ void mx6sx_dram_iocfg(unsigned width, } #endif -#ifdef CONFIG_MX6UL +#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) void mx6ul_dram_iocfg(unsigned width, const struct mx6ul_iomux_ddr_regs *ddr, const struct mx6ul_iomux_grp_regs *grp) diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index c480eba..cfa620b 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -47,12 +47,12 @@ static unsigned long gpio_ports[] = { #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_MX7) [4] = GPIO5_BASE_ADDR, -#ifndef CONFIG_MX6UL +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) [5] = GPIO6_BASE_ADDR, #endif #endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) -#ifndef CONFIG_MX6UL +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) [6] = GPIO7_BASE_ADDR, #endif #endif diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index cdb3a37..dd48120 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -55,7 +55,8 @@ # endif #endif -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL) +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) #define CONFIG_SPL_BSS_START_ADDR 0x88200000 #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ #define CONFIG_SYS_SPL_MALLOC_START 0x88300000 diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 5fb85a1..59e6dae 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -7,7 +7,7 @@ #ifndef __MX6_COMMON_H #define __MX6_COMMON_H -#ifndef CONFIG_MX6UL +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE L2_PL310_BASE @@ -37,8 +37,9 @@ #define CONFIG_REVISION_TAG /* Boot options */ -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \ - defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL)) +#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) #define CONFIG_LOADADDR 0x82000000 #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x87800000 -- 2.7.4

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[U-Boot] [PATCH 0/3] cadence-quadspi: Fix issues with non 32bit aligned accesses
by Vignesh R 08 Jan '18

08 Jan '18

This series reverts use of bounce_buf.c for non-DMA related alignment restriction and replaces it with local bounce buffer to handle problems with non 32 bit aligned writes on TI platforms. Based on top of Jason's series: https://patchwork.ozlabs.org/cover/856431/ Tested on K2G EVM. Goldschmidt Simon (1): Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible" Vignesh R (2): Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible" spi: cadence_qspi_apb: Make flash writes 32 bit aligned drivers/spi/cadence_qspi.c | 13 ++++++++++++- drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 42 +++++++++------------------------------- include/configs/k2g_evm.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/stv0991.h | 1 - 6 files changed, 22 insertions(+), 37 deletions(-) -- 2.15.1

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[U-Boot] "Reset" values for clksel_con registers in clk_rk3399.c:rkclk_init()
by Dr. Philipp Tomsich 08 Jan '18

08 Jan '18

Kever, I came across an odd question in clk_rk3399.c while implementing the reparenting (for assigned-clock-parents) that I today discussed with David Wu… looks like the following code is supposed to restore the reset values to 3 registers, but both the NDA-version of the TRM and the public version of the TRM list different (consistent between the two TRM versions) values. The code in question is: /* * some cru registers changed by bootrom, we'd better reset them to * reset/default values described in TRM to avoid confusion in kernel. * Please consider these three lines as a fix of bootrom bug. */ rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); However, my manual states that the default values are: CLKSEL_CON12 0x100 CLKSEL_CON19 0x100 CLKSEL_CON56 0x320 This came in with commit 9f636a24 ("rockchip: rk3399: init CPU clock when rkclk_init()”). This popped up on my radar, as I was wondering why GbE had been working so far for us, even though we never had any reparenting code for the RK3399. Do you know why our init code is setting these values and why this doesn’t match the comment? I also tried to see if the register-numbers were wrong and the writes went to the wrong registers, but I couldn’t find any register in the CLKSEL_CON block that had 0x4101 or 0x33f as a default/reset value. Thanks, Philipp.

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[U-Boot] [PATCH 0/6] Add Bananapi Zero board with OTG supported
by Jun Nie 08 Jan '18

08 Jan '18

Add Bananapi Zero board defconfig and device tree. OTG device is supported with enabling clock and adding necessary controller configuration change. USB mass storage is tested as a test case. Jun Nie (6): sunxi: h3: add usb_otg and OHCI/EHCI for usbc0 on H3 sunxi: musb: Add fifo config for H3 sunxi: musb: Enable OTG device clock for H3 sunxi: musb: Hack dynamic fifo support for H3 OTG sunxi: usb_phy: Clear PHYCTL register before writing sunxi: Add initial Banana-Pi Zero support arch/arm/dts/Makefile | 1 + arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 113 ++++++++++++++++++++++++ arch/arm/dts/sun8i-h3.dtsi | 32 +++++++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 4 + arch/arm/mach-sunxi/usb_phy.c | 8 +- configs/bananapi_zero_defconfig | 17 ++++ drivers/usb/musb-new/musb_regs.h | 3 +- drivers/usb/musb-new/sunxi.c | 51 +++++++++++ 9 files changed, 229 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts create mode 100644 configs/bananapi_zero_defconfig -- 1.9.1

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[U-Boot] "fdt" commands in extlinux.conf ?
by Ken Harris 08 Jan '18

08 Jan '18

I'd like to enable the CANbus on a Beagle Bone Black (on Fedora ... which doesn't do "cape manager"). The crux is a fdt command in u-boot : fdt set d_can1 status okay Is there a way to do this in extlinux.conf ? I didn't see a way (in uboot 2017.09), so I wrote a uEnv.txt script (see attached). That's a bit verbose and duplicates a bunch of stuff already in uboot (also : uEnv.txt doesn't exist on my "Orange Pi One"). It there a simpler way to state "fdt" commands ? Thanks

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