July 2017 - U-Boot

[U-Boot] [PATCH 0/9] stm32f7 clock improvements
by patrice.chotard＠st.com 26 Jul '17

26 Jul '17

From: Patrice Chotard <patrice.chotard(a)st.com> The objective of this series is to prepare the ground for future STM32H7 SoC introduction. As STM32F7 and STM32H7 SoCs shared several blocks (serial, qspi, gpio ....) some rework is needed to made some drivers more generic. Some of these driver are using proprietatry clock glue which need to be replace by clock framework one, which also implies stm32f7 clock driver rework. Here are the steps: _ align stm32f7 clock DT declaration with kernel one _ retrieve RCC base address from DT _ replace the stm32f7 clock_get() glue function by clock framework clk_get_rate() inside several driver : _ drivers/spi/stm32_qspi.c _ drivers/serial/serial_stm32x7.c _ remove proprietary clock glue Patrice Chotard (9): ARM: DTS: stm32: align DT clock declaration with kernel clk: stm32f7: add static for configure_clocks() clk: stm32f7: get RCC base address from DT clk: stm32f7: add clock .get_rate() callback clk: stm32f7: cleanup clocks unused definitions serial: stm32x7: migrate serial struct to driver serial: stm32x7: add clk_get_rate() support spi: stm32_qspi: add clk_get_rate() support clk: stm32f7: remove clock_get() arch/arm/dts/stm32f746.dtsi | 30 +++--- arch/arm/include/asm/arch-stm32f7/rcc.h | 24 +---- arch/arm/include/asm/arch-stm32f7/stm32.h | 13 --- arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 15 --- board/st/stm32f746-disco/stm32f746-disco.c | 1 - drivers/clk/clk_stm32f7.c | 100 +++++++++++++------- drivers/serial/serial_stm32x7.c | 18 ++-- drivers/serial/serial_stm32x7.h | 5 + drivers/spi/stm32_qspi.c | 10 +- include/dm/platform_data/serial_stm32x7.h | 17 ---- include/dt-bindings/clock/stm32fx-clock.h | 59 ++++++++++++ include/dt-bindings/mfd/stm32f7-rcc.h | 112 +++++++++++++++++++++++ 12 files changed, 276 insertions(+), 128 deletions(-) delete mode 100644 include/dm/platform_data/serial_stm32x7.h create mode 100644 include/dt-bindings/clock/stm32fx-clock.h create mode 100644 include/dt-bindings/mfd/stm32f7-rcc.h -- 1.9.1

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[U-Boot] [PATCH] arm: mach-keystone: Fixes issue with return values in inline assembly
by Andrew F. Davis 26 Jul '17

26 Jul '17

From: "Srinivas, Madan" <madans(a)ti.com> The inline assembly functions in mon.c assume that the caller will check for the return value in r0 according to regular ARM calling conventions. However, this assumption breaks down if the compiler inlines the functions. The caller is then under no obligation to use r0 for the result. To fix this disconnect, we must explicitly move the return value from the smc/bl call to the variable that the function returns. Signed-off-by: Madan Srinivas <madans(a)ti.com> --- arch/arm/mach-keystone/mon.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c index 7076a2a67b..dd446ab011 100644 --- a/arch/arm/mach-keystone/mon.c +++ b/arch/arm/mach-keystone/mon.c @@ -24,6 +24,7 @@ int mon_install(u32 addr, u32 dpsc, u32 freq, u32 bm_addr) "mov r2, %3\n" "mov r3, %4\n" "blx r0\n" + "mov %0, r0\n" "ldmfd r13!, {lr}\n" : "=&r" (result) : "r" (addr), "r" (dpsc), "r" (freq), "r" (bm_addr) @@ -41,6 +42,7 @@ int mon_power_on(int core_id, void *ep) "mov r2, %2\n" "mov r0, #0\n" "smc #0\n" + "mov %0, r0\n" "ldmfd r13!, {lr}\n" : "=&r" (result) : "r" (core_id), "r" (ep) @@ -57,6 +59,7 @@ int mon_power_off(int core_id) "mov r1, %1\n" "mov r0, #1\n" "smc #1\n" + "mov %0, r0\n" "ldmfd r13!, {lr}\n" : "=&r" (result) : "r" (core_id) @@ -90,6 +93,7 @@ static int k2_hs_bm_auth(int cmd, void *arg1) "mov r0, %1\n" "mov r1, %2\n" "smc #2\n" + "mov %0, r0\n" "ldmfd r13!, {r4-r12, lr}\n" : "=&r" (result) : "r" (cmd), "r" (arg1) -- 2.13.0

2 2

[U-Boot] [PATCH] configs: ti: armv7: Fixes bug in fit_loadaddr for ramfs boot
by Andrew F. Davis 26 Jul '17

26 Jul '17

From: Madan Srinivas <madans(a)ti.com> The load address of ramdisk, rdaddr is 0x88080000 and fit_loadaddr is defined as 0x88000000. This leaves only 512Kbytes for the fit image. When the FIT images are larger than this, it will overwite the ramdisk and cause the boot to fail. For eg, The K2 HS fit images are a few MB and end up overwriting the ramdsk. This patch moves the fit_loadaddr to 0x87000000, leaving a 16MB window for the fit image. This memory can be reclaimed once the kernel starts running. Signed-off-by: Madan Srinivas <madans(a)ti.com> --- include/configs/ti_armv7_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index a4676d3a7f..16ea22857f 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -53,7 +53,7 @@ #define DEFAULT_FIT_TI_ARGS \ "boot_fit=0\0" \ - "fit_loadaddr=0x88000000\0" \ + "fit_loadaddr=0x87000000\0" \ "fit_bootfile=fitImage\0" \ "update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \ "loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \ -- 2.13.0

2 4

[U-Boot] [PATCH 0/4] Add default secure boot env for K2x
by Andrew F. Davis 26 Jul '17

26 Jul '17

Hello all, This series adds the default environment variables needed to boot K2x family secure devices. Thanks, Andrew Andrew F. Davis (2): configs: k2x_evm: Adds FIT loading environment variables configs: k2x_evm: Reorder default boot command Madan Srinivas (2): configs: k2x_evm: Adds environment variables for secure devices arm: mach-keystone: Updates mon_install for K2G HS arch/arm/mach-keystone/cmd_mon.c | 8 ++++++-- arch/arm/mach-keystone/include/mach/mon.h | 2 +- arch/arm/mach-keystone/mon.c | 7 ++++--- include/configs/k2e_evm.h | 9 +++++++++ include/configs/k2g_evm.h | 23 ++++++++++++++++++++--- include/configs/k2hk_evm.h | 9 +++++++++ include/configs/ti_armv7_keystone2.h | 30 +++++++++++++++++++++++++++--- 7 files changed, 76 insertions(+), 12 deletions(-) -- 2.13.0

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[U-Boot] [PATCH 1/2] board: ti: am57xx: Fix detection of board version
by Lokesh Vutla 26 Jul '17

26 Jul '17

board_is*("rev", board_ti_get_rev()) uses strncmp() for revison detection and assumes it is success if return value is <= 0. This will fail in case of multiple versions, as revb will be true for board_is_*revb() and board_is_*reva(). Fix it by looking for exact match of the string. Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- board/ti/am57xx/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index bf8c8e1a67..6e248d6b1a 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -36,11 +36,11 @@ #define board_is_x15() board_ti_is("BBRDX15_") #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \ - (strncmp("B.10", board_ti_get_rev(), 3) <= 0)) + !strncmp("B.10", board_ti_get_rev(), 3)) #define board_is_am572x_evm() board_ti_is("AM572PM_") #define board_is_am572x_evm_reva3() \ (board_ti_is("AM572PM_") && \ - (strncmp("A.30", board_ti_get_rev(), 3) <= 0)) + !strncmp("A.30", board_ti_get_rev(), 3)) #define board_is_am572x_idk() board_ti_is("AM572IDK") #define board_is_am571x_idk() board_ti_is("AM571IDK") -- 2.13.0

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[U-Boot] [PATCH] efi_loader: only evaluate EFI_EXIT()'s ret once
by Rob Clark 26 Jul '17

26 Jul '17

There are a couple spots doing things like: return EFI_EXIT(some_fxn(...)); which I handn't noticed before. With addition of printing return value in the EFI_EXIT() macro, now the fxn call was getting evaluated twice. Which we didn't really want. Signed-off-by: Rob Clark <robdclark(a)gmail.com> --- I can rebase this one to come before the other EFI_ENTER/EFI_EXIT patches that I sent earlier today if needed. include/efi_loader.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/efi_loader.h b/include/efi_loader.h index b4e9a80034..1522800764 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -32,10 +32,11 @@ const char *__efi_nesting_level(int delta); * Exit the u-boot world back to UEFI: */ #define EFI_EXIT(ret) ({ \ + efi_status_t _r = ret; \ debug("%sEFI: Exit: %s: %u\n", __efi_nesting_level(-1), \ - __func__, (u32)((ret) & ~EFI_ERROR_MASK)); \ + __func__, (u32)(_r & ~EFI_ERROR_MASK)); \ assert(__efi_check_nesting(-1)); \ - efi_exit_func(ret); \ + efi_exit_func(_r); \ }) /* -- 2.13.0

1 0

[U-Boot] Convert CMD_NAND to KConfig (help)
by Adam Ford 26 Jul '17

26 Jul '17

Hey gang, I tried to convert boards to CMD_NAND with ./tools/moveconfig.py, but when when I attempted to send the patch, Google said I cannot send to that many people. Does anyone have any suggestions on how to send a patch to 104 different addresses? I really didnt' want to spam that many people, but that's what the get_maintainer.py script is showing. If someone else is working on this, I'll step back, but I had some more conversion scripts ready to try but lack of CMD_NAND is holding me back. adam

2 1

[U-Boot] [PATCH v2] mx6: Add support for Phytec pfla02 (NAND)
by Stefano Babic 26 Jul '17

26 Jul '17

Add support for Phytec pfla02, equipped with NAND. CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 31C Reset cause: POR I2C: ready DRAM: 1 GiB NAND: 2048 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 SF: Detected n25q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Stefano Babic <sbabic(a)denx.de> CC: Stefan Christ <s.christ(a)phytec.de> CC: Stefan Müller-Klieser <S.Mueller-Klieser(a)phytec.de> CC: Christian Hemp <C.Hemp(a)phytec.de> --- Changes in v2: - remove overwriting of CD for USDHC2 (F. Estevam) - Drop unused constant for RAM size (F. Estevam) - Detect the RAM chip (SOM delivered with 1GB / 2GB / 4 GB) arch/arm/mach-imx/mx6/Kconfig | 6 + board/phytec/pfla02/Kconfig | 12 + board/phytec/pfla02/MAINTAINERS | 6 + board/phytec/pfla02/Makefile | 9 + board/phytec/pfla02/README | 24 ++ board/phytec/pfla02/pfla02.c | 698 ++++++++++++++++++++++++++++++++++++++++ configs/pfla02_defconfig | 50 +++ include/configs/pfla02.h | 183 +++++++++++ 8 files changed, 988 insertions(+) create mode 100644 board/phytec/pfla02/Kconfig create mode 100644 board/phytec/pfla02/MAINTAINERS create mode 100644 board/phytec/pfla02/Makefile create mode 100644 board/phytec/pfla02/README create mode 100644 board/phytec/pfla02/pfla02.c create mode 100644 configs/pfla02_defconfig create mode 100644 include/configs/pfla02.h diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 1595a76..d70221a 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -330,6 +330,11 @@ config TARGET_PCM058 select BOARD_LATE_INIT select SUPPORT_SPL +config TARGET_PFLA02 + bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad" + select BOARD_LATE_INIT + select SUPPORT_SPL + config TARGET_SECOMX6 bool "secomx6 boards" @@ -427,6 +432,7 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ullevk/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" +source "board/phytec/pfla02/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" diff --git a/board/phytec/pfla02/Kconfig b/board/phytec/pfla02/Kconfig new file mode 100644 index 0000000..142a122 --- /dev/null +++ b/board/phytec/pfla02/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PFLA02 + +config SYS_BOARD + default "pfla02" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "pfla02" + +endif diff --git a/board/phytec/pfla02/MAINTAINERS b/board/phytec/pfla02/MAINTAINERS new file mode 100644 index 0000000..4b069a9 --- /dev/null +++ b/board/phytec/pfla02/MAINTAINERS @@ -0,0 +1,6 @@ +PHYTEC PHYFLEX +M: Stefano Babic <sbabic(a)denx.de> +S: Maintained +F: board/phytec/pfla02/ +F: include/configs/pfla02.h +F: configs/pfla02_defconfig diff --git a/board/phytec/pfla02/Makefile b/board/phytec/pfla02/Makefile new file mode 100644 index 0000000..25af9a0 --- /dev/null +++ b/board/phytec/pfla02/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg(a)denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pfla02.o diff --git a/board/phytec/pfla02/README b/board/phytec/pfla02/README new file mode 100644 index 0000000..0f46ab8 --- /dev/null +++ b/board/phytec/pfla02/README @@ -0,0 +1,24 @@ +Board information +----------------- + +The evaluation board "pbab01" is thought to be used +together with the SOM. + +More information on the board can be found on manufacturer's +website: + +http://www.phytec.de/produkt/system-on-modules/phyflex-imx-6/ + +Building U-Boot +------------------------------- + +$ make pfla02_defconfig +$ make + +This generates the artifacts SPL and u-boot.img. +The SOM can boot from NAND or from SD-Card, having the SPI-NOR +as second option. +The dip switch "SW3" on the board let choose the boot device. + +SW3_1(on), SW3_2(on), SW3_3(off): Boot first from SD, then try SPI +SW3_1(off), SW3_2(on), SW3_3(off): Boot from SPI diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c new file mode 100644 index 0000000..54e88c6 --- /dev/null +++ b/board/phytec/pfla02/pfla02.c @@ -0,0 +1,698 @@ +/* + * Copyright (C) 2017 Stefano Babic <sbabic(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/mach-imx/spi.h> +#include <linux/errno.h> +#include <asm/gpio.h> +#include <mmc.h> +#include <i2c.h> +#include <fsl_esdhc.h> +#include <nand.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/sys_proto.h> +#include <asm/sections.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + +#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14) +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define GREEN_LED IMX_GPIO_NR(2, 31) +#define RED_LED IMX_GPIO_NR(1, 30) +#define IMX6Q_DRIVE_STRENGTH 0x30 + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart4_pads[] = { + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const ecspi3_pads[] = { + IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const gpios_pads[] = { + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +#ifdef CONFIG_CMD_NAND +/* NAND */ +static iomux_v3_cfg_t const nfc_pads[] = { + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL)), +}; +#endif + +static struct i2c_pads_info i2c_pad_info = { + .scl = { + .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD, + .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD, + .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC3_BASE_ADDR, + .max_bus_width = 4}, + {.esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 4}, +}; + +#if !defined(CONFIG_SPL_BUILD) +static iomux_v3_cfg_t const usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; +#endif + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + ret = 1; + break; + case USDHC3_BASE_ADDR: + ret = 1; + break; + } + + return ret; +} + +#ifndef CONFIG_SPL_BUILD +int board_mmc_init(bd_t *bis) +{ + int ret; + int i; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart4_pads); +} + +static void setup_iomux_enet(void) +{ + SETUP_IOMUX_PADS(enet_pads); + + gpio_direction_output(ENET_PHY_RESET_GPIO, 0); + mdelay(10); + gpio_set_value(ENET_PHY_RESET_GPIO, 1); + mdelay(30); +} + +static void setup_spi(void) +{ + gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0"); + gpio_direction_output(IMX_GPIO_NR(4, 24), 1); + + SETUP_IOMUX_PADS(ecspi3_pads); + + enable_spi_clk(true, 2); +} + +static void setup_gpios(void) +{ + SETUP_IOMUX_PADS(gpios_pads); +} + +#ifdef CONFIG_CMD_NAND +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(nfc_pads); + + /* gate ENFC_CLK_ROOT clock first,before clk source switch */ + clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable ENFC_CLK_ROOT clock */ + setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +/* + * Board revision is coded in 4 GPIOs + */ +u32 get_board_rev(void) +{ + u32 rev; + int i; + + for (i = 0, rev = 0; i < 4; i++) + rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i); + + return 16 - rev; +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + if (bus != 2 || (cs != 0)) + return -EINVAL; + + return IMX_GPIO_NR(4, 24); +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + + setup_gpios(); + +#ifdef CONFIG_CMD_NAND + setup_gpmi_nand(); +#endif + return 0; +} + + +#ifdef CONFIG_CMD_BMODE +/* + * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 + * see Table 8-11 and Table 5-9 + * BOOT_CFG1[7] = 1 (boot from NAND) + * BOOT_CFG1[5] = 0 - raw NAND + * BOOT_CFG1[4] = 0 - default pad settings + * BOOT_CFG1[3:2] = 00 - devices = 1 + * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 + * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 + * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 + * BOOT_CFG2[0] = 0 - Reset time 12ms + */ +static const struct boot_mode board_boot_modes[] = { + /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ + {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)}, + {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ + char buf[10]; +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + snprintf(buf, sizeof(buf), "%d", get_board_rev()); + setenv("board_rev", buf); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include <asm/arch/mx6-ddr.h> +#include <spl.h> +#include <libfdt.h> + +#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11) +static void phyflex_err006282_workaround(void) +{ + /* + * Boards beginning with 1362.2 have the SD4_DAT3 pin connected + * to the CMIC. If this pin isn't toggled within 10s the boards + * reset. The pin is unconnected on older boards, so we do not + * need a check for older boards before applying this fixup. + */ + + gpio_direction_output(MX6_PHYFLEX_ERR006282, 0); + mdelay(2); + gpio_direction_output(MX6_PHYFLEX_ERR006282, 1); + mdelay(2); + gpio_set_value(MX6_PHYFLEX_ERR006282, 0); + + gpio_direction_input(MX6_PHYFLEX_ERR006282); +} + +static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_reset = 0x00000030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000030, + .dram_sdodt0 = 0x00000030, + .dram_sdodt1 = 0x00000030, + + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_sdqs4 = 0x00000028, + .dram_sdqs5 = 0x00000028, + .dram_sdqs6 = 0x00000028, + .dram_sdqs7 = 0x00000028, + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_dqm4 = 0x00000028, + .dram_dqm5 = 0x00000028, + .dram_dqm6 = 0x00000028, + .dram_dqm7 = 0x00000028, +}; + +static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6Q_DRIVE_STRENGTH, + .grp_ctlds = IMX6Q_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, + .grp_b4ds = 0x00000028, + .grp_b5ds = 0x00000028, + .grp_b6ds = 0x00000028, + .grp_b7ds = 0x00000028, +}; + +static const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00110011, + .p0_mpwldectrl1 = 0x00240024, + .p1_mpwldectrl0 = 0x00260038, + .p1_mpwldectrl1 = 0x002C0038, + .p0_mpdgctrl0 = 0x03400350, + .p0_mpdgctrl1 = 0x03440340, + .p1_mpdgctrl0 = 0x034C0354, + .p1_mpdgctrl1 = 0x035C033C, + .p0_mprddlctl = 0x322A2A2A, + .p1_mprddlctl = 0x302C2834, + .p0_mpwrdlctl = 0x34303834, + .p1_mpwrdlctl = 0x422A3E36, +}; + +/* Index in RAM Chip array */ +enum { + RAM_1GB, + RAM_2GB, + RAM_4GB +}; + +static struct mx6_ddr3_cfg mt41k_xx[] = { +/* MT41K64M16JT-125 (1Gb density) */ + { + .mem_speed = 1600, + .density = 1, + .width = 16, + .banks = 8, + .rowaddr = 13, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 1, + }, + +/* MT41K256M16JT-125 (2Gb density) */ + { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 1, + }, + +/* MT41K256M16JT-125 (4Gb density) */ + { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 1, + } +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 2, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, mem_ddr); +} + +int board_mmc_init(bd_t *bis) +{ + if (spl_boot_device() == BOOT_DEVICE_SPI) + printf("MMC SEtup, Boot SPI"); + + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + printf("Boot device %x\n", spl_boot_list[0]); + switch (spl_boot_list[0]) { + case BOOT_DEVICE_SPI: + spl_boot_list[1] = BOOT_DEVICE_UART; + break; + case BOOT_DEVICE_MMC1: + spl_boot_list[1] = BOOT_DEVICE_SPI; + spl_boot_list[2] = BOOT_DEVICE_UART; + break; + default: + printf("Boot device %x\n", spl_boot_list[0]); + } +} + +/* + * This is used because get_ram_size() does not + * take care of cache, resulting a wrong size + * pfla02 has just 1, 2 or 4 GB option + * Function checks for mirrors in the first CS + */ +#define RAM_TEST_PATTERN 0xaa5555aa +static unsigned int pfla02_detect_ramsize(void) +{ + u32 *p, *p1; + unsigned int offset = 512 * 1024 * 1024; + int i; + + for (i = 0; i < 2; i++) { + p = (u32 *)PHYS_SDRAM; + p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset); + + *p1 = 0; + *p = RAM_TEST_PATTERN; + + /* + * This is required to detect mirroring + * else we read back values from cache + */ + flush_dcache_all(); + + if (*p == *p1) + return i; + } + return RAM_4GB; +} + +void board_init_f(ulong dummy) +{ + unsigned int ramchip; +#ifdef CONFIG_CMD_NAND + /* Enable NAND */ + setup_gpmi_nand(); +#endif + + /* setup clock gating */ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* setup AXI */ + gpr_init(); + + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + setup_spi(); + + setup_gpios(); + + /* DDR initialization */ + spl_dram_init(&mt41k_xx[RAM_4GB]); + ramchip = pfla02_detect_ramsize(); + if (ramchip != RAM_4GB) + spl_dram_init(&mt41k_xx[ramchip]); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + phyflex_err006282_workaround(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig new file mode 100644 index 0000000..1729e5e --- /dev/null +++ b/configs/pfla02_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_PFLA02=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_HDMIDETECT=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL=y +CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_UBI=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_PARTITION_UUIDS is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +CONFIG_DM=y +CONFIG_MTD=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_THERMAL=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h new file mode 100644 index 0000000..2abbad2 --- /dev/null +++ b/include/configs/pfla02.h @@ -0,0 +1,183 @@ +/* + * Copyright (C) Stefano Babic <sbabic(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __PCM058_CONFIG_H +#define __PCM058_CONFIG_H + +#include <config_distro_defaults.h> + +#ifdef CONFIG_SPL +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) +#include "imx6_spl.h" +#endif + +#include "mx6_common.h" + +/* Thermal */ +#define CONFIG_IMX_THERMAL + +/* Serial */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONSOLE_DEV "ttymxc3" + +/* Early setup */ +#define CONFIG_DISPLAY_BOARDINFO_LATE + + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +/* Ethernet */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 3 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_KSZ9031 + +/* SPI Flash */ +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 0 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_NAND +/* Enable NAND support */ +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* Filesystem support */ +#define CONFIG_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:-(nand);" \ + "spi2.0:1024k(bootloader),64k(env1),64k(env2),-(rescue)" + +/* Various command support */ +#define CONFIG_RBTREE + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Environment organization */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_OFFSET (1024 * SZ_1K) +#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (0x1E0000) +#define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) +#endif + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addcons=setenv bootargs ${bootargs} " \ + "console=${console},${baudrate}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \ + "addmtd=run mtdnand;run mtdspi;" \ + "setenv bootargs ${bootargs} ${mtdparts}\0" \ + "mtdnand=setenv mtdparts mtdparts=gpmi-nand:" \ + "40m(Kernels),400m(root),-(nand)\0" \ + "mtdspi=setenv mtdparts ${mtdparts}" \ + "';spi2.0:1024k(bootloader)," \ + "64k(env1),64k(env2),-(rescue)'\0" \ + "bootcmd=if test -n ${rescue};" \ + "then run swupdate;fi;run nandboot;run swupdate\0" \ + "bootfile=uImage\0" \ + "bootimage=uImage\0" \ + "console=ttymxc3\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdt_file=pfla02.dtb\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "miscargs=panic=1 quiet\0" \ + "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \ + "mmcboot=if run mmcload;then " \ + "run mmcargs addcons addmisc;" \ + "bootm;fi\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p1\0" \ + "ubiroot=1\0" \ + "nandargs=setenv bootargs ubi.mtd=1 " \ + "root=ubi0:rootfs${ubiroot} rootfstype=ubifs\0" \ + "nandboot=run mtdnand;ubi part nand0,0;" \ + "ubi readvol ${kernel_addr_r} kernel${ubiroot};" \ + "run nandargs addip addcons addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \ + "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \ + "run nfsargs addip addcons addmtd addmisc;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "net_nfs_fit=tftp ${kernel_addr_r} ${board_name}/${fitfile};" \ + "run nfsargs addip addcons addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "nfsargs=setenv bootargs root=/dev/nfs" \ + " nfsroot=${serverip}:${nfsroot},v3 panic=1\0" \ + "swupdate=setenv bootargs root=/dev/ram;" \ + "run addip addcons addmtd addmisc;" \ + "sf probe;" \ + "sf read ${kernel_addr_r} 120000 600000;" \ + "sf read 14000000 730000 800000;" \ + "bootm ${kernel_addr_r} 14000000\0" + +#endif -- 2.7.4

1 0

[U-Boot] [PATCH 1/4] ARM: uniphier: remove SPL support for ARMv8 SoCs
by Masahiro Yamada 26 Jul '17

26 Jul '17

It has been a while since ARM Trusted Firmware supported UniPhier SoC family. U-Boot SPL was intended as a temporary loader that runs in secure world. It is a maintenance headache to support two different boot mechanisms. Secure firmware is realm of ARM Trusted Firmware and now U-Boot only serves as a non-secure boot loader for UniPhier ARMv8 SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/dts/uniphier-ld11-global.dts | 9 - arch/arm/dts/uniphier-ld11-ref.dts | 9 - arch/arm/dts/uniphier-ld11.dtsi | 3 - arch/arm/dts/uniphier-ld20-global.dts | 9 - arch/arm/dts/uniphier-ld20-ref.dts | 9 - arch/arm/dts/uniphier-ld20.dtsi | 3 - arch/arm/mach-uniphier/Kconfig | 27 +- arch/arm/mach-uniphier/arm64/Makefile | 9 - arch/arm/mach-uniphier/arm64/arm-cci500.c | 42 -- arch/arm/mach-uniphier/arm64/smp.S | 19 - arch/arm/mach-uniphier/arm64/smp_kick_cpus.c | 32 -- arch/arm/mach-uniphier/arm64/timer.c | 37 -- arch/arm/mach-uniphier/board_init.c | 9 - arch/arm/mach-uniphier/boards.c | 71 --- arch/arm/mach-uniphier/boot-device/Makefile | 4 - arch/arm/mach-uniphier/boot-device/spl_board.c | 262 ---------- arch/arm/mach-uniphier/clk/Makefile | 2 - arch/arm/mach-uniphier/clk/clk-dram-ld11.c | 25 - arch/arm/mach-uniphier/clk/clk-dram-ld20.c | 28 - arch/arm/mach-uniphier/clk/clk-early-ld11.c | 20 - arch/arm/mach-uniphier/clk/dpll-ld11.c | 16 - arch/arm/mach-uniphier/clk/dpll-ld20.c | 19 - arch/arm/mach-uniphier/dram/Makefile | 2 - arch/arm/mach-uniphier/dram/ddruqphy-regs.h | 79 --- arch/arm/mach-uniphier/dram/umc-ld11.c | 491 ----------------- arch/arm/mach-uniphier/dram/umc-ld20.c | 636 ----------------------- arch/arm/mach-uniphier/dram/umc64-regs.h | 85 --- arch/arm/mach-uniphier/init.h | 18 - arch/arm/mach-uniphier/spl_board_init.c | 26 - configs/uniphier_ld11_defconfig | 41 -- configs/uniphier_ld20_defconfig | 40 -- doc/README.uniphier | 6 +- drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 22 +- drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 22 +- drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 22 +- include/configs/uniphier.h | 36 +- 36 files changed, 45 insertions(+), 2145 deletions(-) delete mode 100644 arch/arm/mach-uniphier/arm64/arm-cci500.c delete mode 100644 arch/arm/mach-uniphier/arm64/smp.S delete mode 100644 arch/arm/mach-uniphier/arm64/smp_kick_cpus.c delete mode 100644 arch/arm/mach-uniphier/arm64/timer.c delete mode 100644 arch/arm/mach-uniphier/boot-device/spl_board.c delete mode 100644 arch/arm/mach-uniphier/clk/clk-dram-ld11.c delete mode 100644 arch/arm/mach-uniphier/clk/clk-dram-ld20.c delete mode 100644 arch/arm/mach-uniphier/clk/clk-early-ld11.c delete mode 100644 arch/arm/mach-uniphier/clk/dpll-ld11.c delete mode 100644 arch/arm/mach-uniphier/clk/dpll-ld20.c delete mode 100644 arch/arm/mach-uniphier/dram/ddruqphy-regs.h delete mode 100644 arch/arm/mach-uniphier/dram/umc-ld11.c delete mode 100644 arch/arm/mach-uniphier/dram/umc-ld20.c delete mode 100644 arch/arm/mach-uniphier/dram/umc64-regs.h delete mode 100644 configs/uniphier_ld11_defconfig delete mode 100644 configs/uniphier_ld20_defconfig diff --git a/arch/arm/dts/uniphier-ld11-global.dts b/arch/arm/dts/uniphier-ld11-global.dts index 2ed13606b505..7a650a02486a 100644 --- a/arch/arm/dts/uniphier-ld11-global.dts +++ b/arch/arm/dts/uniphier-ld11-global.dts @@ -68,12 +68,3 @@ &usb2 { status = "okay"; }; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ld11-ref.dts b/arch/arm/dts/uniphier-ld11-ref.dts index 4bdf1121d678..cc8ebe34c27c 100644 --- a/arch/arm/dts/uniphier-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ld11-ref.dts @@ -62,12 +62,3 @@ &usb2 { status = "okay"; }; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index 75dfd1ff3b6b..74f8f721a888 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -109,7 +109,6 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; - u-boot,dm-pre-reloc; serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; @@ -343,11 +342,9 @@ compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc; pinctrl: pinctrl { compatible = "socionext,uniphier-ld11-pinctrl"; - u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/dts/uniphier-ld20-global.dts b/arch/arm/dts/uniphier-ld20-global.dts index 535c0eeed545..9f620d4101b5 100644 --- a/arch/arm/dts/uniphier-ld20-global.dts +++ b/arch/arm/dts/uniphier-ld20-global.dts @@ -50,12 +50,3 @@ &i2c0 { status = "okay"; }; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts index 2bcab967f7f8..494166aee24c 100644 --- a/arch/arm/dts/uniphier-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ld20-ref.dts @@ -50,12 +50,3 @@ &i2c0 { status = "okay"; }; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index ab031f2cab58..927340fa48d2 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -178,7 +178,6 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; - u-boot,dm-pre-reloc; serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; @@ -378,11 +377,9 @@ compatible = "socionext,uniphier-ld20-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc; pinctrl: pinctrl { compatible = "socionext,uniphier-ld20-pinctrl"; - u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 5739325da71b..1aed55a539bd 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -10,14 +10,6 @@ config ARCH_UNIPHIER_32BIT select ARMV7_NONSEC select ARCH_SUPPORT_PSCI -config ARCH_UNIPHIER_64BIT - bool - select ARM64 - select CMD_UNZIP - select SPL_SEPARATE_BSS if SPL - select ARMV8_MULTIENTRY if SPL - select ARMV8_SPIN_TABLE if SPL - choice prompt "UniPhier SoC select" default ARCH_UNIPHIER_PRO4 @@ -38,18 +30,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B bool "UniPhier Pro5/PXs2/LD6b SoCs" select ARCH_UNIPHIER_32BIT -config ARCH_UNIPHIER_LD11_SINGLE - bool "UniPhier LD11 SoC" - select ARCH_UNIPHIER_64BIT - -config ARCH_UNIPHIER_LD20_SINGLE - bool "UniPhier LD20 SoC" - select ARCH_UNIPHIER_64BIT - config ARCH_UNIPHIER_V8_MULTI bool "UniPhier V8 SoCs" depends on !SPL - select ARCH_UNIPHIER_64BIT + select ARM64 + select CMD_UNZIP endchoice @@ -79,13 +64,13 @@ config ARCH_UNIPHIER_LD6B default y config ARCH_UNIPHIER_LD11 - bool "Enable UniPhier LD11 SoC support" if ARCH_UNIPHIER_V8_MULTI - depends on ARCH_UNIPHIER_LD11_SINGLE || ARCH_UNIPHIER_V8_MULTI + bool "Enable UniPhier LD11 SoC support" + depends on ARCH_UNIPHIER_V8_MULTI default y config ARCH_UNIPHIER_LD20 - bool "Enable UniPhier LD20 SoC support" if ARCH_UNIPHIER_V8_MULTI - depends on ARCH_UNIPHIER_LD20_SINGLE || ARCH_UNIPHIER_V8_MULTI + bool "Enable UniPhier LD20 SoC support" + depends on ARCH_UNIPHIER_V8_MULTI select OF_BOARD_SETUP default y diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile index 06072f23bd8c..12d91e0491e8 100644 --- a/arch/arm/mach-uniphier/arm64/Makefile +++ b/arch/arm/mach-uniphier/arm64/Makefile @@ -2,14 +2,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD -obj-y += timer.o -else obj-y += mem_map.o -ifdef CONFIG_ARMV8_MULTIENTRY -obj-y += smp.o smp_kick_cpus.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o -else obj-$(CONFIG_ARCH_UNIPHIER_LD20) += lowlevel_init.o -endif -endif diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c deleted file mode 100644 index bf0fad459bbd..000000000000 --- a/arch/arm/mach-uniphier/arm64/arm-cci500.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/bitops.h> -#include <linux/io.h> -#include <linux/sizes.h> - -#include "../init.h" - -#define CCI500_BASE 0x5FD00000 -#define CCI500_SLAVE_OFFSET 0x1000 - -#define CCI500_SNOOP_CTRL -#define CCI500_SNOOP_CTRL_EN_DVM BIT(1) -#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0) - -void cci500_init(unsigned int nr_slaves) -{ - unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET; - int i; - - for (i = 0; i < nr_slaves; i++) { - void __iomem *base; - u32 tmp; - - base = ioremap(slave_base, SZ_4K); - - tmp = readl(base); - tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP; - writel(tmp, base); - - iounmap(base); - - slave_base += CCI500_SLAVE_OFFSET; - } -} diff --git a/arch/arm/mach-uniphier/arm64/smp.S b/arch/arm/mach-uniphier/arm64/smp.S deleted file mode 100644 index 9348ec97c425..000000000000 --- a/arch/arm/mach-uniphier/arm64/smp.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro(a)socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/linkage.h> - -ENTRY(uniphier_smp_setup) - mrs x0, s3_1_c15_c2_1 /* CPUECTLR_EL1 */ - orr x0, x0, #(1 << 6) /* SMPEN */ - msr s3_1_c15_c2_1, x0 - ret -ENDPROC(uniphier_smp_setup) - -ENTRY(uniphier_secondary_startup) - bl uniphier_smp_setup - b _start -ENDPROC(uniphier_secondary_startup) diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c deleted file mode 100644 index 8e5b198c96ce..000000000000 --- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> -#include <linux/sizes.h> - -#include "../init.h" - -#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200 - -void uniphier_smp_setup(void); -void uniphier_secondary_startup(void); - -void uniphier_smp_kick_all_cpus(void) -{ - void __iomem *rom_boot_rsv0; - - rom_boot_rsv0 = ioremap(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8); - - writeq((u64)uniphier_secondary_startup, rom_boot_rsv0); - - iounmap(rom_boot_rsv0); - - uniphier_smp_setup(); - - asm("dsb ishst\n" /* Ensure the write to ROM_RSV0 is visible */ - "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ -} diff --git a/arch/arm/mach-uniphier/arm64/timer.c b/arch/arm/mach-uniphier/arm64/timer.c deleted file mode 100644 index c10903ae58fd..000000000000 --- a/arch/arm/mach-uniphier/arm64/timer.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/bitops.h> -#include <linux/io.h> -#include <linux/sizes.h> - -#define CNT_CONTROL_BASE 0x60E00000 - -#define CNTCR 0x000 -#define CNTCR_EN BIT(0) - -/* setup ARMv8 Generic Timer */ -int timer_init(void) -{ - void __iomem *base; - u32 tmp; - - base = ioremap(CNT_CONTROL_BASE, SZ_4K); - - /* - * Note: - * In a system that implements both Secure and Non-secure states, - * this register is only writable in Secure state. - */ - tmp = readl(base + CNTCR); - tmp |= CNTCR_EN; - writel(tmp, base + CNTCR); - - iounmap(base); - - return 0; -} diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index ca910f6d7254..884bc67654d4 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -73,9 +73,6 @@ static void uniphier_ld20_misc_init(void) writel(0x0000b500, 0x6184e024); writel(0x00000001, 0x6184e000); } -#ifdef CONFIG_ARMV8_MULTIENTRY - cci500_init(2); -#endif } #endif @@ -230,12 +227,6 @@ int board_init(void) support_card_late_init(); - led_puts("U6"); - -#ifdef CONFIG_ARMV8_MULTIENTRY - uniphier_smp_kick_all_cpus(); -#endif - led_puts("Uboo"); return 0; diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index e3b933502230..78de256a01e5 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -140,69 +140,6 @@ static const struct uniphier_board_data uniphier_ld6b_data = { }; #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD11) -static const struct uniphier_board_data uniphier_ld11_data = { - .dram_freq = 1600, - .dram_ch[0] = { - .size = 0x20000000, - .width = 16, - }, - .dram_ch[1] = { - .size = 0x20000000, - .width = 16, - }, -}; -#endif - -#if defined(CONFIG_ARCH_UNIPHIER_LD20) -static const struct uniphier_board_data uniphier_ld20_ref_data = { - .dram_freq = 1866, - .dram_ch[0] = { - .size = 0x40000000, - .width = 32, - }, - .dram_ch[1] = { - .size = 0x40000000, - .width = 32, - }, - .dram_ch[2] = { - .size = 0x40000000, - .width = 32, - }, - .flags = UNIPHIER_BD_BOARD_LD20_REF, -}; - -static const struct uniphier_board_data uniphier_ld20_data = { - .dram_freq = 1866, - .dram_ch[0] = { - .size = 0x40000000, - .width = 32, - }, - .dram_ch[1] = { - .size = 0x40000000, - .width = 32, - }, - .dram_ch[2] = { - .size = 0x40000000, - .width = 32, - }, - .flags = UNIPHIER_BD_BOARD_LD20_GLOBAL, -}; - -static const struct uniphier_board_data uniphier_ld21_data = { - .dram_freq = 1866, - .dram_ch[0] = { - .size = 0x20000000, - .width = 32, - }, - .dram_ch[1] = { - .size = 0x40000000, - .width = 32, - }, - .flags = UNIPHIER_BD_DRAM_SPARSE | UNIPHIER_BD_BOARD_LD21_GLOBAL, -}; -#endif - struct uniphier_board_id { const char *compatible; const struct uniphier_board_data *param; @@ -232,14 +169,6 @@ static const struct uniphier_board_id uniphier_boards[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD6B) { "socionext,uniphier-ld6b", &uniphier_ld6b_data, }, #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD11) - { "socionext,uniphier-ld11", &uniphier_ld11_data, }, -#endif -#if defined(CONFIG_ARCH_UNIPHIER_LD20) - { "socionext,uniphier-ld21", &uniphier_ld21_data, }, - { "socionext,uniphier-ld20-ref", &uniphier_ld20_ref_data, }, - { "socionext,uniphier-ld20", &uniphier_ld20_data, }, -#endif }; const struct uniphier_board_data *uniphier_get_board_param(void) diff --git a/arch/arm/mach-uniphier/boot-device/Makefile b/arch/arm/mach-uniphier/boot-device/Makefile index abb58a729aa3..b35729213032 100644 --- a/arch/arm/mach-uniphier/boot-device/Makefile +++ b/arch/arm/mach-uniphier/boot-device/Makefile @@ -14,7 +14,3 @@ obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-device-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-device-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-device-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += boot-device-pxs3.o - -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE) += spl_board.o -endif diff --git a/arch/arm/mach-uniphier/boot-device/spl_board.c b/arch/arm/mach-uniphier/boot-device/spl_board.c deleted file mode 100644 index bd47ac874b03..000000000000 --- a/arch/arm/mach-uniphier/boot-device/spl_board.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright (C) 2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <spl.h> -#include <linux/bitops.h> -#include <linux/compat.h> -#include <linux/io.h> -#include <asm/processor.h> - -#include "../soc-info.h" - -#define MMC_CMD_SWITCH 6 -#define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_READ_MULTIPLE_BLOCK 18 - -#define EXT_CSD_PART_CONF 179 /* R/W */ - -#define MMC_RSP_PRESENT BIT(0) -#define MMC_RSP_136 BIT(1) /* 136 bit response */ -#define MMC_RSP_CRC BIT(2) /* expect valid crc */ -#define MMC_RSP_BUSY BIT(3) /* card may send busy */ -#define MMC_RSP_OPCODE BIT(4) /* response contains opcode */ - -#define MMC_RSP_NONE (0) -#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) -#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \ - MMC_RSP_BUSY) -#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC) -#define MMC_RSP_R3 (MMC_RSP_PRESENT) -#define MMC_RSP_R4 (MMC_RSP_PRESENT) -#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) -#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) -#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) - -#define SDHCI_DMA_ADDRESS 0x00 -#define SDHCI_BLOCK_SIZE 0x04 -#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF)) -#define SDHCI_BLOCK_COUNT 0x06 -#define SDHCI_ARGUMENT 0x08 -#define SDHCI_TRANSFER_MODE 0x0C -#define SDHCI_TRNS_DMA BIT(0) -#define SDHCI_TRNS_BLK_CNT_EN BIT(1) -#define SDHCI_TRNS_ACMD12 BIT(2) -#define SDHCI_TRNS_READ BIT(4) -#define SDHCI_TRNS_MULTI BIT(5) -#define SDHCI_COMMAND 0x0E -#define SDHCI_CMD_RESP_MASK 0x03 -#define SDHCI_CMD_CRC 0x08 -#define SDHCI_CMD_INDEX 0x10 -#define SDHCI_CMD_DATA 0x20 -#define SDHCI_CMD_ABORTCMD 0xC0 -#define SDHCI_CMD_RESP_NONE 0x00 -#define SDHCI_CMD_RESP_LONG 0x01 -#define SDHCI_CMD_RESP_SHORT 0x02 -#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 -#define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff)) -#define SDHCI_RESPONSE 0x10 -#define SDHCI_HOST_CONTROL 0x28 -#define SDHCI_CTRL_DMA_MASK 0x18 -#define SDHCI_CTRL_SDMA 0x00 -#define SDHCI_BLOCK_GAP_CONTROL 0x2A -#define SDHCI_SOFTWARE_RESET 0x2F -#define SDHCI_RESET_CMD 0x02 -#define SDHCI_RESET_DATA 0x04 -#define SDHCI_INT_STATUS 0x30 -#define SDHCI_INT_RESPONSE BIT(0) -#define SDHCI_INT_DATA_END BIT(1) -#define SDHCI_INT_ERROR BIT(15) -#define SDHCI_SIGNAL_ENABLE 0x38 - -/* RCA assigned by Boot ROM */ -#define UNIPHIER_EMMC_RCA 0x1000 - -struct uniphier_mmc_cmd { - unsigned int cmdidx; - unsigned int resp_type; - unsigned int cmdarg; - unsigned int is_data; -}; - -static int uniphier_emmc_send_cmd(void __iomem *host_base, - struct uniphier_mmc_cmd *cmd) -{ - u32 mode = 0; - u32 mask = SDHCI_INT_RESPONSE; - u32 stat, flags; - - writel(U32_MAX, host_base + SDHCI_INT_STATUS); - writel(0, host_base + SDHCI_SIGNAL_ENABLE); - writel(cmd->cmdarg, host_base + SDHCI_ARGUMENT); - - if (cmd->is_data) - mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN | - SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ | - SDHCI_TRNS_MULTI; - - writew(mode, host_base + SDHCI_TRANSFER_MODE); - - if (!(cmd->resp_type & MMC_RSP_PRESENT)) - flags = SDHCI_CMD_RESP_NONE; - else if (cmd->resp_type & MMC_RSP_136) - flags = SDHCI_CMD_RESP_LONG; - else if (cmd->resp_type & MMC_RSP_BUSY) - flags = SDHCI_CMD_RESP_SHORT_BUSY; - else - flags = SDHCI_CMD_RESP_SHORT; - - if (cmd->resp_type & MMC_RSP_CRC) - flags |= SDHCI_CMD_CRC; - if (cmd->resp_type & MMC_RSP_OPCODE) - flags |= SDHCI_CMD_INDEX; - if (cmd->is_data) - flags |= SDHCI_CMD_DATA; - - if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data) - mask |= SDHCI_INT_DATA_END; - - writew(SDHCI_MAKE_CMD(cmd->cmdidx, flags), host_base + SDHCI_COMMAND); - - do { - stat = readl(host_base + SDHCI_INT_STATUS); - if (stat & SDHCI_INT_ERROR) - return -EIO; - - } while ((stat & mask) != mask); - - return 0; -} - -static int uniphier_emmc_switch_part(void __iomem *host_base, int part_num) -{ - struct uniphier_mmc_cmd cmd = {}; - - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; - cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24); - - return uniphier_emmc_send_cmd(host_base, &cmd); -} - -static int uniphier_emmc_is_over_2gb(void __iomem *host_base) -{ - struct uniphier_mmc_cmd cmd = {}; - u32 csd40, csd72; /* CSD[71:40], CSD[103:72] */ - int ret; - - cmd.cmdidx = MMC_CMD_SEND_CSD; - cmd.resp_type = MMC_RSP_R2; - cmd.cmdarg = UNIPHIER_EMMC_RCA << 16; - - ret = uniphier_emmc_send_cmd(host_base, &cmd); - if (ret) - return ret; - - csd40 = readl(host_base + SDHCI_RESPONSE + 4); - csd72 = readl(host_base + SDHCI_RESPONSE + 8); - - return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3); -} - -static int uniphier_emmc_load_image(void __iomem *host_base, u32 dev_addr, - unsigned long load_addr, u32 block_cnt) -{ - struct uniphier_mmc_cmd cmd = {}; - u8 tmp; - - WARN_ON(load_addr >> 32); - - writel(load_addr, host_base + SDHCI_DMA_ADDRESS); - writew(SDHCI_MAKE_BLKSZ(7, 512), host_base + SDHCI_BLOCK_SIZE); - writew(block_cnt, host_base + SDHCI_BLOCK_COUNT); - - tmp = readb(host_base + SDHCI_HOST_CONTROL); - tmp &= ~SDHCI_CTRL_DMA_MASK; - tmp |= SDHCI_CTRL_SDMA; - writeb(tmp, host_base + SDHCI_HOST_CONTROL); - - tmp = readb(host_base + SDHCI_BLOCK_GAP_CONTROL); - tmp &= ~1; /* clear Stop At Block Gap Request */ - writeb(tmp, host_base + SDHCI_BLOCK_GAP_CONTROL); - - cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; - cmd.resp_type = MMC_RSP_R1; - cmd.cmdarg = dev_addr; - cmd.is_data = 1; - - return uniphier_emmc_send_cmd(host_base, &cmd); -} - -static int spl_board_load_image(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev) -{ - u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; - void __iomem *host_base = (void __iomem *)0x5a000200; - struct uniphier_mmc_cmd cmd = {}; - int ret; - - /* - * deselect card before SEND_CSD command. - * Do not check the return code. It fails, but it is OK. - */ - cmd.cmdidx = MMC_CMD_SELECT_CARD; - cmd.resp_type = MMC_RSP_R1; - - uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */ - - /* reset CMD Line */ - writeb(SDHCI_RESET_CMD | SDHCI_RESET_DATA, - host_base + SDHCI_SOFTWARE_RESET); - while (readb(host_base + SDHCI_SOFTWARE_RESET)) - cpu_relax(); - - ret = uniphier_emmc_is_over_2gb(host_base); - if (ret < 0) - return ret; - if (ret) { - debug("card is block addressing\n"); - } else { - debug("card is byte addressing\n"); - dev_addr *= 512; - } - - cmd.cmdarg = UNIPHIER_EMMC_RCA << 16; - - /* select card again */ - ret = uniphier_emmc_send_cmd(host_base, &cmd); - if (ret) - printf("failed to select card\n"); - - /* Switch to Boot Partition 1 */ - ret = uniphier_emmc_switch_part(host_base, 1); - if (ret) - printf("failed to switch partition\n"); - - ret = uniphier_emmc_load_image(host_base, dev_addr, - CONFIG_SYS_TEXT_BASE, 1); - if (ret) { - printf("failed to load image\n"); - return ret; - } - - ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE); - if (ret) - return ret; - - ret = uniphier_emmc_load_image(host_base, dev_addr, - spl_image->load_addr, - spl_image->size / 512); - if (ret) { - printf("failed to load image\n"); - return ret; - } - - return 0; -} -SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image); diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index dad035d03a88..1680dddd6e68 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -11,8 +11,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-sld3.o clk-dram-sld3.o dpll-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-sld3.o clk-dram-pro5.o dpll-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-early-ld11.o clk-dram-ld11.o dpll-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-early-ld11.o clk-dram-ld20.o dpll-ld20.o else diff --git a/arch/arm/mach-uniphier/clk/clk-dram-ld11.c b/arch/arm/mach-uniphier/clk/clk-dram-ld11.c deleted file mode 100644 index 593e11a29282..000000000000 --- a/arch/arm/mach-uniphier/clk/clk-dram-ld11.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2016-2017 Socionext Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sc64-regs.h" - -void uniphier_ld11_dram_clk_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL7); - tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30; - writel(tmp, SC_RSTCTRL7); - - /* provide clocks */ - tmp = readl(SC_CLKCTRL7); - tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30; - writel(tmp, SC_CLKCTRL7); -} diff --git a/arch/arm/mach-uniphier/clk/clk-dram-ld20.c b/arch/arm/mach-uniphier/clk/clk-dram-ld20.c deleted file mode 100644 index 62e5acd64d24..000000000000 --- a/arch/arm/mach-uniphier/clk/clk-dram-ld20.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2016-2017 Socionext Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sc64-regs.h" - -void uniphier_ld20_dram_clk_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL7); - tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 | - SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 | - SC_RSTCTRL7_UMC30; - writel(tmp, SC_RSTCTRL7); - - /* provide clocks */ - tmp = readl(SC_CLKCTRL7); - tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 | - SC_CLKCTRL7_UMC30; - writel(tmp, SC_CLKCTRL7); -} diff --git a/arch/arm/mach-uniphier/clk/clk-early-ld11.c b/arch/arm/mach-uniphier/clk/clk-early-ld11.c deleted file mode 100644 index bb6f7a47cb0a..000000000000 --- a/arch/arm/mach-uniphier/clk/clk-early-ld11.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2016-2017 Socionext Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sc64-regs.h" - -void uniphier_ld11_early_clk_init(void) -{ - u32 tmp; - - /* provide clocks */ - tmp = readl(SC_CLKCTRL4); - tmp |= SC_CLKCTRL4_PERI; - writel(tmp, SC_CLKCTRL4); -} diff --git a/arch/arm/mach-uniphier/clk/dpll-ld11.c b/arch/arm/mach-uniphier/clk/dpll-ld11.c deleted file mode 100644 index 7f0677c0d4a6..000000000000 --- a/arch/arm/mach-uniphier/clk/dpll-ld11.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" -#include "../sc64-regs.h" -#include "pll.h" - -int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd) -{ - uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); - - return 0; -} diff --git a/arch/arm/mach-uniphier/clk/dpll-ld20.c b/arch/arm/mach-uniphier/clk/dpll-ld20.c deleted file mode 100644 index 86e99c4d1f0e..000000000000 --- a/arch/arm/mach-uniphier/clk/dpll-ld20.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" -#include "../sc64-regs.h" -#include "pll.h" - -int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd) -{ - uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); - uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); - uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); - - return 0; -} diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index 2ce6199988a4..1da33f6d80a1 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -14,8 +14,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \ obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += umc-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += umc-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o else diff --git a/arch/arm/mach-uniphier/dram/ddruqphy-regs.h b/arch/arm/mach-uniphier/dram/ddruqphy-regs.h deleted file mode 100644 index e496af5ba846..000000000000 --- a/arch/arm/mach-uniphier/dram/ddruqphy-regs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DDRUQPHY_REGS_H -#define _DDRUQPHY_REGS_H - -#include <linux/bitops.h> - -#define PHY_REG_SHIFT 2 -#define PHY_SLV_DLY_WIDTH 6 -#define PHY_BITLVL_DLY_WIDTH 6 -#define PHY_MAS_DLY_WIDTH 8 - -#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT)) -#define PHY_SCL_START_GO_DONE BIT(28) -#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT)) -#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT)) -#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT)) -#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT)) -#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT)) -#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT)) -#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT)) -#define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0) -#define PHY_DLL_RECALIB_INCR BIT(27) -#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT)) -#define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0) -#define PHY_DLL_ADRCTRL_INCR BIT(9) -#define PHY_DLL_ADRCTRL_MDL_SHIFT 24 -#define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \ - PHY_DLL_ADRCTRL_MDL_SHIFT) -#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT)) -#define PHY_LANE_SEL_LANE_SHIFT 0 -#define PHY_LANE_SEL_LANE_WIDTH 8 -#define PHY_LANE_SEL_BIT_SHIFT 8 -#define PHY_LANE_SEL_BIT_WIDTH 4 -#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT)) -#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT)) -#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT)) -#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT)) -#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT)) -#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT)) -#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT)) -#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT)) -#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT)) -#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT)) -#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT)) -#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT)) -#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT)) -#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT)) -#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT)) -#define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \ - GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0) -#define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \ - BIT(PHY_BITLVL_DLY_WIDTH) -#define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \ - BIT(PHY_BITLVL_DLY_WIDTH + 1) -#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT)) -#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT)) -#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \ - GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0) -#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \ - BIT(PHY_BITLVL_DLY_WIDTH) -#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \ - BIT(PHY_BITLVL_DLY_WIDTH + 1) -#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT)) -#define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0) -#define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1) -#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT)) -#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT)) -#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT)) -#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT)) -#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT)) -#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT)) -#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT)) - -#endif /* _DDRUQPHY_REGS_H */ diff --git a/arch/arm/mach-uniphier/dram/umc-ld11.c b/arch/arm/mach-uniphier/dram/umc-ld11.c deleted file mode 100644 index 9e2021a627e5..000000000000 --- a/arch/arm/mach-uniphier/dram/umc-ld11.c +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - */ - -#include <common.h> -#include <linux/io.h> -#include <linux/sizes.h> -#include <asm/processor.h> - -#include "../init.h" -#include "ddrphy-regs.h" -#include "umc64-regs.h" - -#define DDR_FREQ 1600 - -#define DRAM_CH_NR 2 -#define RANK_BLOCKS_TR 2 - -enum dram_freq { - DRAM_FREQ_1600M, - DRAM_FREQ_NR, -}; - -enum dram_size { - DRAM_SZ_256M, - DRAM_SZ_512M, - DRAM_SZ_NR, -}; - -/* PHY */ -static const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} }; -static const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} }; -static const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} }; -static const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} }; -static const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} }; - -/* Register address */ -#define PHY_ZQ0CR1 0x00000184 -#define PHY_ZQ1CR1 0x00000194 -#define PHY_ZQ2CR1 0x000001A4 -#define PHY_DX0GCR 0x000001C0 -#define PHY_DX0GTR 0x000001F0 -#define PHY_DX1GCR 0x00000200 -#define PHY_DX1GTR 0x00000230 -#define PHY_DX2GCR 0x00000240 -#define PHY_DX2GTR 0x00000270 -#define PHY_DX3GCR 0x00000280 -#define PHY_DX3GTR 0x000002B0 - -#define PHY_DXMDLR(dx) (0x000001EC + 0x40 * (dx)) -#define PHY_DXLCDLR0(dx) (0x000001E0 + 0x40 * (dx)) -#define PHY_DXLCDLR1(dx) (0x000001E4 + 0x40 * (dx)) -#define PHY_DXLCDLR2(dx) (0x000001E8 + 0x40 * (dx)) -#define PHY_DXBDLR1(dx) (0x000001D0 + 0x40 * (dx)) -#define PHY_DXBDLR2(dx) (0x000001D4 + 0x40 * (dx)) - -/* MASK */ -#define PHY_ACBD_MASK 0x00FC0000 -#define PHY_CK0BD_MASK 0x0000003F -#define PHY_CK1BD_MASK 0x00000FC0 -#define PHY_IPRD_MASK 0x000000FF -#define PHY_WLD_MASK(rank) (0xFF << (8 * (rank))) -#define PHY_DQSGD_MASK(rank) (0xFF << (8 * (rank))) -#define PHY_DQSGX_MASK BIT(6) -#define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */ -#define PHY_DSDQOE_MASK 0x00000FFF - -static void ddrphy_maskwritel(u32 data, u32 mask, void __iomem *addr) -{ - u32 value; - - value = (readl(addr) & ~(mask)) | (data & mask); - writel(value, addr); -} - -static u32 ddrphy_maskreadl(u32 mask, void __iomem *addr) -{ - return readl(addr) & mask; -} - -/* step of 0.5T for PUB-byte */ -static u8 ddrphy_get_mdl(int dx, void __iomem *phy_base) -{ - return ddrphy_maskreadl(PHY_IPRD_MASK, phy_base + PHY_DXMDLR(dx)); -} - -/* Calculating step for PUB-byte */ -static int ddrphy_hpstep(int delay, int dx, void __iomem *phy_base) -{ - return delay * ddrphy_get_mdl(dx, phy_base) * DDR_FREQ / 1000000; -} - -static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable) -{ - u32 tmp; - - tmp = readl(phy_base + PHY_PGCR1); - - if (enable) - tmp &= ~PHY_PGCR1_INHVT; - else - tmp |= PHY_PGCR1_INHVT; - - writel(tmp, phy_base + PHY_PGCR1); - - if (!enable) { - while (!(readl(phy_base + PHY_PGSR1) & PHY_PGSR1_VTSTOP)) - cpu_relax(); - } -} - -static void ddrphy_set_ckoffset_qoffset(int delay_ckoffset0, int delay_ckoffset1, - int delay_qoffset, int enable, - void __iomem *phy_base) -{ - u8 ck_step0, ck_step1; /* ckoffset_step for clock */ - u8 q_step; /* qoffset_step for clock */ - int dx; - - dx = 2; /* use dx2 in sLD11 */ - - ck_step0 = ddrphy_hpstep(delay_ckoffset0, dx, phy_base); /* CK-Offset */ - ck_step1 = ddrphy_hpstep(delay_ckoffset1, dx, phy_base); /* CK-Offset */ - q_step = ddrphy_hpstep(delay_qoffset, dx, phy_base); /* Q-Offset */ - - ddrphy_vt_ctrl(phy_base, 0); - - /* Q->[23:18], CK1->[11:6], CK0->bit[5:0] */ - if (enable == 1) - ddrphy_maskwritel((q_step << 18) + (ck_step1 << 6) + ck_step0, - PHY_ACBD_MASK | PHY_CK1BD_MASK | PHY_CK0BD_MASK, - phy_base + PHY_ACBDLR); - - ddrphy_vt_ctrl(phy_base, 1); -} - -static void ddrphy_set_wl_delay_dx(int dx, int r0_delay, int r1_delay, - int enable, void __iomem *phy_base) -{ - int rank; - int delay_wl[4]; - u32 wl_mask = 0; /* WriteLeveling's Mask */ - u32 wl_value = 0; /* WriteLeveling's Value */ - - delay_wl[0] = r0_delay & 0xfff; - delay_wl[1] = r1_delay & 0xfff; - delay_wl[2] = 0; - delay_wl[3] = 0; - - ddrphy_vt_ctrl(phy_base, 0); - - for (rank = 0; rank < 4; rank++) { - wl_mask |= PHY_WLD_MASK(rank); - /* WriteLeveling's delay */ - wl_value |= ddrphy_hpstep(delay_wl[rank], dx, phy_base) << (8 * rank); - } - - if (enable == 1) - ddrphy_maskwritel(wl_value, wl_mask, phy_base + PHY_DXLCDLR0(dx)); - - ddrphy_vt_ctrl(phy_base, 1); -} - -static void ddrphy_set_dqsg_delay_dx(int dx, int r0_delay, int r1_delay, - int enable, void __iomem *phy_base) -{ - int rank; - int delay_dqsg[4]; - u32 dqsg_mask = 0; /* DQSGating_LCDL_delay's Mask */ - u32 dqsg_value = 0; /* DQSGating_LCDL_delay's Value */ - - delay_dqsg[0] = r0_delay; - delay_dqsg[1] = r1_delay; - delay_dqsg[2] = 0; - delay_dqsg[3] = 0; - - ddrphy_vt_ctrl(phy_base, 0); - - for (rank = 0; rank < 4; rank++) { - dqsg_mask |= PHY_DQSGD_MASK(rank); - /* DQSGating's delay */ - dqsg_value |= ddrphy_hpstep(delay_dqsg[rank], dx, phy_base) << (8 * rank); - } - - if (enable == 1) - ddrphy_maskwritel(dqsg_value, dqsg_mask, phy_base + PHY_DXLCDLR2(dx)); - - ddrphy_vt_ctrl(phy_base, 1); -} - -static void ddrphy_set_dswb_delay_dx(int dx, int delay, int enable, void __iomem *phy_base) -{ - u8 dswb_step; - - ddrphy_vt_ctrl(phy_base, 0); - - dswb_step = ddrphy_hpstep(delay, dx, phy_base); /* DQS-BDL's delay */ - - if (enable == 1) - ddrphy_maskwritel(dswb_step << 24, PHY_DSWBD_MASK, phy_base + PHY_DXBDLR1(dx)); - - ddrphy_vt_ctrl(phy_base, 1); -} - -static void ddrphy_set_oe_delay_dx(int dx, int dqs_delay, int dq_delay, - int enable, void __iomem *phy_base) -{ - u8 dqs_oe_step, dq_oe_step; - u32 wdata; - - ddrphy_vt_ctrl(phy_base, 0); - - /* OE(DQS,DQ) */ - dqs_oe_step = ddrphy_hpstep(dqs_delay, dx, phy_base); /* DQS-oe's delay */ - dq_oe_step = ddrphy_hpstep(dq_delay, dx, phy_base); /* DQ-oe's delay */ - wdata = ((dq_oe_step<<6) + dqs_oe_step) & 0xFFF; - - if (enable == 1) - ddrphy_maskwritel(wdata, PHY_DSDQOE_MASK, phy_base + PHY_DXBDLR2(dx)); - - ddrphy_vt_ctrl(phy_base, 1); -} - -static void ddrphy_ext_dqsgt(void __iomem *phy_base) -{ - /* Extend DQSGating_window min:+1T max:+1T */ - ddrphy_maskwritel(PHY_DQSGX_MASK, PHY_DQSGX_MASK, phy_base + PHY_DSGCR); -} - -static void ddrphy_shift_tof_hws(void __iomem *phy_base, const int shift[][2]) -{ - int dx, block, byte; - u32 lcdlr1, wdqd; - - ddrphy_vt_ctrl(phy_base, 0); - - for (block = 0; block < RANK_BLOCKS_TR; block++) { - for (byte = 0; byte < 2; byte++) { - dx = block * 2 + byte; - lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx)); - wdqd = lcdlr1 & 0xff; - wdqd = clamp(wdqd + ddrphy_hpstep(shift[block][byte], dx, phy_base), - 0U, 0xffU); - lcdlr1 = (lcdlr1 & ~0xff) | wdqd; - writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx)); - readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */ - } - } - - ddrphy_vt_ctrl(phy_base, 1); -} - -static void ddrphy_shift_rof_hws(void __iomem *phy_base, const int pos_shift[][2], - const int neg_shift[][2]) -{ - int dx, block, byte; - u32 lcdlr1, rdqsd, rdqnsd; - - ddrphy_vt_ctrl(phy_base, 0); - - for (block = 0; block < RANK_BLOCKS_TR; block++) { - for (byte = 0; byte < 2; byte++) { - dx = block * 2 + byte; - lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx)); - - /* DQS LCDL RDQNSD->[23:16] RDQSD->[15:8] */ - rdqsd = (lcdlr1 >> 8) & 0xff; - rdqnsd = (lcdlr1 >> 16) & 0xff; - rdqsd = clamp(rdqsd + ddrphy_hpstep(pos_shift[block][byte], dx, phy_base), - 0U, 0xffU); - rdqnsd = clamp(rdqnsd + ddrphy_hpstep(neg_shift[block][byte], dx, phy_base), - 0U, 0xffU); - lcdlr1 = (lcdlr1 & ~(0xffff << 8)) | (rdqsd << 8) | (rdqnsd << 16); - writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx)); - readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */ - } - } - - ddrphy_vt_ctrl(phy_base, 1); -} - -static void ddrphy_boot_run_hws(void __iomem *phy_base) -{ - /* Hard Training for DIO */ - writel(0x0000f401, phy_base + PHY_PIR); - while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) - cpu_relax(); -} - -static void ddrphy_training(void __iomem *phy_base) -{ - /* DIO roffset shift before hard training */ - ddrphy_shift_rof_hws(phy_base, rof_pos_shift_pre, rof_neg_shift_pre); - - /* Hard Training for each CH */ - ddrphy_boot_run_hws(phy_base); - - /* DIO toffset shift after training */ - ddrphy_shift_tof_hws(phy_base, tof_shift); - - /* DIO roffset shift after training */ - ddrphy_shift_rof_hws(phy_base, rof_pos_shift, rof_neg_shift); - - /* Extend DQSGating window min:+1T max:+1T */ - ddrphy_ext_dqsgt(phy_base); -} - -static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq) -{ - writel(0x40000000, phy_base + PHY_PIR); - writel(0x0300C4F1, phy_base + PHY_PGCR1); - writel(0x0C807D04, phy_base + PHY_PTR0); - writel(0x27100578, phy_base + PHY_PTR1); - writel(0x00083DEF, phy_base + PHY_PTR2); - writel(0x12061A80, phy_base + PHY_PTR3); - writel(0x08027100, phy_base + PHY_PTR4); - writel(0x9D9CBB66, phy_base + PHY_DTPR0); - writel(0x1a878400, phy_base + PHY_DTPR1); - writel(0x50025200, phy_base + PHY_DTPR2); - writel(0xF004641A, phy_base + PHY_DSGCR); - writel(0x0000040B, phy_base + PHY_DCR); - writel(0x00000d71, phy_base + PHY_MR0); - writel(0x00000006, phy_base + PHY_MR1); - writel(0x00000098, phy_base + PHY_MR2); - writel(0x00000000, phy_base + PHY_MR3); - - while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) - cpu_relax(); - - writel(0x00000059, phy_base + PHY_ZQ0CR1); - writel(0x00000019, phy_base + PHY_ZQ1CR1); - writel(0x00000019, phy_base + PHY_ZQ2CR1); - writel(0x30FC6C20, phy_base + PHY_PGCR2); - - ddrphy_set_ckoffset_qoffset(119, 0, 0, 1, phy_base); - ddrphy_set_wl_delay_dx(0, 220, 220, 1, phy_base); - ddrphy_set_wl_delay_dx(1, 160, 160, 1, phy_base); - ddrphy_set_wl_delay_dx(2, 190, 190, 1, phy_base); - ddrphy_set_wl_delay_dx(3, 150, 150, 1, phy_base); - ddrphy_set_dqsg_delay_dx(0, 750, 750, 1, phy_base); - ddrphy_set_dqsg_delay_dx(1, 750, 750, 1, phy_base); - ddrphy_set_dqsg_delay_dx(2, 750, 750, 1, phy_base); - ddrphy_set_dqsg_delay_dx(3, 750, 750, 1, phy_base); - ddrphy_set_dswb_delay_dx(0, 0, 1, phy_base); - ddrphy_set_dswb_delay_dx(1, 0, 1, phy_base); - ddrphy_set_dswb_delay_dx(2, 0, 1, phy_base); - ddrphy_set_dswb_delay_dx(3, 0, 1, phy_base); - ddrphy_set_oe_delay_dx(0, 0, 0, 1, phy_base); - ddrphy_set_oe_delay_dx(1, 0, 0, 1, phy_base); - ddrphy_set_oe_delay_dx(2, 0, 0, 1, phy_base); - ddrphy_set_oe_delay_dx(3, 0, 0, 1, phy_base); - - writel(0x44000E81, phy_base + PHY_DX0GCR); - writel(0x44000E81, phy_base + PHY_DX1GCR); - writel(0x44000E81, phy_base + PHY_DX2GCR); - writel(0x44000E81, phy_base + PHY_DX3GCR); - writel(0x00055002, phy_base + PHY_DX0GTR); - writel(0x00055002, phy_base + PHY_DX1GTR); - writel(0x00055010, phy_base + PHY_DX2GTR); - writel(0x00055010, phy_base + PHY_DX3GTR); - writel(0x930035C7, phy_base + PHY_DTCR); - writel(0x00000003, phy_base + PHY_PIR); - readl(phy_base + PHY_PIR); - while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) - cpu_relax(); - - writel(0x00000181, phy_base + PHY_PIR); - readl(phy_base + PHY_PIR); - while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) - cpu_relax(); - - writel(0x44181884, phy_base + PHY_DXCCR); - writel(0x00000001, phy_base + PHY_GPR1); -} - -/* UMC */ -static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060B0B1C}; -static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x27201806}; -static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00120B04}; -static const u32 umc_cmdctle[DRAM_FREQ_NR] = {0x00680607}; -static const u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200}; -static const u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808}; - -static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000810}; -static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000004}; -static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002}; -static const u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203}; - -static const u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605}; - -static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, - unsigned long size, int ch) -{ - /* Wait for PHY Init Complete */ - writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); - writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB); - writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC); - writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE); - writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF); - writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG); - - writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D0); - writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D1); - - writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D0); - writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D1); - - writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D0); - writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D1); - - writel(0x00000003, dc_base + UMC_ACSSETA); - writel(0x00000103, dc_base + UMC_FLOWCTLG); - writel(umc_acssetb[ch], dc_base + UMC_ACSSETB); - writel(0x02020200, dc_base + UMC_SPCSETB); - writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH); - writel(0x00000002, dc_base + UMC_ACFETCHCTRL); - - return 0; -} - -static int umc_ch_init(void __iomem *umc_ch_base, - enum dram_freq freq, unsigned long size, int ch) -{ - void __iomem *dc_base = umc_ch_base; - - return umc_dc_init(dc_base, freq, size, ch); -} - -static void um_init(void __iomem *um_base) -{ - writel(0x00000001, um_base + UMC_SIORST); - writel(0x00000001, um_base + UMC_VO0RST); - writel(0x00000001, um_base + UMC_VPERST); - writel(0x00000001, um_base + UMC_RGLRST); - writel(0x00000001, um_base + UMC_A2DRST); - writel(0x00000001, um_base + UMC_DMDRST); -} - -int uniphier_ld11_umc_init(const struct uniphier_board_data *bd) -{ - void __iomem *um_base = (void __iomem *)0x5B800000; - void __iomem *umc_ch_base = (void __iomem *)0x5BC00000; - void __iomem *phy_base = (void __iomem *)0x5BC01000; - enum dram_freq freq; - int ch, ret; - - switch (bd->dram_freq) { - case 1600: - freq = DRAM_FREQ_1600M; - break; - default: - pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); - return -EINVAL; - } - - writel(0x00000101, umc_ch_base + UMC_DIOCTLA); - while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) - cpu_relax(); - - writel(0x00000000, umc_ch_base + UMC_DIOCTLA); - writel(0x00000001, umc_ch_base + UMC_DEBUGC); - writel(0x00000101, umc_ch_base + UMC_DIOCTLA); - - writel(0x00000100, umc_ch_base + UMC_INITSET); - while (readl(umc_ch_base + UMC_INITSTAT) & BIT(8)) - cpu_relax(); - - writel(0x00000100, umc_ch_base + 0x00200000 + UMC_INITSET); - while (readl(umc_ch_base + 0x00200000 + UMC_INITSTAT) & BIT(8)) - cpu_relax(); - - ddrphy_init(phy_base, freq); - - for (ch = 0; ch < DRAM_CH_NR; ch++) { - unsigned long size = bd->dram_ch[ch].size; - unsigned int width = bd->dram_ch[ch].width; - - ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch); - if (ret) { - pr_err("failed to initialize UMC ch%d\n", ch); - return ret; - } - - umc_ch_base += 0x00200000; - } - ddrphy_training(phy_base); - - um_init(um_base); - - return 0; -} diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c deleted file mode 100644 index 500c1c11ba42..000000000000 --- a/arch/arm/mach-uniphier/dram/umc-ld20.c +++ /dev/null @@ -1,636 +0,0 @@ -/* - * Copyright (C) 2016-2017 Socionext Inc. - * - * based on commit 5ffd75ecd4929f22361ef65a35f0331d2fbc0f35 of Diag - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/bitops.h> -#include <linux/compat.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/sizes.h> -#include <asm/processor.h> - -#include "../init.h" -#include "ddruqphy-regs.h" -#include "umc64-regs.h" - -#define DRAM_CH_NR 3 - -enum dram_freq { - DRAM_FREQ_1866M, - DRAM_FREQ_NR, -}; - -enum dram_size { - DRAM_SZ_256M, - DRAM_SZ_512M, - DRAM_SZ_NR, -}; - -enum dram_board { /* board type */ - DRAM_BOARD_LD20_REF, /* LD20 reference */ - DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */ - DRAM_BOARD_LD20_C1, /* LD20 TV C1 */ - DRAM_BOARD_LD21_REF, /* LD21 reference */ - DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */ - DRAM_BOARD_NR, -}; - -/* PHY */ -static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = { - {268 - 262, 268 - 263, 268 - 378}, /* LD20 reference */ - {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV */ - {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV C1 */ - {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 reference */ - {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 TV */ -}; - -static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = { - {268, 268, 268}, /* LD20 reference */ - {268, 268, 268}, /* LD20 TV */ - {189, 189, 189}, /* LD20 TV C1 */ - {268, 268 + 252, /* No CH2 */}, /* LD21 reference */ - {268, 268 + 202, /* No CH2 */}, /* LD21 TV */ -}; - -static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = { - {268 - 378, 268 - 263, 268 - 378}, /* LD20 reference */ - {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV */ - {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV C1 */ - {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 reference */ - {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 TV */ -}; - -static const u32 ddrphy_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = { - {0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */ - {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */ - {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV C1 */ - {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 reference */ - {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 TV */ -}; - -static const u32 ddrphy_scl_gate_timing[DRAM_CH_NR] = { - 0x00000140, 0x00000180, 0x00000140 -}; - -static const short ddrphy_op_dq_shift_val_ld20[DRAM_CH_NR][32] = { - { - 2, 1, 0, 1, 2, 1, 1, 1, - 2, 1, 1, 2, 1, 1, 1, 1, - 1, 2, 1, 1, 1, 2, 1, 1, - 2, 2, 0, 1, 1, 2, 2, 1, - }, - { - 1, 1, 0, 1, 2, 2, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 0, 0, 1, 1, 0, 0, - 0, 1, 1, 1, 2, 1, 2, 1, - }, - { - 2, 2, 0, 2, 1, 1, 2, 1, - 1, 1, 0, 1, 1, -1, 1, 1, - 2, 2, 2, 2, 1, 1, 1, 1, - 1, 1, 1, 0, 2, 2, 1, 2, - }, -}; - -static const short ddrphy_op_dq_shift_val_ld21[DRAM_CH_NR][32] = { - { - 1, 1, 0, 1, 1, 1, 1, 1, - 1, 0, 0, 0, 1, 1, 0, 2, - 1, 1, 0, 0, 1, 1, 1, 1, - 1, 0, 0, 0, 1, 0, 0, 1, - }, - { 1, 0, 2, 1, 1, 1, 1, 0, - 1, 0, 0, 1, 0, 1, 0, 0, - 1, 0, 1, 0, 1, 1, 1, 0, - 1, 1, 1, 1, 0, 1, 0, 0, - }, - /* No CH2 */ -}; - -static const short (* const ddrphy_op_dq_shift_val[DRAM_BOARD_NR])[32] = { - ddrphy_op_dq_shift_val_ld20, /* LD20 reference */ - ddrphy_op_dq_shift_val_ld20, /* LD20 TV */ - ddrphy_op_dq_shift_val_ld20, /* LD20 TV C */ - ddrphy_op_dq_shift_val_ld21, /* LD21 reference */ - ddrphy_op_dq_shift_val_ld21, /* LD21 TV */ -}; - -static const short ddrphy_ip_dq_shift_val_ld20[DRAM_CH_NR][32] = { - { - 3, 3, 3, 2, 3, 2, 0, 2, - 2, 3, 3, 1, 2, 2, 2, 2, - 2, 2, 2, 2, 0, 1, 1, 1, - 2, 2, 2, 2, 3, 0, 2, 2, - }, - { - 2, 2, 1, 1, -1, 1, 1, 1, - 2, 0, 2, 2, 2, 1, 0, 2, - 2, 1, 2, 1, 0, 1, 1, 1, - 2, 2, 2, 2, 2, 2, 2, 2, - }, - { - 2, 2, 3, 2, 1, 2, 2, 2, - 2, 3, 4, 2, 3, 4, 3, 3, - 2, 2, 1, 2, 1, 1, 1, 1, - 2, 2, 2, 2, 1, 2, 2, 1, - }, -}; - -static const short ddrphy_ip_dq_shift_val_ld21[DRAM_CH_NR][32] = { - { - 2, 2, 2, 2, 1, 2, 2, 2, - 2, 3, 3, 2, 2, 2, 2, 2, - 2, 1, 2, 2, 1, 1, 1, 1, - 2, 2, 2, 3, 1, 2, 2, 2, - }, - { - 3, 4, 4, 1, 0, 1, 1, 1, - 1, 2, 1, 2, 2, 3, 3, 2, - 1, 0, 2, 1, 1, 0, 1, 0, - 0, 1, 0, 0, 1, 1, 0, 1, - }, - /* No CH2 */ -}; - -static const short (* const ddrphy_ip_dq_shift_val[DRAM_BOARD_NR])[32] = { - ddrphy_ip_dq_shift_val_ld20, /* LD20 reference */ - ddrphy_ip_dq_shift_val_ld20, /* LD20 TV */ - ddrphy_ip_dq_shift_val_ld20, /* LD20 TV C */ - ddrphy_ip_dq_shift_val_ld21, /* LD21 reference */ - ddrphy_ip_dq_shift_val_ld21, /* LD21 TV */ -}; - -static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane, - unsigned int bit) -{ - WARN_ON(lane >= 1 << PHY_LANE_SEL_LANE_WIDTH); - WARN_ON(bit >= 1 << PHY_LANE_SEL_BIT_WIDTH); - - writel((bit << PHY_LANE_SEL_BIT_SHIFT) | - (lane << PHY_LANE_SEL_LANE_SHIFT), - phy_base + PHY_LANE_SEL); -} - -#define DDRPHY_EFUSEMON (void *)0x5f900118 - -static void ddrphy_init(void __iomem *phy_base, enum dram_board board, int ch) -{ - writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1); - while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1))) - cpu_relax(); - - if (readl(DDRPHY_EFUSEMON) & BIT(ch)) - writel(0x00000000, phy_base + PHY_UNIQUIFY_TSMC_IO_1); - else - writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1); - - writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3); - writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1); - ddrphy_select_lane(phy_base, 0, 0); - writel(0x00000005, phy_base + PHY_DLL_TRIM_1); - writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); - ddrphy_select_lane(phy_base, 6, 0); - writel(0x00000005, phy_base + PHY_DLL_TRIM_1); - writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); - ddrphy_select_lane(phy_base, 12, 0); - writel(0x00000005, phy_base + PHY_DLL_TRIM_1); - writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); - ddrphy_select_lane(phy_base, 18, 0); - writel(0x00000005, phy_base + PHY_DLL_TRIM_1); - writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); - writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM); - writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1); - writel(ddrphy_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL); - writel(0x00000070, phy_base + PHY_VREF_TRAINING); - writel(0x01000075, phy_base + PHY_SCL_CONFIG_1); - writel(0x00000501, phy_base + PHY_SCL_CONFIG_2); - writel(0x00000000, phy_base + PHY_SCL_CONFIG_3); - writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); - writel(0x00000000, phy_base + PHY_SCL_CONFIG_4); - writel(ddrphy_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING); - writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT); - writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF); - writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL); - ddrphy_select_lane(phy_base, 0, 0); - writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK); - writel(0xa800100d, phy_base + PHY_DLL_RECALIB); - writel(0x00005076, phy_base + PHY_SCL_LATENCY); -} - -static int ddrphy_to_dly_step(void __iomem *phy_base, unsigned int freq, - int delay) -{ - int mdl; - - mdl = (readl(phy_base + PHY_DLL_ADRCTRL) & PHY_DLL_ADRCTRL_MDL_MASK) >> - PHY_DLL_ADRCTRL_MDL_SHIFT; - - return DIV_ROUND_CLOSEST((long)freq * delay * mdl, 2 * 1000000L); -} - -static void ddrphy_set_delay(void __iomem *phy_base, unsigned int reg, - u32 mask, u32 incr, int dly_step) -{ - u32 tmp; - - tmp = readl(phy_base + reg); - tmp &= ~mask; - tmp |= min_t(u32, abs(dly_step), mask); - - if (dly_step >= 0) - tmp |= incr; - else - tmp &= ~incr; - - writel(tmp, phy_base + reg); -} - -static void ddrphy_set_dll_recalib(void __iomem *phy_base, int dly_step) -{ - ddrphy_set_delay(phy_base, PHY_DLL_RECALIB, - PHY_DLL_RECALIB_TRIM_MASK, PHY_DLL_RECALIB_INCR, - dly_step); -} - -static void ddrphy_set_dll_adrctrl(void __iomem *phy_base, int dly_step) -{ - ddrphy_set_delay(phy_base, PHY_DLL_ADRCTRL, - PHY_DLL_ADRCTRL_TRIM_MASK, PHY_DLL_ADRCTRL_INCR, - dly_step); -} - -static void ddrphy_set_dll_trim_clk(void __iomem *phy_base, int dly_step) -{ - ddrphy_select_lane(phy_base, 0, 0); - - ddrphy_set_delay(phy_base, PHY_DLL_TRIM_CLK, - PHY_DLL_TRIM_CLK_MASK, PHY_DLL_TRIM_CLK_INCR, - dly_step); -} - -static void ddrphy_init_tail(void __iomem *phy_base, enum dram_board board, - unsigned int freq, int ch) -{ - int step; - - step = ddrphy_to_dly_step(phy_base, freq, ddrphy_adrctrl[board][ch]); - ddrphy_set_dll_adrctrl(phy_base, step); - - step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dlltrimclk[board][ch]); - ddrphy_set_dll_trim_clk(phy_base, step); - - step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dllrecalib[board][ch]); - ddrphy_set_dll_recalib(phy_base, step); -} - -static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg, - u32 mask, u32 incr, short shift_val) -{ - u32 tmp; - int val; - - tmp = readl(phy_base + reg); - - val = tmp & mask; - if (!(tmp & incr)) - val = -val; - - val += shift_val; - - tmp &= ~(incr | mask); - tmp |= min_t(u32, abs(val), mask); - if (val >= 0) - tmp |= incr; - - writel(tmp, phy_base + reg); -} - -static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg, - u32 mask, u32 incr, u32 override, - const short *shift_val_array) -{ - u32 tmp; - int dx, bit; - - tmp = readl(phy_base + reg); - tmp |= override; - writel(tmp, phy_base + reg); - - for (dx = 0; dx < 4; dx++) { - for (bit = 0; bit < 8; bit++) { - ddrphy_select_lane(phy_base, - (PHY_BITLVL_DLY_WIDTH + 1) * dx, - bit); - - ddrphy_shift_one_dq(phy_base, reg, mask, incr, - shift_val_array[dx * 8 + bit]); - } - } - - ddrphy_select_lane(phy_base, 0, 0); -} - -static int ddrphy_training(void __iomem *phy_base, enum dram_board board, - int ch) -{ - writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM); - writel(0x00010000, phy_base + PHY_DLL_TRIM_2); - writel(0x50000000, phy_base + PHY_SCL_START); - - while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE) - cpu_relax(); - - writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL); - writel(0xff00ff00, phy_base + PHY_SCL_DATA_0); - writel(0xff00ff00, phy_base + PHY_SCL_DATA_1); - writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR); - writel(0x11000000, phy_base + PHY_SCL_START); - - while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE) - cpu_relax(); - - writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR); - writel(0x30500000, phy_base + PHY_SCL_START); - - while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE) - cpu_relax(); - - writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL); - writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA); - writel(0x789b3de0, phy_base + PHY_SCL_DATA_0); - writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1); - writel(0x11000000, phy_base + PHY_SCL_START); - - while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE) - cpu_relax(); - - writel(0x34000000, phy_base + PHY_SCL_START); - - while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE) - cpu_relax(); - - writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL); - - writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); - writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL); - writel(0x011BD0C4, phy_base + PHY_DSCL_CNT); - - /* shift ip_dq trim */ - ddrphy_shift_dq(phy_base, - PHY_IP_DQ_DQS_BITWISE_TRIM, - PHY_IP_DQ_DQS_BITWISE_TRIM_MASK, - PHY_IP_DQ_DQS_BITWISE_TRIM_INC, - PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE, - ddrphy_ip_dq_shift_val[board][ch]); - - /* shift op_dq trim */ - ddrphy_shift_dq(phy_base, - PHY_OP_DQ_DM_DQS_BITWISE_TRIM, - PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK, - PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC, - PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE, - ddrphy_op_dq_shift_val[board][ch]); - - return 0; -} - -/* UMC */ -static const u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11}; -static const u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC}; -static const u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF}; -static const u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114}; -static const u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0}; - -static const u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = { - /* 256MB 512MB */ - {0x00000601, 0x00000801}, /* 1866 MHz */ -}; - -static const u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = { - /* 256MB 512MB */ - {0x00000120, 0x00000130}, /* 1866 MHz */ -}; - -static const u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = { - /* 256MB 512MB */ - {0x00033603, 0x00033803}, /* 1866 MHz */ -}; - -static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; -static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; -static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; -static const u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = { - /* 256MB 512MB */ - {0x0049071D, 0x0078071D}, /* 1866 MHz */ -}; - -static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000610}; -static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000204}; -static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002}; -static const u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000}; - -static const u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E}; -static const u32 umc_directbusctrla[DRAM_CH_NR] = { - 0x00000000, 0x00000001, 0x00000001 -}; - -static void umc_poll_phy_init_complete(void __iomem *dc_base) -{ - /* Wait for PHY Init Complete */ - while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0))) - cpu_relax(); -} - -static int umc_dc_init(void __iomem *dc_base, unsigned int freq, - unsigned long size, int ch) -{ - enum dram_freq freq_e; - enum dram_size size_e; - - switch (freq) { - case 1866: - freq_e = DRAM_FREQ_1866M; - break; - default: - pr_err("unsupported DRAM frequency %ud MHz\n", freq); - return -EINVAL; - } - - switch (size) { - case 0: - return 0; - case SZ_256M: - size_e = DRAM_SZ_256M; - break; - case SZ_512M: - size_e = DRAM_SZ_512M; - break; - default: - pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n", - size, ch); - return -EINVAL; - } - - writel(0x00000001, dc_base + UMC_DFICSOVRRD); - writel(0x00000000, dc_base + UMC_DFITURNOFF); - - writel(umc_initctla[freq_e], dc_base + UMC_INITCTLA); - writel(umc_initctlb[freq_e], dc_base + UMC_INITCTLB); - writel(umc_initctlc[freq_e], dc_base + UMC_INITCTLC); - - writel(umc_drmmr0[freq_e], dc_base + UMC_DRMMR0); - writel(0x00000004, dc_base + UMC_DRMMR1); - writel(umc_drmmr2[freq_e], dc_base + UMC_DRMMR2); - writel(0x00000000, dc_base + UMC_DRMMR3); - - writel(umc_memconf0a[freq_e][size_e], dc_base + UMC_MEMCONF0A); - writel(umc_memconf0b[freq_e][size_e], dc_base + UMC_MEMCONF0B); - writel(umc_memconfch[freq_e][size_e], dc_base + UMC_MEMCONFCH); - writel(0x00000000, dc_base + UMC_MEMMAPSET); - - writel(umc_cmdctla[freq_e], dc_base + UMC_CMDCTLA); - writel(umc_cmdctlb[freq_e], dc_base + UMC_CMDCTLB); - writel(umc_cmdctlc[freq_e], dc_base + UMC_CMDCTLC); - writel(umc_cmdctle[freq_e][size_e], dc_base + UMC_CMDCTLE); - - writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0); - writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D1); - - writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D0); - writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D1); - writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D0); - writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D1); - writel(umc_dataset[freq_e], dc_base + UMC_DATASET); - - writel(0x00400020, dc_base + UMC_DCCGCTL); - writel(0x00000003, dc_base + UMC_ACSSETA); - writel(0x00000103, dc_base + UMC_FLOWCTLG); - writel(0x00010200, dc_base + UMC_ACSSETB); - - writel(umc_flowctla[freq_e], dc_base + UMC_FLOWCTLA); - writel(0x00004444, dc_base + UMC_FLOWCTLC); - writel(0x00000000, dc_base + UMC_DFICUPDCTLA); - - writel(0x00202000, dc_base + UMC_FLOWCTLB); - writel(0x00000000, dc_base + UMC_BSICMAPSET); - writel(0x00000000, dc_base + UMC_ERRMASKA); - writel(0x00000000, dc_base + UMC_ERRMASKB); - - writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA); - - writel(0x00000001, dc_base + UMC_INITSET); - /* Wait for PHY Init Complete */ - while (readl(dc_base + UMC_INITSTAT) & BIT(0)) - cpu_relax(); - - writel(0x2A0A0A00, dc_base + UMC_SPCSETB); - writel(0x00000000, dc_base + UMC_DFICSOVRRD); - - return 0; -} - -static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base, - enum dram_board board, unsigned int freq, - unsigned long size, int ch) -{ - void __iomem *dc_base = umc_ch_base + 0x00011000; - void __iomem *phy_base = phy_ch_base; - int ret; - - /* PHY Update Mode (ON) */ - writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA); - - /* deassert PHY reset signals */ - writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, - dc_base + UMC_DIOCTLA); - - ddrphy_init(phy_base, board, ch); - - umc_poll_phy_init_complete(dc_base); - - ddrphy_init_tail(phy_base, board, freq, ch); - - ret = umc_dc_init(dc_base, freq, size, ch); - if (ret) - return ret; - - ret = ddrphy_training(phy_base, board, ch); - if (ret) - return ret; - - return 0; -} - -static void um_init(void __iomem *um_base) -{ - writel(0x000000ff, um_base + UMC_MBUS0); - writel(0x000000ff, um_base + UMC_MBUS1); - writel(0x000000ff, um_base + UMC_MBUS2); - writel(0x00000001, um_base + UMC_MBUS3); - writel(0x00000001, um_base + UMC_MBUS4); - writel(0x00000001, um_base + UMC_MBUS5); - writel(0x00000001, um_base + UMC_MBUS6); - writel(0x00000001, um_base + UMC_MBUS7); - writel(0x00000001, um_base + UMC_MBUS8); - writel(0x00000001, um_base + UMC_MBUS9); - writel(0x00000001, um_base + UMC_MBUS10); -} - -int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) -{ - void __iomem *um_base = (void __iomem *)0x5b600000; - void __iomem *umc_ch_base = (void __iomem *)0x5b800000; - void __iomem *phy_ch_base = (void __iomem *)0x6e200000; - enum dram_board board; - int ch, ret; - - switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) { - case UNIPHIER_BD_BOARD_LD20_REF: - board = DRAM_BOARD_LD20_REF; - break; - case UNIPHIER_BD_BOARD_LD20_GLOBAL: - board = DRAM_BOARD_LD20_GLOBAL; - break; - case UNIPHIER_BD_BOARD_LD20_C1: - board = DRAM_BOARD_LD20_C1; - break; - case UNIPHIER_BD_BOARD_LD21_REF: - board = DRAM_BOARD_LD21_REF; - break; - case UNIPHIER_BD_BOARD_LD21_GLOBAL: - board = DRAM_BOARD_LD21_GLOBAL; - break; - default: - pr_err("unsupported board type %d\n", - UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)); - return -EINVAL; - } - - for (ch = 0; ch < DRAM_CH_NR; ch++) { - unsigned long size = bd->dram_ch[ch].size; - unsigned int width = bd->dram_ch[ch].width; - - if (size) { - ret = umc_ch_init(umc_ch_base, phy_ch_base, board, - bd->dram_freq, size / (width / 16), - ch); - if (ret) { - pr_err("failed to initialize UMC ch%d\n", ch); - return ret; - } - } - - umc_ch_base += 0x00200000; - phy_ch_base += 0x00004000; - } - - um_init(um_base); - - return 0; -} diff --git a/arch/arm/mach-uniphier/dram/umc64-regs.h b/arch/arm/mach-uniphier/dram/umc64-regs.h deleted file mode 100644 index 860d04e38140..000000000000 --- a/arch/arm/mach-uniphier/dram/umc64-regs.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - */ - -#ifndef UMC_LD20_REGS_H -#define UMC_LD20_REGS_H - -#define UMC_CMDCTLA 0x00000000 -#define UMC_CMDCTLB 0x00000004 -#define UMC_CMDCTLC 0x00000008 -#define UMC_INITCTLA 0x00000020 -#define UMC_INITCTLB 0x00000024 -#define UMC_INITCTLC 0x00000028 -#define UMC_DRMMR0 0x00000030 -#define UMC_DRMMR1 0x00000034 -#define UMC_DRMMR2 0x00000038 -#define UMC_DRMMR3 0x0000003C -#define UMC_INITSET 0x00000040 -#define UMC_INITSTAT 0x00000044 -#define UMC_CMDCTLE 0x00000050 -#define UMC_CMDCTLF 0x00000054 -#define UMC_CMDCTLG 0x00000058 -#define UMC_SPCSETB 0x00000084 -#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ -#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ -#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ -#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ -#define UMC_ACSSETA 0x000000C0 -#define UMC_ACSSETB 0x000000C4 -#define UMC_MEMCONF0A 0x00000200 -#define UMC_MEMCONF0B 0x00000204 -#define UMC_MEMCONFCH 0x00000240 -#define UMC_MEMMAPSET 0x00000250 -#define UMC_FLOWCTLA 0x00000400 -#define UMC_FLOWCTLB 0x00000404 -#define UMC_FLOWCTLC 0x00000408 -#define UMC_ACFETCHCTRL 0x00000460 -#define UMC_FLOWCTLG 0x00000508 -#define UMC_RDATACTL_D0 0x00000600 -#define UMC_WDATACTL_D0 0x00000604 -#define UMC_RDATACTL_D1 0x00000608 -#define UMC_WDATACTL_D1 0x0000060C -#define UMC_DATASET 0x00000610 -#define UMC_ODTCTL_D0 0x00000618 -#define UMC_ODTCTL_D1 0x0000061C -#define UMC_RESPCTL 0x00000624 -#define UMC_DIRECTBUSCTRLA 0x00000680 -#define UMC_DEBUGC 0x00000718 -#define UMC_DCCGCTL 0x00000720 -#define UMC_DICGCTLA 0x00000724 -#define UMC_DICGCTLB 0x00000728 -#define UMC_ERRMASKA 0x00000958 -#define UMC_ERRMASKB 0x0000095C -#define UMC_BSICMAPSET 0x00000988 -#define UMC_DIOCTLA 0x00000C00 -#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ -#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ -#define UMC_DFISTCTLC 0x00000C18 -#define UMC_DFICUPDCTLA 0x00000C20 -#define UMC_DFIPUPDCTLA 0x00000C30 -#define UMC_DFICSOVRRD 0x00000C84 -#define UMC_DFITURNOFF 0x00000C88 - -/* UM registers */ -#define UMC_MBUS0 0x00080004 -#define UMC_MBUS1 0x00081004 -#define UMC_MBUS2 0x00082004 -#define UMC_MBUS3 0x00000C78 -#define UMC_MBUS4 0x00000CF8 -#define UMC_MBUS5 0x00000E78 -#define UMC_MBUS6 0x00000EF8 -#define UMC_MBUS7 0x00001278 -#define UMC_MBUS8 0x000012F8 -#define UMC_MBUS9 0x00002478 -#define UMC_MBUS10 0x000024F8 - -/* UMC1 register */ -#define UMC_SIORST 0x00000728 -#define UMC_VO0RST 0x0000073c -#define UMC_VPERST 0x00000744 -#define UMC_RGLRST 0x00000750 -#define UMC_A2DRST 0x00000764 -#define UMC_DMDRST 0x00000770 - -#endif /* UMC_LD20_REGS_H */ diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 56f514e297f5..b322628eedfa 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -24,13 +24,6 @@ struct uniphier_board_data { #define UNIPHIER_BD_DRAM_SPARSE BIT(9) #define UNIPHIER_BD_DDR3PLUS BIT(8) - -#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x7) -#define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */ -#define UNIPHIER_BD_BOARD_LD20_GLOBAL 1 /* LD20 TV Set */ -#define UNIPHIER_BD_BOARD_LD20_C1 2 /* LD20 TV Set C1 */ -#define UNIPHIER_BD_BOARD_LD21_REF 3 /* LD21 reference */ -#define UNIPHIER_BD_BOARD_LD21_GLOBAL 4 /* LD21 TV Set */ }; const struct uniphier_board_data *uniphier_get_board_param(void); @@ -41,8 +34,6 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd); int uniphier_sld8_init(const struct uniphier_board_data *bd); int uniphier_pro5_init(const struct uniphier_board_data *bd); int uniphier_pxs2_init(const struct uniphier_board_data *bd); -int uniphier_ld11_init(const struct uniphier_board_data *bd); -int uniphier_ld20_init(const struct uniphier_board_data *bd); #if defined(CONFIG_MICRO_SUPPORT_CARD) void uniphier_sbc_init_admulti(void); @@ -85,17 +76,12 @@ int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd); int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd); int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd); int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd); -int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd); -int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd); void uniphier_sld3_early_clk_init(void); -void uniphier_ld11_early_clk_init(void); void uniphier_sld3_dram_clk_init(void); void uniphier_pro5_dram_clk_init(void); void uniphier_pxs2_dram_clk_init(void); -void uniphier_ld11_dram_clk_init(void); -void uniphier_ld20_dram_clk_init(void); int uniphier_sld3_umc_init(const struct uniphier_board_data *bd); int uniphier_ld4_umc_init(const struct uniphier_board_data *bd); @@ -103,8 +89,6 @@ int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); int uniphier_sld8_umc_init(const struct uniphier_board_data *bd); int uniphier_pro5_umc_init(const struct uniphier_board_data *bd); int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd); -int uniphier_ld20_umc_init(const struct uniphier_board_data *bd); -int uniphier_ld11_umc_init(const struct uniphier_board_data *bd); void uniphier_sld3_pll_init(void); void uniphier_ld4_pll_init(void); @@ -125,8 +109,6 @@ unsigned int uniphier_boot_device_raw(void); int uniphier_have_internal_stm(void); int uniphier_boot_from_backend(void); int uniphier_pin_init(const char *pinconfig_name); -void uniphier_smp_kick_all_cpus(void); -void cci500_init(unsigned int nr_slaves); #undef pr_warn #define pr_warn(fmt, args...) printf(fmt, ##args) diff --git a/arch/arm/mach-uniphier/spl_board_init.c b/arch/arm/mach-uniphier/spl_board_init.c index 0079a083e838..6da5631bcace 100644 --- a/arch/arm/mach-uniphier/spl_board_init.c +++ b/arch/arm/mach-uniphier/spl_board_init.c @@ -97,26 +97,6 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { .umc_init = uniphier_pxs2_umc_init, }, #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD11) - { - .soc_id = UNIPHIER_LD11_ID, - .early_clk_init = uniphier_ld11_early_clk_init, - .dpll_init = uniphier_ld11_dpll_init, - .memconf_init = uniphier_memconf_2ch_init, - .dram_clk_init = uniphier_ld11_dram_clk_init, - .umc_init = uniphier_ld11_umc_init, - }, -#endif -#if defined(CONFIG_ARCH_UNIPHIER_LD20) - { - .soc_id = UNIPHIER_LD20_ID, - .early_clk_init = uniphier_ld11_early_clk_init, - .dpll_init = uniphier_ld20_dpll_init, - .memconf_init = uniphier_memconf_3ch_init, - .dram_clk_init = uniphier_ld20_dram_clk_init, - .umc_init = uniphier_ld20_umc_init, - }, -#endif }; UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata, uniphier_spl_initdata) @@ -141,10 +121,8 @@ void spl_board_init(void) if (initdata->bcu_init) initdata->bcu_init(bd); - initdata->early_clk_init(); - #ifdef CONFIG_SPL_SERIAL_SUPPORT preloader_console_init(); #endif @@ -168,8 +146,4 @@ void spl_board_init(void) pr_err("failed to init DRAM\n"); hang(); } - -#ifdef CONFIG_ARM64 - dcache_disable(); -#endif } diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig deleted file mode 100644 index 9601dcca05df..000000000000 --- a/configs/uniphier_ld11_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_ARCH_UNIPHIER_LD11_SINGLE=y -CONFIG_MICRO_SUPPORT_CARD=y -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref" -# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -CONFIG_SPL=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_CONFIG=y -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -# CONFIG_CMD_MISC is not set -CONFIG_CMD_FAT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_OF_TRANSLATE=y -CONFIG_GPIO_UNIPHIER=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_STORAGE=y diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig deleted file mode 100644 index b5255a6b8db9..000000000000 --- a/configs/uniphier_ld20_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_ARCH_UNIPHIER_LD20_SINGLE=y -CONFIG_MICRO_SUPPORT_CARD=y -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref" -# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -CONFIG_SPL=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_CONFIG=y -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -# CONFIG_CMD_MISC is not set -CONFIG_CMD_FAT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_OF_TRANSLATE=y -CONFIG_GPIO_UNIPHIER=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_MMC_UNIPHIER=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/doc/README.uniphier b/doc/README.uniphier index f79659c9cabd..e2f3b9a2ec23 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -55,11 +55,11 @@ LD6b reference board: $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-ld6b-ref LD11 reference board: - $ make uniphier_ld11_defconfig - $ make CROSS_COMPILE=aarch64-linux-gnu- + $ make uniphier_v8_defconfig + $ make CROSS_COMPILE=aarch64-linux-gnu- DEVICE_TREE=uniphier-ld11-ref LD20 reference board: - $ make uniphier_ld20_defconfig + $ make uniphier_v8_defconfig $ make CROSS_COMPILE=aarch64-linux-gnu- PXs3 reference board: diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index 9c2db1afc8c7..e2b234ff1496 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -59,12 +59,12 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c3), UNIPHIER_PINCTRL_GROUP(i2c4), UNIPHIER_PINCTRL_GROUP(nand), - UNIPHIER_PINCTRL_GROUP_SPL(system_bus), - UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1), - UNIPHIER_PINCTRL_GROUP_SPL(uart0), - UNIPHIER_PINCTRL_GROUP_SPL(uart1), - UNIPHIER_PINCTRL_GROUP_SPL(uart2), - UNIPHIER_PINCTRL_GROUP_SPL(uart3), + UNIPHIER_PINCTRL_GROUP(system_bus), + UNIPHIER_PINCTRL_GROUP(system_bus_cs1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), @@ -78,11 +78,11 @@ static const char * const uniphier_ld11_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(i2c4), UNIPHIER_PINMUX_FUNCTION(nand), - UNIPHIER_PINMUX_FUNCTION_SPL(system_bus), - UNIPHIER_PINMUX_FUNCTION_SPL(uart0), - UNIPHIER_PINMUX_FUNCTION_SPL(uart1), - UNIPHIER_PINMUX_FUNCTION_SPL(uart2), - UNIPHIER_PINMUX_FUNCTION_SPL(uart3), + UNIPHIER_PINMUX_FUNCTION(system_bus), + UNIPHIER_PINMUX_FUNCTION(uart0), + UNIPHIER_PINMUX_FUNCTION(uart1), + UNIPHIER_PINMUX_FUNCTION(uart2), + UNIPHIER_PINMUX_FUNCTION(uart3), UNIPHIER_PINMUX_FUNCTION(usb0), UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 0b0af1c018a9..11d5d98a5a16 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -69,12 +69,12 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c4), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(sd), - UNIPHIER_PINCTRL_GROUP_SPL(system_bus), - UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1), - UNIPHIER_PINCTRL_GROUP_SPL(uart0), - UNIPHIER_PINCTRL_GROUP_SPL(uart1), - UNIPHIER_PINCTRL_GROUP_SPL(uart2), - UNIPHIER_PINCTRL_GROUP_SPL(uart3), + UNIPHIER_PINCTRL_GROUP(system_bus), + UNIPHIER_PINCTRL_GROUP(system_bus_cs1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), @@ -91,11 +91,11 @@ static const char * const uniphier_ld20_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c4), UNIPHIER_PINMUX_FUNCTION(nand), UNIPHIER_PINMUX_FUNCTION(sd), - UNIPHIER_PINMUX_FUNCTION_SPL(system_bus), - UNIPHIER_PINMUX_FUNCTION_SPL(uart0), - UNIPHIER_PINMUX_FUNCTION_SPL(uart1), - UNIPHIER_PINMUX_FUNCTION_SPL(uart2), - UNIPHIER_PINMUX_FUNCTION_SPL(uart3), + UNIPHIER_PINMUX_FUNCTION(system_bus), + UNIPHIER_PINMUX_FUNCTION(uart0), + UNIPHIER_PINMUX_FUNCTION(uart1), + UNIPHIER_PINMUX_FUNCTION(uart2), + UNIPHIER_PINMUX_FUNCTION(uart3), UNIPHIER_PINMUX_FUNCTION(usb0), UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 86752d91ffeb..423e48b0037a 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -78,12 +78,12 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c3), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(sd), - UNIPHIER_PINCTRL_GROUP_SPL(system_bus), - UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1), - UNIPHIER_PINCTRL_GROUP_SPL(uart0), - UNIPHIER_PINCTRL_GROUP_SPL(uart1), - UNIPHIER_PINCTRL_GROUP_SPL(uart2), - UNIPHIER_PINCTRL_GROUP_SPL(uart3), + UNIPHIER_PINCTRL_GROUP(system_bus), + UNIPHIER_PINCTRL_GROUP(system_bus_cs1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), @@ -102,11 +102,11 @@ static const char * const uniphier_pxs3_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), UNIPHIER_PINMUX_FUNCTION(sd), - UNIPHIER_PINMUX_FUNCTION_SPL(system_bus), - UNIPHIER_PINMUX_FUNCTION_SPL(uart0), - UNIPHIER_PINMUX_FUNCTION_SPL(uart1), - UNIPHIER_PINMUX_FUNCTION_SPL(uart2), - UNIPHIER_PINMUX_FUNCTION_SPL(uart3), + UNIPHIER_PINMUX_FUNCTION(system_bus), + UNIPHIER_PINMUX_FUNCTION(uart0), + UNIPHIER_PINMUX_FUNCTION(uart1), + UNIPHIER_PINMUX_FUNCTION(uart2), + UNIPHIER_PINMUX_FUNCTION(uart3), UNIPHIER_PINMUX_FUNCTION(usb0), UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index e45b506eba92..3da21b60ccd6 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -80,17 +80,7 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 1 -#ifdef CONFIG_ARMV8_MULTIENTRY -#define CPU_RELEASE_ADDR 0x80000000 -#define COUNTER_FREQUENCY 50000000 -#define CONFIG_GICV3 -#define GICD_BASE 0x5fe00000 -#if defined(CONFIG_ARCH_UNIPHIER_LD11) -#define GICR_BASE 0x5fe40000 -#elif defined(CONFIG_ARCH_UNIPHIER_LD20) -#define GICR_BASE 0x5fe80000 -#endif -#elif !defined(CONFIG_ARM64) +#if !defined(CONFIG_ARM64) /* Time clock 1MHz */ #define CONFIG_SYS_TIMER_RATE 1000000 #endif @@ -137,7 +127,7 @@ #define CONFIG_CMDLINE_EDITING /* add command line history */ -#if defined(CONFIG_ARM64) && !defined(CONFIG_ARMV8_MULTIENTRY) +#if defined(CONFIG_ARM64) /* ARM Trusted Firmware */ #define BOOT_IMAGES \ "second_image=unph_bl.bin\0" \ @@ -265,9 +255,7 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) /* only for SPL */ -#if defined(CONFIG_ARM64) -#define CONFIG_SPL_TEXT_BASE 0x30000000 -#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ +#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ defined(CONFIG_ARCH_UNIPHIER_LD4) || \ defined(CONFIG_ARCH_UNIPHIER_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 @@ -275,18 +263,9 @@ #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD11) -#define CONFIG_SPL_STACK (0x30014c00) -#elif defined(CONFIG_ARCH_UNIPHIER_LD20) -#define CONFIG_SPL_STACK (0x3001c000) -#else #define CONFIG_SPL_STACK (0x00100000) -#endif #define CONFIG_SPL_FRAMEWORK -#ifdef CONFIG_ARM64 -#define CONFIG_SPL_BOARD_LOAD_IMAGE -#endif #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 @@ -295,16 +274,7 @@ #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 -#if defined(CONFIG_ARCH_UNIPHIER_LD20) -#define CONFIG_SPL_MAX_SIZE 0x14000 -#else #define CONFIG_SPL_MAX_SIZE 0x10000 -#endif -#if defined(CONFIG_ARCH_UNIPHIER_LD11) -#define CONFIG_SPL_BSS_START_ADDR 0x30012000 -#elif defined(CONFIG_ARCH_UNIPHIER_LD20) -#define CONFIG_SPL_BSS_START_ADDR 0x30016000 -#endif #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #define CONFIG_SPL_PAD_TO 0x20000 -- 2.7.4

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[U-Boot] [PATCH] nios2: tune specific cpu features
by Kirill Smirnov 26 Jul '17

26 Jul '17

This patch allows developer to tell gcc which nios2 cpu features he enabled in his design. This way gcc will generate more efficient code for a specific platform. Signed-off-by: Kirill Smirnov <kirill.k.smirnov(a)gmail.com> --- arch/nios2/Kconfig | 31 +++++++++++++++++++++++++++++++ arch/nios2/config.mk | 22 ++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig index bb4fb2ac3a..12be43343c 100644 --- a/arch/nios2/Kconfig +++ b/arch/nios2/Kconfig @@ -11,4 +11,35 @@ config SYS_CONFIG_NAME The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h should be included from include/config.h. +config SYS_TUNE_CPU_FEATURES + bool "Tune cpu features" + default n + help + Tune gcc flags to reflect nios2 cpu features. + If a specific feature is enabled the corresponding + -mhw-<feature> flag is passed to gcc. Otherwise, + -mno-hw-<features> flag is passed. + +if SYS_TUNE_CPU_FEATURES + +config SYS_HW_DIV + bool "Enable div family of instructions" + default n + help + This options passes -mhw-div flag to gcc. + +config SYS_HW_MUL + bool "Enable mul family of instructions" + default y + help + This options passes -mhw-mul flag to gcc. + +config SYS_HW_MULX + bool "Enable mulx family of instructions" + default n + help + This options passes -mhw-mulx flag to gcc. + +endif + endmenu diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 82bd887961..bbb5d7f853 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -15,5 +15,27 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000 PLATFORM_CPPFLAGS += -D__NIOS2__ PLATFORM_CPPFLAGS += -G0 +ifeq ($(CONFIG_SYS_TUNE_CPU_FEATURES),y) + +ifeq ($(CONFIG_SYS_HW_DIV),y) +PLATFORM_CPPFLAGS += -mhw-div +else +PLATFORM_CPPFLAGS += -mno-hw-div +endif + +ifeq ($(CONFIG_SYS_HW_MUL),y) +PLATFORM_CPPFLAGS += -mhw-mul +else +PLATFORM_CPPFLAGS += -mno-hw-mul +endif + +ifeq ($(CONFIG_SYS_HW_MULX),y) +PLATFORM_CPPFLAGS += -mhw-mulx +else +PLATFORM_CPPFLAGS += -mno-hw-mulx +endif + +endif + LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -- 2.13.2

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