July 2017 - U-Boot

[U-Boot] [PATCH v2] rockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via Kconfig
by Philipp Tomsich 27 Jul '17

27 Jul '17

SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously enabled through rk3399_common.h. This change implies these options through Kconfig. These need to always be active for the RK3399, as follows: - SPL_SERIAL_SUPPORT is needed to pass the SPL build - SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- Changes in v2: - fixes the naming of SPL_DRIVERS_MISC_SUPPORT (shortened to SPL_DRIVERS_MISC in v1 of this patch) arch/arm/mach-rockchip/Kconfig | 2 ++ include/configs/rk3399_common.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index fd08897..8406e33 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -92,6 +92,8 @@ config ROCKCHIP_RK3399 select SUPPORT_SPL select SPL select SPL_SEPARATE_BSS + select SPL_SERIAL_SUPPORT + select SPL_DRIVERS_MISC_SUPPORT select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT help diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 54ea97b..6c9d760 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT #if defined(CONFIG_SPL_SPI_SUPPORT) #define CONFIG_SPL_SPI_LOAD #endif -- 2.1.4

1 2

[U-Boot] [PATCH v6 0/3] rockchip: firefly: Enabled the USB keyboard in the uboot
by Leo Wen 27 Jul '17

27 Jul '17

These three patches enable usbkeyboard drivers(usb_kbd.c) and set some environment variables to auto-start USB device. You can use the usbkeyboard instead of the serial input command in uboot. Leo Wen (3): rockchip: firefly: Add some macros to enable the usb keyboard rockchip: firefly: Set the environment variable 'usbkbd' to the stdin rockchip: firefly: Add "usb start" to auto-start USB device configs/firefly-rk3288_defconfig | 4 ++++ include/configs/firefly-rk3288.h | 5 +++-- 2 files changed, 7 insertions(+), 2 deletions(-) -- 2.7.4

2 12

[U-Boot] [PATCH] rockchip: rk3288: Add support for drive-strength in PINCTRL
by Romain Perier 27 Jul '17

27 Jul '17

Currently, drive-strenght to 12ma are described and supposed to be used on RK3288. However, the pinctrl driver for this SoC only handles muxing and pull up/pull down via PU/PD control registers. So complex IPs like GMAC are working in normal ethernet 100mbps, but not at 1gbps typically. This commit adds support for handling drive-strength of 12ma, when it's defined in the DT. Signed-off-by: Romain Perier <romain.perier(a)collabora.com> --- drivers/pinctrl/rockchip/pinctrl_rk3288.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c index 47cefc5abf..a21b64044b 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c @@ -729,7 +729,7 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index, value |= (mask << (shift + 16)) | (muxval << shift); writel(value, addr); - /* Handle pullup/pulldown */ + /* Handle pullup/pulldown/drive-strength */ if (flags) { uint val = 0; @@ -737,10 +737,15 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index, val = 1; else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) val = 2; + else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH)) + val = 3; + shift = (index & 7) * 2; ind = index >> 3; if (banknum == 0) addr = &priv->pmu->gpio0pull[ind]; + else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH)) + addr = &priv->grf->gpio1_e[banknum - 1][ind]; else addr = &priv->grf->gpio1_p[banknum - 1][ind]; debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val, @@ -779,6 +784,9 @@ static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config) if (flags < 0) return flags; + if (fdtdec_get_int(blob, pcfg_node, "drive-strength", 0) == 12) + flags |= 1 << PIN_CONFIG_DRIVE_STRENGTH; + ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2], flags); if (ret) -- 2.11.0

2 3

[U-Boot] [PATCH] rockchip: use UUID for root partitions
by Kever Yang 27 Jul '17

27 Jul '17

We use to use /dev/mmcbl0p7 as root partition, and pass it to kernel by cmdline, but the mmc number in kernel in not fixed, we need to change the bootargs to adapt it from time to time. We can use the UUID to fix it, the ID is from: https://www.freedesktop.org/wiki/Specifications/DiscoverablePartitionsSpec/ ARM 32bit: 69dad710-2ce4-4e3c-b16c-21a1d49abed3 ARM 64bit: b921b045-1df0-41c3-af44-4c6f280d3fae Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- include/configs/rockchip-common.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 9d183ce..e330cd5 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -28,6 +28,12 @@ #endif #define CONFIG_RANDOM_UUID + +#ifdef CONFIG_ARM64 +#define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0" +#else +#define ROOT_UUID "69DAD710-2CE4-4E3C-B16C-21A1D49ABED3;\0" +#endif #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ "name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \ @@ -36,7 +42,7 @@ "name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \ "name=atf,size=4M,uuid=${uuid_gpt_atf};" \ "name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \ - "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \ + "name=rootfs,size=-,uuid="ROOT_UUID #endif -- 1.9.1

2 3

[U-Boot] [PATCH] rockchip: rk3229: add dwc2 node for fastboot
by Meng Dongyang 27 Jul '17

27 Jul '17

The dwc2 gadget function will get address from DT when fastboot start, so we need to add dwc2 node to support fastboot. Meng Dongyang (1): rockchip: dts: rk3229: add dwc2 node for fastboot arch/arm/dts/rk3229-evb.dts | 4 ++++ arch/arm/dts/rk322x.dtsi | 10 ++++++++++ 2 files changed, 14 insertions(+) -- 1.9.1

4 7

[U-Boot] [PATCH] rockchip: dts: firefly using ddr3 1600
by Kever Yang 27 Jul '17

27 Jul '17

According to my test, some of firefly-rk3399 hang after dram init when using ddr3-1333 config, while using ddr3-1600 config works for all the board I have test. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/dts/rk3399-firefly.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index 91d3193..a3e9ddf 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -8,7 +8,7 @@ #include <dt-bindings/pwm/pwm.h> #include <dt-bindings/pinctrl/rockchip.h> #include "rk3399.dtsi" -#include "rk3399-sdram-ddr3-1333.dtsi" +#include "rk3399-sdram-ddr3-1600.dtsi" / { model = "Firefly-RK3399 Board"; -- 1.9.1

2 3

[U-Boot] [PATCH 1/2] rockchip: phycore: Add ID page of M24C32-D EEPROM
by Wadim Egorov 27 Jul '17

27 Jul '17

The Identification Page (32 byte) is an additional page which can be written and (later) permanently locked in Read-only mode. phyCORE-RK3288 SoMs are using this page to describe the module variant. This page also contains a MAC. Our boards can be equipped with a different amount of EEPROMs. To make this more transparent let's add an alias for the eeprom which stores the module variant. Signed-off-by: Wadim Egorov <w.egorov(a)phytec.de> --- arch/arm/dts/rk3288-phycore-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi index fd463f4..02d1196 100644 --- a/arch/arm/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -61,6 +61,7 @@ aliases { rtc0 = &i2c_rtc; rtc1 = &rk818; + eeprom0 = &i2c_eeprom_id; }; ext_gmac: external-gmac-clock { @@ -383,6 +384,13 @@ pagesize = <32>; }; + /* M24C32-D Identification page */ + i2c_eeprom_id: eeprom@58 { + compatible = "atmel,24c32"; + reg = <0x58>; + pagesize = <32>; + }; + vdd_cpu: regulator@60 { compatible = "fcs,fan53555"; reg = <0x60>; -- 1.9.1

2 6

[U-Boot] [PATCH 0/2] rockchip: rk3288: Fixes for GMAC
by Romain Perier 27 Jul '17

27 Jul '17

This set of patches contains two fixes. The first one removes the pull up for GPIO4B0 that is the pin for phy-reset. This is already supported by GMAC ("reset-gpio" from DT) and should not be hardcoded in the pinctrl driver. The second one, revert back the removal of the MAX_TCLK pin that was accidentaly removed while re-working commit 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the..."). Romain Perier (2): rockchip: rk3288: Remove phy reset GPIO pull up rockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMAC drivers/pinctrl/rockchip/pinctrl_rk3288.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.11.0

2 8

[U-Boot] [PATCH 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL
by Kever Yang 27 Jul '17

27 Jul '17

Lets set the all the DDR region as non secure in SPL, the trust like OPTEE should have the correct setting for it if there is one. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/mach-rockchip/rk322x-board-spl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 15216c7..aa8a742 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -41,6 +41,8 @@ static struct rk322x_grf * const grf = (void *)GRF_BASE; CON_IOMUX_UART2SEL_MASK, CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); } + +#define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) { struct udevice *dev; @@ -71,6 +73,7 @@ void board_init_f(ulong dummy) return; } + rk_clrreg(SGRF_DDR_CON0, 0x4000); #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif -- 1.9.1

3 17

[U-Boot] [PATCH v2 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL
by Kever Yang 27 Jul '17

27 Jul '17

Disable the ddr secure region setting in SPL and the ddr memory becomes non-secure, every one can access it. the trust firmware like OPTEE should have the correct setting for it after SPL if there is one. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v2: - add comment for the change and update the commit message arch/arm/mach-rockchip/rk322x-board-spl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 15216c7..4ddb8ba 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -41,6 +41,8 @@ static struct rk322x_grf * const grf = (void *)GRF_BASE; CON_IOMUX_UART2SEL_MASK, CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); } + +#define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) { struct udevice *dev; @@ -71,6 +73,8 @@ void board_init_f(ulong dummy) return; } + /* Disable the ddr secure region setting to make it non-secure */ + rk_clrreg(SGRF_DDR_CON0, 0x4000); #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif -- 1.9.1

1 3