July 2017 - U-Boot

[U-Boot] [PATCH v2] Add support for Microchip LAN75xx and LAN78xx
by Yuiko.Oshino＠microchip.com 27 Jul '17

27 Jul '17

From: Yuiko Oshino <yuiko.oshino(a)microchip.com> Add support for Microchip LAN7500, LAN7800 and LAN7850, USB to 10/100/1000 Ethernet Controllers Signed-off-by: Yuiko Oshino <yuiko.oshino(a)microchip.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> --- Changes for v2: - wait_for_bit functions copy the real one. - uses phylib - unnecessary variables were removed - all return values are checked - uses mii_resolve_flowctrl_fdx() from linux/mii.h ([PATCH] mii: Add mii_resolve_flowctrl_fdx() submitted on June 26, 2017) --- drivers/usb/Kconfig | 2 + drivers/usb/eth/Kconfig | 18 ++ drivers/usb/eth/Makefile | 2 + drivers/usb/eth/lan75xx.c | 320 +++++++++++++++++++++++++++++ drivers/usb/eth/lan78xx.c | 479 +++++++++++++++++++++++++++++++++++++++++++ drivers/usb/eth/lan7x.c | 506 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/eth/lan7x.h | 232 +++++++++++++++++++++ 7 files changed, 1559 insertions(+) create mode 100644 drivers/usb/eth/Kconfig create mode 100644 drivers/usb/eth/lan75xx.c create mode 100644 drivers/usb/eth/lan78xx.c create mode 100644 drivers/usb/eth/lan7x.c create mode 100644 drivers/usb/eth/lan7x.h diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index da3ec2f..62126aa 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -94,4 +94,6 @@ endif source "drivers/usb/gadget/Kconfig" +source "drivers/usb/eth/Kconfig" + endif diff --git a/drivers/usb/eth/Kconfig b/drivers/usb/eth/Kconfig new file mode 100644 index 0000000..a07243f --- /dev/null +++ b/drivers/usb/eth/Kconfig @@ -0,0 +1,18 @@ +comment "USB to Ethernet Controller Drivers" + +config USB_ETHER_LAN75XX + bool "Microchip LAN75XX support" + ---help--- + Say Y here if you would like to support Microchip LAN75XX Hi-Speed + USB 2.0 to 10/100/1000 Gigabit Ethernet controller. + Supports 10Base-T/ 100Base-TX/1000Base-T. + This driver supports the internal PHY. + +config USB_ETHER_LAN78XX + bool "Microchip LAN78XX support" + ---help--- + Say Y here if you would like to support Microchip LAN78XX USB 3.1 + Gen 1 to 10/100/1000 Gigabit Ethernet controller. + Supports 10Base-T/ 100Base-TX/1000Base-T. + This driver supports the internal PHY. + diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile index 4c44efc..4b935a3 100644 --- a/drivers/usb/eth/Makefile +++ b/drivers/usb/eth/Makefile @@ -9,4 +9,6 @@ obj-$(CONFIG_USB_ETHER_ASIX) += asix.o obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o +obj-$(CONFIG_USB_ETHER_LAN75XX) += lan7x.o lan75xx.o +obj-$(CONFIG_USB_ETHER_LAN78XX) += lan7x.o lan78xx.o obj-$(CONFIG_USB_ETHER_RTL8152) += r8152.o r8152_fw.o diff --git a/drivers/usb/eth/lan75xx.c b/drivers/usb/eth/lan75xx.c new file mode 100644 index 0000000..8ac7784 --- /dev/null +++ b/drivers/usb/eth/lan75xx.c @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <usb.h> +#include <linux/mii.h> +#include "usb_ether.h" +#include "lan7x.h" + +/* LAN75xx specific register/bit defines */ +#define LAN75XX_HW_CFG_BIR BIT(7) + +#define LAN75XX_BURST_CAP 0x034 + +#define LAN75XX_BULK_IN_DLY 0x03C + +#define LAN75XX_RFE_CTL 0x060 + +#define LAN75XX_FCT_RX_CTL 0x090 + +#define LAN75XX_FCT_TX_CTL 0x094 + +#define LAN75XX_FCT_RX_FIFO_END 0x098 + +#define LAN75XX_FCT_TX_FIFO_END 0x09C + +#define LAN75XX_FCT_FLOW 0x0A0 + +/* MAC ADDRESS PERFECT FILTER For LAN75xx */ +#define LAN75XX_ADDR_FILTX 0x300 +#define LAN75XX_ADDR_FILTX_FB_VALID BIT(31) + +/* + * Lan75xx infrastructure commands + */ +static int lan75xx_phy_gig_workaround(struct usb_device *udev, + struct ueth_data *dev) +{ + int ret = 0; + + /* Only internal phy */ + /* Set the phy in Gig loopback */ + lan7x_mdio_write(udev, dev->phy_id, MII_BMCR, + (BMCR_LOOPBACK | BMCR_SPEED1000)); + + /* Wait for the link up */ + ret = lan7x_mdio_wait_for_bit(udev, "BMSR_LSTATUS", + dev->phy_id, MII_BMSR, BMSR_LSTATUS, + true, PHY_CONNECT_TIMEOUT_MS, 1); + if (ret) + return ret; + + /* phy reset */ + return lan7x_pmt_phy_reset(udev, dev); +} + +static int lan75xx_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev) +{ + uint32_t flow = 0, fct_flow = 0; + int ret; + + ret = lan7x_update_flowcontrol(udev, dev, &flow, &fct_flow); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_FCT_FLOW, fct_flow); + if (ret) + return ret; + return lan7x_write_reg(udev, FLOW, flow); +} + +static int lan75xx_read_mac(unsigned char *enetaddr, + struct usb_device *udev) +{ + /* + * Refer to the doc/README.enetaddr and doc/README.usb for + * the U-Boot MAC address policy + */ + return lan7x_read_eeprom_mac(enetaddr, udev); +} + +static int lan75xx_set_receive_filter(struct usb_device *udev) +{ + /* No multicast in u-boot */ + return lan7x_write_reg(udev, LAN75XX_RFE_CTL, + RFE_CTL_BCAST_EN | RFE_CTL_DA_PERFECT); +} + +/* starts the TX path */ +static void lan75xx_start_tx_path(struct usb_device *udev) +{ + /* Enable Tx at MAC */ + lan7x_write_reg(udev, MAC_TX, MAC_TX_TXEN); + + /* Enable Tx at SCSRs */ + lan7x_write_reg(udev, LAN75XX_FCT_TX_CTL, FCT_TX_CTL_EN); +} + +/* Starts the Receive path */ +static void lan75xx_start_rx_path(struct usb_device *udev) +{ + /* Enable Rx at MAC */ + lan7x_write_reg(udev, MAC_RX, + LAN7X_MAC_RX_MAX_SIZE_DEFAULT | + MAC_RX_FCS_STRIP | MAC_RX_RXEN); + + /* Enable Rx at SCSRs */ + lan7x_write_reg(udev, LAN75XX_FCT_RX_CTL, FCT_RX_CTL_EN); +} + +static int lan75xx_basic_reset(struct usb_device *udev, + struct ueth_data *dev, + struct lan7x_private *priv) +{ + int ret; + u32 val; + + ret = lan7x_basic_reset(udev, dev); + if (ret) + return ret; + + /* Keep the chip ID */ + ret = lan7x_read_reg(udev, ID_REV, &val); + if (ret) + return ret; + debug("LAN75xx ID_REV = 0x%08x\n", val); + + priv->chipid = (val & ID_REV_CHIP_ID_MASK) >> 16; + + /* Respond to the IN token with a NAK */ + ret = lan7x_read_reg(udev, HW_CFG, &val); + if (ret) + return ret; + val |= LAN75XX_HW_CFG_BIR; + return lan7x_write_reg(udev, HW_CFG, val); +} + +#ifdef CONFIG_DM_ETH +int lan75xx_write_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + unsigned char *enetaddr = pdata->enetaddr; + u32 addr_lo = get_unaligned_le32(&enetaddr[0]); + u32 addr_hi = (u32)get_unaligned_le16(&enetaddr[4]); + int ret; + + /* set hardware address */ + ret = lan7x_write_reg(udev, RX_ADDRL, addr_lo); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, RX_ADDRH, addr_hi); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_ADDR_FILTX + 4, addr_lo); + if (ret) + return ret; + + addr_hi |= LAN75XX_ADDR_FILTX_FB_VALID; + ret = lan7x_write_reg(udev, LAN75XX_ADDR_FILTX, addr_hi); + if (ret) + return ret; + + debug("MAC addr %pM written\n", enetaddr); + + return 0; +} + +static int lan75xx_eth_start(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + int ret; + u32 write_buf; + + /* Reset and read Mac addr were done in probe() */ + ret = lan75xx_write_hwaddr(dev); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, INT_STS, 0xFFFFFFFF); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_BURST_CAP, 0); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); + if (ret) + return ret; + + /* set FIFO sizes */ + write_buf = (MAX_RX_FIFO_SIZE - 512) / 512; + ret = lan7x_write_reg(udev, LAN75XX_FCT_RX_FIFO_END, write_buf); + if (ret) + return ret; + + write_buf = (MAX_TX_FIFO_SIZE - 512) / 512; + ret = lan7x_write_reg(udev, LAN75XX_FCT_TX_FIFO_END, write_buf); + if (ret) + return ret; + + /* Init Tx */ + ret = lan7x_write_reg(udev, FLOW, 0); + if (ret) + return ret; + + /* Init Rx. Set Vlan, keep defult for VLAN on 75xx */ + ret = lan75xx_set_receive_filter(udev); + if (ret) + return ret; + + /* phy workaround for gig link */ + ret = lan75xx_phy_gig_workaround(udev, ueth); + if (ret) + return ret; + + /* Init PHY, autonego, and link */ + ret = lan7x_eth_phylib_connect(dev, &priv->ueth); + if (ret) + return ret; + ret = lan7x_eth_phylib_config_start(dev); + if (ret) + return ret; + + /* + * MAC_CR has to be set after PHY init. + * MAC will auto detect the PHY speed. + */ + ret = lan7x_read_reg(udev, MAC_CR, &write_buf); + if (ret) + return ret; + write_buf |= MAC_CR_AUTO_DUPLEX | MAC_CR_AUTO_SPEED | MAC_CR_ADP; + ret = lan7x_write_reg(udev, MAC_CR, write_buf); + if (ret) + return ret; + + lan75xx_start_tx_path(udev); + lan75xx_start_rx_path(udev); + + return lan75xx_update_flowcontrol(udev, ueth); +} + +int lan75xx_read_rom_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + ret = lan75xx_read_mac(pdata->enetaddr, udev); + if (ret) + memset(pdata->enetaddr, 0, 6); + + return 0; +} + +static int lan75xx_eth_probe(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + struct eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + /* Do a reset in order to get the MAC address from HW */ + if (lan75xx_basic_reset(udev, ueth, priv)) + return 0; + + /* Get the MAC address */ + /* + * We must set the eth->enetaddr from HW because the upper layer + * will force to use the environmental var (usbethaddr) or random if + * there is no valid MAC address in eth->enetaddr. + */ + lan75xx_read_mac(pdata->enetaddr, udev); + /* Do not return 0 for not finding MAC addr in HW */ + + ret = usb_ether_register(dev, ueth, RX_URB_SIZE); + if (ret) + return ret; + + /* Register phylib */ + return lan7x_phylib_register(dev); +} + +static const struct eth_ops lan75xx_eth_ops = { + .start = lan75xx_eth_start, + .send = lan7x_eth_send, + .recv = lan7x_eth_recv, + .free_pkt = lan7x_free_pkt, + .stop = lan7x_eth_stop, + .write_hwaddr = lan75xx_write_hwaddr, + .read_rom_hwaddr = lan75xx_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(lan75xx_eth) = { + .name = "lan75xx_eth", + .id = UCLASS_ETH, + .probe = lan75xx_eth_probe, + .remove = lan7x_eth_remove, + .ops = &lan75xx_eth_ops, + .priv_auto_alloc_size = sizeof(struct lan7x_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +static const struct usb_device_id lan75xx_eth_id_table[] = { + { USB_DEVICE(0x0424, 0x7500) }, /* LAN7500 USB Ethernet */ + { } /* Terminating entry */ +}; + +U_BOOT_USB_DEVICE(lan75xx_eth, lan75xx_eth_id_table); +#endif diff --git a/drivers/usb/eth/lan78xx.c b/drivers/usb/eth/lan78xx.c new file mode 100644 index 0000000..5160db7 --- /dev/null +++ b/drivers/usb/eth/lan78xx.c @@ -0,0 +1,479 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <usb.h> +#include "usb_ether.h" +#include "lan7x.h" + +/* LAN78xx specific register/bit defines */ +#define LAN78XX_HW_CFG_LED1_EN BIT(21) /* Muxed with EEDO */ +#define LAN78XX_HW_CFG_LED0_EN BIT(20) /* Muxed with EECLK */ + +#define LAN78XX_USB_CFG0 0x080 +#define LAN78XX_USB_CFG0_BIR BIT(6) + +#define LAN78XX_BURST_CAP 0x090 + +#define LAN78XX_BULK_IN_DLY 0x094 + +#define LAN78XX_RFE_CTL 0x0B0 + +#define LAN78XX_FCT_RX_CTL 0x0C0 + +#define LAN78XX_FCT_TX_CTL 0x0C4 + +#define LAN78XX_FCT_RX_FIFO_END 0x0C8 + +#define LAN78XX_FCT_TX_FIFO_END 0x0CC + +#define LAN78XX_FCT_FLOW 0x0D0 + +#define LAN78XX_MAF_BASE 0x400 +#define LAN78XX_MAF_HIX 0x00 +#define LAN78XX_MAF_LOX 0x04 +#define LAN78XX_MAF_HI_BEGIN (LAN78XX_MAF_BASE + LAN78XX_MAF_HIX) +#define LAN78XX_MAF_LO_BEGIN (LAN78XX_MAF_BASE + LAN78XX_MAF_LOX) +#define LAN78XX_MAF_HI(index) (LAN78XX_MAF_BASE + (8 * (index)) + \ + LAN78XX_MAF_HIX) +#define LAN78XX_MAF_LO(index) (LAN78XX_MAF_BASE + (8 * (index)) + \ + LAN78XX_MAF_LOX) +#define LAN78XX_MAF_HI_VALID BIT(31) + +/* OTP registers */ +#define LAN78XX_OTP_BASE_ADDR 0x00001000 + +#define LAN78XX_OTP_PWR_DN (LAN78XX_OTP_BASE_ADDR + 4 * 0x00) +#define LAN78XX_OTP_PWR_DN_PWRDN_N BIT(0) + +#define LAN78XX_OTP_ADDR1 (LAN78XX_OTP_BASE_ADDR + 4 * 0x01) +#define LAN78XX_OTP_ADDR1_15_11 0x1F + +#define LAN78XX_OTP_ADDR2 (LAN78XX_OTP_BASE_ADDR + 4 * 0x02) +#define LAN78XX_OTP_ADDR2_10_3 0xFF + +#define LAN78XX_OTP_RD_DATA (LAN78XX_OTP_BASE_ADDR + 4 * 0x06) + +#define LAN78XX_OTP_FUNC_CMD (LAN78XX_OTP_BASE_ADDR + 4 * 0x08) +#define LAN78XX_OTP_FUNC_CMD_READ BIT(0) + +#define LAN78XX_OTP_CMD_GO (LAN78XX_OTP_BASE_ADDR + 4 * 0x0A) +#define LAN78XX_OTP_CMD_GO_GO BIT(0) + +#define LAN78XX_OTP_STATUS (LAN78XX_OTP_BASE_ADDR + 4 * 0x0C) +#define LAN78XX_OTP_STATUS_BUSY BIT(0) + +#define LAN78XX_OTP_INDICATOR_1 0xF3 +#define LAN78XX_OTP_INDICATOR_2 0xF7 + +/* + * Lan78xx infrastructure commands + */ +static int lan78xx_read_raw_otp(struct usb_device *udev, u32 offset, + u32 length, u8 *data) +{ + int i; + int ret; + u32 buf; + + ret = lan7x_read_reg(udev, LAN78XX_OTP_PWR_DN, &buf); + if (ret) + return ret; + + if (buf & LAN78XX_OTP_PWR_DN_PWRDN_N) { + /* clear it and wait to be cleared */ + ret = lan7x_write_reg(udev, LAN78XX_OTP_PWR_DN, 0); + if (ret) + return ret; + + ret = lan7x_wait_for_bit(udev, "LAN78XX_OTP_PWR_DN_PWRDN_N", + LAN78XX_OTP_PWR_DN, + LAN78XX_OTP_PWR_DN_PWRDN_N, + false, 1000, 0); + if (ret) + return ret; + } + + for (i = 0; i < length; i++) { + ret = lan7x_write_reg(udev, LAN78XX_OTP_ADDR1, + ((offset + i) >> 8) & + LAN78XX_OTP_ADDR1_15_11); + if (ret) + return ret; + ret = lan7x_write_reg(udev, LAN78XX_OTP_ADDR2, + ((offset + i) & LAN78XX_OTP_ADDR2_10_3)); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_OTP_FUNC_CMD, + LAN78XX_OTP_FUNC_CMD_READ); + if (ret) + return ret; + ret = lan7x_write_reg(udev, LAN78XX_OTP_CMD_GO, + LAN78XX_OTP_CMD_GO_GO); + + if (ret) + return ret; + + ret = lan7x_wait_for_bit(udev, "LAN78XX_OTP_STATUS_BUSY", + LAN78XX_OTP_STATUS, + LAN78XX_OTP_STATUS_BUSY, + false, 1000, 0); + if (ret) + return ret; + + ret = lan7x_read_reg(udev, LAN78XX_OTP_RD_DATA, &buf); + if (ret) + return ret; + + data[i] = (u8)(buf & 0xFF); + } + + return 0; +} + +static int lan78xx_read_otp(struct usb_device *udev, u32 offset, + u32 length, u8 *data) +{ + u8 sig; + int ret; + + ret = lan78xx_read_raw_otp(udev, 0, 1, &sig); + + if (!ret) { + if (sig == LAN78XX_OTP_INDICATOR_1) + offset = offset; + else if (sig == LAN78XX_OTP_INDICATOR_2) + offset += 0x100; + else + return -EINVAL; + ret = lan78xx_read_raw_otp(udev, offset, length, data); + if (ret) + return ret; + } + debug("LAN78x: MAC address from OTP = %pM\n", data); + + return ret; +} + +static int lan78xx_read_otp_mac(unsigned char *enetaddr, + struct usb_device *udev) +{ + int ret; + + memset(enetaddr, 0, 6); + + ret = lan78xx_read_otp(udev, + EEPROM_MAC_OFFSET, + ETH_ALEN, + enetaddr); + if (!ret && is_valid_ethaddr(enetaddr)) { + /* eeprom values are valid so use them */ + debug("MAC address read from OTP %pM\n", enetaddr); + return 0; + } + debug("MAC address read from OTP invalid %pM\n", enetaddr); + + memset(enetaddr, 0, 6); + return -EINVAL; +} + +static int lan78xx_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev) +{ + uint32_t flow = 0, fct_flow = 0; + int ret; + + ret = lan7x_update_flowcontrol(udev, dev, &flow, &fct_flow); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_FCT_FLOW, fct_flow); + if (ret) + return ret; + return lan7x_write_reg(udev, FLOW, flow); +} + +static int lan78xx_read_mac(unsigned char *enetaddr, + struct usb_device *udev, + struct lan7x_private *priv) +{ + u32 val; + int ret; + int saved = 0, done = 0; + + /* + * Depends on chip, some EEPROM pins are muxed with LED function. + * disable & restore LED function to access EEPROM. + */ + if ((priv->chipid == ID_REV_CHIP_ID_7800) || + (priv->chipid == ID_REV_CHIP_ID_7850)) { + ret = lan7x_read_reg(udev, HW_CFG, &val); + if (ret) + return ret; + saved = val; + val &= ~(LAN78XX_HW_CFG_LED1_EN | LAN78XX_HW_CFG_LED0_EN); + ret = lan7x_write_reg(udev, HW_CFG, val); + if (ret) + goto restore; + } + + /* + * Refer to the doc/README.enetaddr and doc/README.usb for + * the U-Boot MAC address policy + */ + /* try reading mac address from EEPROM, then from OTP */ + ret = lan7x_read_eeprom_mac(enetaddr, udev); + if (!ret) + done = 1; + +restore: + if ((priv->chipid == ID_REV_CHIP_ID_7800) || + (priv->chipid == ID_REV_CHIP_ID_7850)) { + ret = lan7x_write_reg(udev, HW_CFG, saved); + if (ret) + return ret; + } + /* if the EEPROM mac address is good, then exit */ + if (done) + return 0; + + /* try reading mac address from OTP if the device is LAN78xx */ + return lan78xx_read_otp_mac(enetaddr, udev); +} + +static int lan78xx_set_receive_filter(struct usb_device *udev) +{ + /* No multicast in u-boot for now */ + return lan7x_write_reg(udev, LAN78XX_RFE_CTL, + RFE_CTL_BCAST_EN | RFE_CTL_DA_PERFECT); +} + +/* starts the TX path */ +static void lan78xx_start_tx_path(struct usb_device *udev) +{ + /* Enable Tx at MAC */ + lan7x_write_reg(udev, MAC_TX, MAC_TX_TXEN); + + /* Enable Tx at SCSRs */ + lan7x_write_reg(udev, LAN78XX_FCT_TX_CTL, FCT_TX_CTL_EN); +} + +/* Starts the Receive path */ +static void lan78xx_start_rx_path(struct usb_device *udev) +{ + /* Enable Rx at MAC */ + lan7x_write_reg(udev, MAC_RX, + LAN7X_MAC_RX_MAX_SIZE_DEFAULT | + MAC_RX_FCS_STRIP | MAC_RX_RXEN); + + /* Enable Rx at SCSRs */ + lan7x_write_reg(udev, LAN78XX_FCT_RX_CTL, FCT_RX_CTL_EN); +} + +static int lan78xx_basic_reset(struct usb_device *udev, + struct ueth_data *dev, + struct lan7x_private *priv) +{ + int ret; + u32 val; + + ret = lan7x_basic_reset(udev, dev); + if (ret) + return ret; + + /* Keep the chip ID */ + ret = lan7x_read_reg(udev, ID_REV, &val); + if (ret) + return ret; + debug("LAN78xx ID_REV = 0x%08x\n", val); + + priv->chipid = (val & ID_REV_CHIP_ID_MASK) >> 16; + + /* Respond to the IN token with a NAK */ + ret = lan7x_read_reg(udev, LAN78XX_USB_CFG0, &val); + if (ret) + return ret; + val |= LAN78XX_USB_CFG0_BIR; + return lan7x_write_reg(udev, LAN78XX_USB_CFG0, val); +} + +#ifdef CONFIG_DM_ETH +int lan78xx_write_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + unsigned char *enetaddr = pdata->enetaddr; + u32 addr_lo = get_unaligned_le32(&enetaddr[0]); + u32 addr_hi = (u32)get_unaligned_le16(&enetaddr[4]); + int ret; + + /* set hardware address */ + ret = lan7x_write_reg(udev, RX_ADDRL, addr_lo); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, RX_ADDRH, addr_hi); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_MAF_LO(0), addr_lo); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_MAF_HI(0), + addr_hi | LAN78XX_MAF_HI_VALID); + if (ret) + return ret; + + debug("MAC addr %pM written\n", enetaddr); + + return 0; +} + +static int lan78xx_eth_start(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + + int ret; + u32 write_buf; + + /* Reset and read Mac addr were done in probe() */ + ret = lan78xx_write_hwaddr(dev); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_BURST_CAP, 0); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, INT_STS, 0xFFFFFFFF); + if (ret) + return ret; + + /* set FIFO sizes */ + ret = lan7x_write_reg(udev, LAN78XX_FCT_RX_FIFO_END, + (MAX_RX_FIFO_SIZE - 512) / 512); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_FCT_TX_FIFO_END, + (MAX_TX_FIFO_SIZE - 512) / 512); + if (ret) + return ret; + + /* Init Tx */ + ret = lan7x_write_reg(udev, FLOW, 0); + if (ret) + return ret; + + /* Init Rx. Set Vlan, keep defult for VLAN on 78xx */ + ret = lan78xx_set_receive_filter(udev); + if (ret) + return ret; + + /* Init PHY, autonego, and link */ + ret = lan7x_eth_phylib_connect(dev, &priv->ueth); + if (ret) + return ret; + ret = lan7x_eth_phylib_config_start(dev); + if (ret) + return ret; + + /* + * MAC_CR has to be set after PHY init. + * MAC will auto detect the PHY speed. + */ + ret = lan7x_read_reg(udev, MAC_CR, &write_buf); + if (ret) + return ret; + write_buf |= MAC_CR_AUTO_DUPLEX | MAC_CR_AUTO_SPEED | MAC_CR_ADP; + ret = lan7x_write_reg(udev, MAC_CR, write_buf); + if (ret) + return ret; + + lan78xx_start_tx_path(udev); + lan78xx_start_rx_path(udev); + + return lan78xx_update_flowcontrol(udev, &priv->ueth); +} + +int lan78xx_read_rom_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct lan7x_private *priv = dev_get_priv(dev); + int ret; + + ret = lan78xx_read_mac(pdata->enetaddr, udev, priv); + if (ret) + memset(pdata->enetaddr, 0, 6); + + return 0; +} + +static int lan78xx_eth_probe(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + struct eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + /* Do a reset in order to get the MAC address from HW */ + if (lan78xx_basic_reset(udev, ueth, priv)) + return 0; + + /* Get the MAC address */ + /* + * We must set the eth->enetaddr from HW because the upper layer + * will force to use the environmental var (usbethaddr) or random if + * there is no valid MAC address in eth->enetaddr. + */ + lan78xx_read_mac(pdata->enetaddr, udev, priv); + /* Do not return 0 for not finding MAC addr in HW */ + + ret = usb_ether_register(dev, ueth, RX_URB_SIZE); + if (ret) + return ret; + + /* Register phylib */ + return lan7x_phylib_register(dev); +} + +static const struct eth_ops lan78xx_eth_ops = { + .start = lan78xx_eth_start, + .send = lan7x_eth_send, + .recv = lan7x_eth_recv, + .free_pkt = lan7x_free_pkt, + .stop = lan7x_eth_stop, + .write_hwaddr = lan78xx_write_hwaddr, + .read_rom_hwaddr = lan78xx_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(lan78xx_eth) = { + .name = "lan78xx_eth", + .id = UCLASS_ETH, + .probe = lan78xx_eth_probe, + .remove = lan7x_eth_remove, + .ops = &lan78xx_eth_ops, + .priv_auto_alloc_size = sizeof(struct lan7x_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +static const struct usb_device_id lan78xx_eth_id_table[] = { + { USB_DEVICE(0x0424, 0x7800) }, /* LAN7800 USB Ethernet */ + { USB_DEVICE(0x0424, 0x7850) }, /* LAN7850 USB Ethernet */ + { } /* Terminating entry */ +}; + +U_BOOT_USB_DEVICE(lan78xx_eth, lan78xx_eth_id_table); +#endif diff --git a/drivers/usb/eth/lan7x.c b/drivers/usb/eth/lan7x.c new file mode 100644 index 0000000..a2ebbeb --- /dev/null +++ b/drivers/usb/eth/lan7x.c @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <malloc.h> +#include <miiphy.h> +#include <memalign.h> +#include <usb.h> +#include <linux/ethtool.h> +#include <linux/mii.h> +#include "usb_ether.h" +#include "lan7x.h" + +/* + * Lan7x infrastructure commands + */ +int lan7x_write_reg(struct usb_device *udev, u32 index, u32 data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); + + cpu_to_le32s(&data); + tmpbuf[0] = data; + + len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + USB_VENDOR_REQUEST_WRITE_REGISTER, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0, index, tmpbuf, sizeof(data), + USB_CTRL_SET_TIMEOUT_MS); + if (len != sizeof(data)) { + debug("%s failed: index=%d, data=%d, len=%d", + __func__, index, data, len); + return -EIO; + } + return 0; +} + +int lan7x_read_reg(struct usb_device *udev, u32 index, u32 *data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); + + len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + USB_VENDOR_REQUEST_READ_REGISTER, + USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0, index, tmpbuf, sizeof(*data), + USB_CTRL_GET_TIMEOUT_MS); + *data = tmpbuf[0]; + if (len != sizeof(*data)) { + debug("%s failed: index=%d, len=%d", __func__, index, len); + return -EIO; + } + + le32_to_cpus(data); + return 0; +} + +static int lan7x_phy_wait_not_busy(struct usb_device *udev) +{ + return lan7x_wait_for_bit(udev, __func__, + MII_ACC, MII_ACC_MII_BUSY, + false, 100, 0); +} + +int lan7x_mdio_read(struct usb_device *udev, int phy_id, int idx) +{ + u32 val, addr; + + /* confirm MII not busy */ + if (lan7x_phy_wait_not_busy(udev)) { + debug("MII is busy in %s\n", __func__); + return -ETIMEDOUT; + } + + /* set the address, index & direction (read from PHY) */ + addr = (phy_id << 11) | (idx << 6) | + MII_ACC_MII_READ | MII_ACC_MII_BUSY; + lan7x_write_reg(udev, MII_ACC, addr); + + if (lan7x_phy_wait_not_busy(udev)) { + debug("Timed out reading MII reg %02X\n", idx); + return -ETIMEDOUT; + } + + lan7x_read_reg(udev, MII_DATA, &val); + + return val & 0xFFFF; +} + +void lan7x_mdio_write(struct usb_device *udev, int phy_id, int idx, int regval) +{ + u32 addr; + + /* confirm MII not busy */ + if (lan7x_phy_wait_not_busy(udev)) { + debug("MII is busy in %s\n", __func__); + return; + } + + lan7x_write_reg(udev, MII_DATA, regval); + + /* set the address, index & direction (write to PHY) */ + addr = (phy_id << 11) | (idx << 6) | + MII_ACC_MII_WRITE | MII_ACC_MII_BUSY; + lan7x_write_reg(udev, MII_ACC, addr); + + if (lan7x_phy_wait_not_busy(udev)) + debug("Timed out writing MII reg %02X\n", idx); +} + +/* + * Lan7x phylib wrappers + */ +static int lan7x_phylib_mdio_read(struct mii_dev *bus, + int addr, int devad, int reg) +{ + struct usb_device *udev = dev_get_parent_priv(bus->priv); + + return lan7x_mdio_read(udev, addr, reg); +} + +static int lan7x_phylib_mdio_write(struct mii_dev *bus, + int addr, int devad, int reg, u16 val) +{ + struct usb_device *udev = dev_get_parent_priv(bus->priv); + + lan7x_mdio_write(udev, addr, reg, (int)val); + + return 0; +} + +/* + * Lan7x eeprom functions + */ +static int lan7x_eeprom_confirm_not_busy(struct usb_device *udev) +{ + return lan7x_wait_for_bit(udev, __func__, + E2P_CMD, E2P_CMD_EPC_BUSY, + false, 100, 0); +} + +static int lan7x_wait_eeprom(struct usb_device *udev) +{ + return lan7x_wait_for_bit(udev, __func__, + E2P_CMD, + (E2P_CMD_EPC_BUSY | E2P_CMD_EPC_TIMEOUT), + false, 100, 0); +} + +static int lan7x_read_eeprom(struct usb_device *udev, + u32 offset, u32 length, u8 *data) +{ + u32 val; + int i, ret; + + ret = lan7x_eeprom_confirm_not_busy(udev); + if (ret) + return ret; + + for (i = 0; i < length; i++) { + val = E2P_CMD_EPC_BUSY | E2P_CMD_EPC_CMD_READ | + (offset & E2P_CMD_EPC_ADDR_MASK); + lan7x_write_reg(udev, E2P_CMD, val); + + ret = lan7x_wait_eeprom(udev); + if (ret) + return ret; + + lan7x_read_reg(udev, E2P_DATA, &val); + data[i] = val & 0xFF; + offset++; + } + return ret; +} + +/* + * Lan7x phylib functions + */ +int lan7x_phylib_register(struct udevice *udev) +{ + struct lan7x_private *priv = dev_get_priv(udev); + int ret; + + priv->mdiobus = mdio_alloc(); + if (!priv->mdiobus) { + printf("mdio_alloc failed\n"); + return -ENOMEM; + } + priv->mdiobus->read = lan7x_phylib_mdio_read; + priv->mdiobus->write = lan7x_phylib_mdio_write; + strcpy(priv->mdiobus->name, "lan78x_mdiobus"); + priv->mdiobus->priv = (void *)udev; + + ret = mdio_register(priv->mdiobus); + if (ret) { + printf("mdio_register failed\n"); + free(priv->mdiobus); + return -ENOMEM; + } + + return 0; +} + +int lan7x_eth_phylib_connect(struct udevice *udev, struct ueth_data *dev) +{ + struct lan7x_private *priv = dev_get_priv(udev); + + priv->phydev = phy_connect(priv->mdiobus, dev->phy_id, + udev, PHY_INTERFACE_MODE_MII); + + if (!priv->phydev) { + printf("phy_connect failed\n"); + return -ENODEV; + } + return 0; +} + +int lan7x_eth_phylib_config_start(struct udevice *udev) +{ + struct lan7x_private *priv = dev_get_priv(udev); + int ret; + + /* configure supported modes */ + priv->phydev->supported = PHY_BASIC_FEATURES | + SUPPORTED_1000baseT_Full | + SUPPORTED_Pause | + SUPPORTED_Asym_Pause; + + priv->phydev->advertising = ADVERTISED_10baseT_Half | + ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | + ADVERTISED_100baseT_Full | + ADVERTISED_1000baseT_Full | + ADVERTISED_Pause | + ADVERTISED_Asym_Pause | + ADVERTISED_Autoneg; + + priv->phydev->autoneg = AUTONEG_ENABLE; + + ret = genphy_config_aneg(priv->phydev); + if (ret) { + printf("genphy_config_aneg failed\n"); + return ret; + } + ret = phy_startup(priv->phydev); + if (ret) { + printf("phy_startup failed\n"); + return ret; + } + + debug("** %s() speed %i duplex %i adv %X supp %X\n", __func__, + priv->phydev->speed, priv->phydev->duplex, + priv->phydev->advertising, priv->phydev->supported); + + return 0; +} + +int lan7x_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev, + uint32_t *flow, uint32_t *fct_flow) +{ + uint32_t lcladv, rmtadv; + u8 cap = 0; + struct lan7x_private *priv = dev_get_priv(udev->dev); + + debug("** %s()\n", __func__); + debug("** %s() priv->phydev->speed %i duplex %i\n", __func__, + priv->phydev->speed, priv->phydev->duplex); + + if (priv->phydev->duplex == DUPLEX_FULL) { + lcladv = lan7x_mdio_read(udev, dev->phy_id, MII_ADVERTISE); + rmtadv = lan7x_mdio_read(udev, dev->phy_id, MII_LPA); + cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); + + debug("TX Flow "); + if (cap & FLOW_CTRL_TX) { + *flow = (FLOW_CR_TX_FCEN | 0xFFFF); + /* set fct_flow thresholds to 20% and 80% */ + *fct_flow = ((MAX_RX_FIFO_SIZE * 2) / (10 * 512)) + & 0x7FUL; + *fct_flow <<= 8UL; + *fct_flow |= ((MAX_RX_FIFO_SIZE * 8) / (10 * 512)) + & 0x7FUL; + debug("EN "); + } else { + debug("DIS "); + } + debug("RX Flow "); + if (cap & FLOW_CTRL_RX) { + *flow |= FLOW_CR_RX_FCEN; + debug("EN"); + } else { + debug("DIS"); + } + } + debug("\n"); + return 0; +} + +int lan7x_read_eeprom_mac(unsigned char *enetaddr, struct usb_device *udev) +{ + int ret; + + memset(enetaddr, 0, 6); + + ret = lan7x_read_eeprom(udev, 0, 1, enetaddr); + + if ((ret == 0) && (enetaddr[0] == EEPROM_INDICATOR)) { + ret = lan7x_read_eeprom(udev, + EEPROM_MAC_OFFSET, ETH_ALEN, + enetaddr); + if ((ret == 0) && is_valid_ethaddr(enetaddr)) { + /* eeprom values are valid so use them */ + debug("MAC address read from EEPROM %pM\n", + enetaddr); + return 0; + } + } + debug("MAC address read from EEPROM invalid %pM\n", enetaddr); + + memset(enetaddr, 0, 6); + return -EINVAL; +} + +int lan7x_pmt_phy_reset(struct usb_device *udev, + struct ueth_data *dev) +{ + int ret; + u32 data; + + ret = lan7x_read_reg(udev, PMT_CTL, &data); + if (ret) + return ret; + ret = lan7x_write_reg(udev, PMT_CTL, data | PMT_CTL_PHY_RST); + if (ret) + return ret; + + /* for LAN7x, we need to check PMT_CTL_READY asserted */ + ret = lan7x_wait_for_bit(udev, "PMT_CTL_PHY_RST", + PMT_CTL, PMT_CTL_PHY_RST, + false, 1000, 0); /* could take over 125mS */ + if (ret) + return ret; + + return lan7x_wait_for_bit(udev, "PMT_CTL_READY", + PMT_CTL, PMT_CTL_READY, + true, 1000, 0); +} + +int lan7x_basic_reset(struct usb_device *udev, + struct ueth_data *dev) +{ + int ret; + + dev->phy_id = LAN7X_INTERNAL_PHY_ID; /* fixed phy id */ + + ret = lan7x_write_reg(udev, HW_CFG, HW_CFG_LRST); + if (ret) + return ret; + + ret = lan7x_wait_for_bit(udev, "HW_CFG_LRST", + HW_CFG, HW_CFG_LRST, + false, 1000, 0); + if (ret) + return ret; + + return lan7x_pmt_phy_reset(udev, dev); +} + +#ifdef CONFIG_DM_ETH +void lan7x_eth_stop(struct udevice *dev) +{ + debug("** %s()\n", __func__); +} + +int lan7x_eth_send(struct udevice *dev, void *packet, int length) +{ + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + int err; + int actual_len; + u32 tx_cmd_a; + u32 tx_cmd_b; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, + PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); + + debug("** %s(), len %d, buf %#x\n", __func__, length, + (unsigned int)(ulong) msg); + if (length > PKTSIZE) + return -ENOSPC; + + /* LAN7x disable all TX offload features for u-boot */ + tx_cmd_a = (u32) (length & TX_CMD_A_LEN_MASK) | TX_CMD_A_FCS; + tx_cmd_b = 0; + cpu_to_le32s(&tx_cmd_a); + cpu_to_le32s(&tx_cmd_b); + + /* prepend cmd_a and cmd_b */ + memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); + memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); + memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, + length); + err = usb_bulk_msg(ueth->pusb_dev, + usb_sndbulkpipe(ueth->pusb_dev, ueth->ep_out), + (void *)msg, + length + sizeof(tx_cmd_a) + + sizeof(tx_cmd_b), + &actual_len, USB_BULK_SEND_TIMEOUT_MS); + debug("Tx: len = %u, actual = %u, err = %d\n", + (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)), + (unsigned int)actual_len, err); + + return err; +} + +int lan7x_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE); + unsigned char *buf_ptr; + int err; + int actual_len = 0; + u32 packet_len = 0; + u32 rx_cmd_a = 0; + + err = usb_bulk_msg(ueth->pusb_dev, + usb_rcvbulkpipe(ueth->pusb_dev, ueth->ep_in), + (void *)recv_buf, RX_URB_SIZE, &actual_len, + USB_BULK_RECV_TIMEOUT_MS); + + debug("Rx: RX_URB_SIZE = %u, actual = %u, err = %d\n", RX_URB_SIZE, + actual_len, err); + if (err != 0) { + debug("Rx: failed to receive\n"); + return err; + } + if (actual_len > RX_URB_SIZE) { + debug("Rx: received too many bytes %d\n", actual_len); + return -ENOSPC; + } + + buf_ptr = recv_buf; + + /* + * No multiple Ethernet Frames per USB Packet (MEF) used + * for the U-boot for now. + */ + if (actual_len > 0) { + if (actual_len < sizeof(rx_cmd_a)) { + debug("Rx: incomplete packet length\n"); + return -EIO; + } + memcpy(&rx_cmd_a, buf_ptr, sizeof(rx_cmd_a)); + le32_to_cpus(&rx_cmd_a); + if (rx_cmd_a & RX_CMD_A_RXE) { + debug("Rx: Error header=%#x", rx_cmd_a); + return -EIO; + } + packet_len = (u16) (rx_cmd_a & RX_CMD_A_LEN_MASK); + + if (packet_len > actual_len - sizeof(packet_len)) { + debug("Rx: too large packet: %d\n", packet_len); + return -EIO; + } + + /* + * For LAN7x, the length in command A does not + * include command A, B, and C length. + * So use it as is. + */ + + debug("Rx: cmd_a 0x%08X packet_len %d\n", rx_cmd_a, packet_len); + + /* Notify net stack */ + net_process_received_packet(buf_ptr + 10, packet_len); + } + + return err; +} + +int lan7x_free_pkt(struct udevice *dev, uchar *packet, int packet_len) +{ + struct lan7x_private *priv = dev_get_priv(dev); + + packet_len = ALIGN(packet_len, 4); + usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len); + + return 0; +} + +int lan7x_eth_remove(struct udevice *dev) +{ + struct lan7x_private *priv = dev_get_priv(dev); + + debug("** %s()\n", __func__); + free(priv->phydev); + mdio_unregister(priv->mdiobus); + mdio_free(priv->mdiobus); + + return 0; +} +#endif /* CONFIG_DM_ETH */ diff --git a/drivers/usb/eth/lan7x.h b/drivers/usb/eth/lan7x.h new file mode 100644 index 0000000..6f4647a --- /dev/null +++ b/drivers/usb/eth/lan7x.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <console.h> +#include <watchdog.h> + +/* USB Vendor Requests */ +#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 +#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 +#define USB_VENDOR_REQUEST_GET_STATS 0xA2 + +/* Tx Command A */ +#define TX_CMD_A_FCS BIT(22) +#define TX_CMD_A_LEN_MASK 0x000FFFFF + +/* Rx Command A */ +#define RX_CMD_A_RXE BIT(18) +#define RX_CMD_A_LEN_MASK 0x00003FFF + +/* SCSRs */ +#define ID_REV 0x00 +#define ID_REV_CHIP_ID_MASK 0xFFFF0000 +#define ID_REV_CHIP_ID_7500 0x7500 +#define ID_REV_CHIP_ID_7800 0x7800 +#define ID_REV_CHIP_ID_7850 0x7850 + +#define INT_STS 0x0C + +#define HW_CFG 0x010 +#define HW_CFG_LRST BIT(1) + +#define PMT_CTL 0x014 +#define PMT_CTL_PHY_PWRUP BIT(10) +#define PMT_CTL_READY BIT(7) +#define PMT_CTL_PHY_RST BIT(4) + +#define E2P_CMD 0x040 +#define E2P_CMD_EPC_BUSY BIT(31) +#define E2P_CMD_EPC_CMD_READ 0x00000000 +#define E2P_CMD_EPC_TIMEOUT BIT(10) +#define E2P_CMD_EPC_ADDR_MASK 0x000001FF + +#define E2P_DATA 0x044 + +#define RFE_CTL_BCAST_EN BIT(10) +#define RFE_CTL_DA_PERFECT BIT(1) + +#define FCT_RX_CTL_EN BIT(31) + +#define FCT_TX_CTL_EN BIT(31) + +#define MAC_CR 0x100 +#define MAC_CR_ADP BIT(13) +#define MAC_CR_AUTO_DUPLEX BIT(12) +#define MAC_CR_AUTO_SPEED BIT(11) + +#define MAC_RX 0x104 +#define MAC_RX_FCS_STRIP BIT(4) +#define MAC_RX_RXEN BIT(0) + +#define MAC_TX 0x108 +#define MAC_TX_TXEN BIT(0) + +#define FLOW 0x10C +#define FLOW_CR_TX_FCEN BIT(30) +#define FLOW_CR_RX_FCEN BIT(29) + +#define RX_ADDRH 0x118 +#define RX_ADDRL 0x11C + +#define MII_ACC 0x120 +#define MII_ACC_MII_READ 0x00000000 +#define MII_ACC_MII_WRITE 0x00000002 +#define MII_ACC_MII_BUSY BIT(0) + +#define MII_DATA 0x124 + +#define SS_USB_PKT_SIZE 1024 +#define HS_USB_PKT_SIZE 512 +#define FS_USB_PKT_SIZE 64 + +#define MAX_RX_FIFO_SIZE (12 * 1024) +#define MAX_TX_FIFO_SIZE (12 * 1024) +#define DEFAULT_BULK_IN_DELAY 0x0800 + +#define EEPROM_INDICATOR 0xA5 +#define EEPROM_MAC_OFFSET 0x01 + +/* Some extra defines */ +#define LAN7X_INTERNAL_PHY_ID 1 + +#define LAN7X_MAC_RX_MAX_SIZE(mtu) \ + ((mtu) << 16) /* Max frame size */ +#define LAN7X_MAC_RX_MAX_SIZE_DEFAULT \ + LAN7X_MAC_RX_MAX_SIZE(ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */) + +/* Timeouts */ +#define USB_CTRL_SET_TIMEOUT_MS 5000 +#define USB_CTRL_GET_TIMEOUT_MS 5000 +#define USB_BULK_SEND_TIMEOUT_MS 5000 +#define USB_BULK_RECV_TIMEOUT_MS 5000 +#define TIMEOUT_RESOLUTION_MS 50 +#define PHY_CONNECT_TIMEOUT_MS 5000 + +#define RX_URB_SIZE 2048 + +/* driver private */ +struct lan7x_private { + struct ueth_data ueth; + u32 chipid; /* Chip or device ID */ + struct mii_dev *mdiobus; + struct phy_device *phydev; +}; + +/* + * Lan7x infrastructure commands + */ + +int lan7x_write_reg(struct usb_device *udev, u32 index, u32 data); + +int lan7x_read_reg(struct usb_device *udev, u32 index, u32 *data); + +static inline int lan7x_wait_for_bit(struct usb_device *udev, + const char *prefix, const u32 reg, + const u32 mask, const bool set, + const unsigned int timeout_ms, + const bool breakable) +{ + u32 val; + unsigned long start = get_timer(0); + + while (1) { + lan7x_read_reg(udev, reg, &val); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > timeout_ms) + break; + + if (breakable && ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + + udelay(1); + WATCHDOG_RESET(); + } + + debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg, + mask, set); + + return -ETIMEDOUT; +} + +int lan7x_mdio_read(struct usb_device *udev, int phy_id, int idx); + +void lan7x_mdio_write(struct usb_device *udev, int phy_id, int idx, + int regval); + +static inline int lan7x_mdio_wait_for_bit(struct usb_device *udev, + const char *prefix, + int phy_id, const u32 reg, + const u32 mask, const bool set, + const unsigned int timeout_ms, + const bool breakable) +{ + u32 val; + unsigned long start = get_timer(0); + + while (1) { + val = lan7x_mdio_read(udev, phy_id, reg); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > timeout_ms) + break; + + if (breakable && ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + + udelay(1); + WATCHDOG_RESET(); + } + + debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg, + mask, set); + + return -ETIMEDOUT; +} + +int lan7x_phylib_register(struct udevice *udev); + +int lan7x_eth_phylib_connect(struct udevice *udev, struct ueth_data *dev); + +int lan7x_eth_phylib_config_start(struct udevice *udev); + +int lan7x_pmt_phy_reset(struct usb_device *udev, + struct ueth_data *dev); + +int lan7x_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev, + uint32_t *flow, uint32_t *fct_flow); + +int lan7x_read_eeprom_mac(unsigned char *enetaddr, struct usb_device *udev); + +int lan7x_basic_reset(struct usb_device *udev, + struct ueth_data *dev); + +#ifdef CONFIG_DM_ETH +void lan7x_eth_stop(struct udevice *dev); + +int lan7x_eth_send(struct udevice *dev, void *packet, int length); + +int lan7x_eth_recv(struct udevice *dev, int flags, uchar **packetp); + +int lan7x_free_pkt(struct udevice *dev, uchar *packet, int packet_len); + +int lan7x_eth_remove(struct udevice *dev); +#endif /* CONFIG_DM_ETH */ -- 2.7.4

2 1

[U-Boot] [PATCH] mii: Add mii_resolve_flowctrl_fdx()
by Yuiko.Oshino＠microchip.com 27 Jul '17

27 Jul '17

From: Yuiko Oshino <yuiko.oshino(a)microchip.com> Add an mii helper function to resolve flow control status per IEEE 802.3-2005 table 28B-3. This function was taken from the linux source tree. Signed-off-by: Yuiko Oshino <yuiko.oshino(a)microchip.com> --- include/linux/mii.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/include/linux/mii.h b/include/linux/mii.h index 66b83d8..19afb74 100644 --- a/include/linux/mii.h +++ b/include/linux/mii.h @@ -190,4 +190,27 @@ static inline unsigned int mii_duplex (unsigned int duplex_lock, return 0; } +/** + * mii_resolve_flowctrl_fdx + * @lcladv: value of MII ADVERTISE register + * @rmtadv: value of MII LPA register + * + * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3 + */ +static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv) +{ + u8 cap = 0; + + if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) { + cap = FLOW_CTRL_TX | FLOW_CTRL_RX; + } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) { + if (lcladv & ADVERTISE_PAUSE_CAP) + cap = FLOW_CTRL_RX; + else if (rmtadv & ADVERTISE_PAUSE_CAP) + cap = FLOW_CTRL_TX; + } + + return cap; +} + #endif /* __LINUX_MII_H__ */ -- 2.7.4

2 2

[U-Boot] [PATCH v2] Add support for Microchip LAN75xx and LAN78xx
by Yuiko.Oshino＠microchip.com 27 Jul '17

27 Jul '17

From: Yuiko Oshino <yuiko.oshino(a)microchip.com> Add support for Microchip LAN7500, LAN7800 and LAN7850, USB to 10/100/1000 Ethernet Controllers Signed-off-by: Yuiko Oshino <yuiko.oshino(a)microchip.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> Cc: Tom Rini <trini(a)konsulko.com> --- Changes for v2: - wait_for_bit functions copy the real one. - uses phylib - unnecessary variables were removed - all return values are checked - uses mii_resolve_flowctrl_fdx() from linux/mii.h ([PATCH] mii: Add mii_resolve_flowctrl_fdx() submitted on June 26, 2017) --- drivers/usb/Kconfig | 2 + drivers/usb/eth/Kconfig | 18 ++ drivers/usb/eth/Makefile | 2 + drivers/usb/eth/lan75xx.c | 320 +++++++++++++++++++++++++++++ drivers/usb/eth/lan78xx.c | 479 +++++++++++++++++++++++++++++++++++++++++++ drivers/usb/eth/lan7x.c | 506 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/eth/lan7x.h | 232 +++++++++++++++++++++ 7 files changed, 1559 insertions(+) create mode 100644 drivers/usb/eth/Kconfig create mode 100644 drivers/usb/eth/lan75xx.c create mode 100644 drivers/usb/eth/lan78xx.c create mode 100644 drivers/usb/eth/lan7x.c create mode 100644 drivers/usb/eth/lan7x.h diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index da3ec2f..62126aa 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -94,4 +94,6 @@ endif source "drivers/usb/gadget/Kconfig" +source "drivers/usb/eth/Kconfig" + endif diff --git a/drivers/usb/eth/Kconfig b/drivers/usb/eth/Kconfig new file mode 100644 index 0000000..a07243f --- /dev/null +++ b/drivers/usb/eth/Kconfig @@ -0,0 +1,18 @@ +comment "USB to Ethernet Controller Drivers" + +config USB_ETHER_LAN75XX + bool "Microchip LAN75XX support" + ---help--- + Say Y here if you would like to support Microchip LAN75XX Hi-Speed + USB 2.0 to 10/100/1000 Gigabit Ethernet controller. + Supports 10Base-T/ 100Base-TX/1000Base-T. + This driver supports the internal PHY. + +config USB_ETHER_LAN78XX + bool "Microchip LAN78XX support" + ---help--- + Say Y here if you would like to support Microchip LAN78XX USB 3.1 + Gen 1 to 10/100/1000 Gigabit Ethernet controller. + Supports 10Base-T/ 100Base-TX/1000Base-T. + This driver supports the internal PHY. + diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile index 4c44efc..4b935a3 100644 --- a/drivers/usb/eth/Makefile +++ b/drivers/usb/eth/Makefile @@ -9,4 +9,6 @@ obj-$(CONFIG_USB_ETHER_ASIX) += asix.o obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o +obj-$(CONFIG_USB_ETHER_LAN75XX) += lan7x.o lan75xx.o +obj-$(CONFIG_USB_ETHER_LAN78XX) += lan7x.o lan78xx.o obj-$(CONFIG_USB_ETHER_RTL8152) += r8152.o r8152_fw.o diff --git a/drivers/usb/eth/lan75xx.c b/drivers/usb/eth/lan75xx.c new file mode 100644 index 0000000..8ac7784 --- /dev/null +++ b/drivers/usb/eth/lan75xx.c @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <usb.h> +#include <linux/mii.h> +#include "usb_ether.h" +#include "lan7x.h" + +/* LAN75xx specific register/bit defines */ +#define LAN75XX_HW_CFG_BIR BIT(7) + +#define LAN75XX_BURST_CAP 0x034 + +#define LAN75XX_BULK_IN_DLY 0x03C + +#define LAN75XX_RFE_CTL 0x060 + +#define LAN75XX_FCT_RX_CTL 0x090 + +#define LAN75XX_FCT_TX_CTL 0x094 + +#define LAN75XX_FCT_RX_FIFO_END 0x098 + +#define LAN75XX_FCT_TX_FIFO_END 0x09C + +#define LAN75XX_FCT_FLOW 0x0A0 + +/* MAC ADDRESS PERFECT FILTER For LAN75xx */ +#define LAN75XX_ADDR_FILTX 0x300 +#define LAN75XX_ADDR_FILTX_FB_VALID BIT(31) + +/* + * Lan75xx infrastructure commands + */ +static int lan75xx_phy_gig_workaround(struct usb_device *udev, + struct ueth_data *dev) +{ + int ret = 0; + + /* Only internal phy */ + /* Set the phy in Gig loopback */ + lan7x_mdio_write(udev, dev->phy_id, MII_BMCR, + (BMCR_LOOPBACK | BMCR_SPEED1000)); + + /* Wait for the link up */ + ret = lan7x_mdio_wait_for_bit(udev, "BMSR_LSTATUS", + dev->phy_id, MII_BMSR, BMSR_LSTATUS, + true, PHY_CONNECT_TIMEOUT_MS, 1); + if (ret) + return ret; + + /* phy reset */ + return lan7x_pmt_phy_reset(udev, dev); +} + +static int lan75xx_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev) +{ + uint32_t flow = 0, fct_flow = 0; + int ret; + + ret = lan7x_update_flowcontrol(udev, dev, &flow, &fct_flow); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_FCT_FLOW, fct_flow); + if (ret) + return ret; + return lan7x_write_reg(udev, FLOW, flow); +} + +static int lan75xx_read_mac(unsigned char *enetaddr, + struct usb_device *udev) +{ + /* + * Refer to the doc/README.enetaddr and doc/README.usb for + * the U-Boot MAC address policy + */ + return lan7x_read_eeprom_mac(enetaddr, udev); +} + +static int lan75xx_set_receive_filter(struct usb_device *udev) +{ + /* No multicast in u-boot */ + return lan7x_write_reg(udev, LAN75XX_RFE_CTL, + RFE_CTL_BCAST_EN | RFE_CTL_DA_PERFECT); +} + +/* starts the TX path */ +static void lan75xx_start_tx_path(struct usb_device *udev) +{ + /* Enable Tx at MAC */ + lan7x_write_reg(udev, MAC_TX, MAC_TX_TXEN); + + /* Enable Tx at SCSRs */ + lan7x_write_reg(udev, LAN75XX_FCT_TX_CTL, FCT_TX_CTL_EN); +} + +/* Starts the Receive path */ +static void lan75xx_start_rx_path(struct usb_device *udev) +{ + /* Enable Rx at MAC */ + lan7x_write_reg(udev, MAC_RX, + LAN7X_MAC_RX_MAX_SIZE_DEFAULT | + MAC_RX_FCS_STRIP | MAC_RX_RXEN); + + /* Enable Rx at SCSRs */ + lan7x_write_reg(udev, LAN75XX_FCT_RX_CTL, FCT_RX_CTL_EN); +} + +static int lan75xx_basic_reset(struct usb_device *udev, + struct ueth_data *dev, + struct lan7x_private *priv) +{ + int ret; + u32 val; + + ret = lan7x_basic_reset(udev, dev); + if (ret) + return ret; + + /* Keep the chip ID */ + ret = lan7x_read_reg(udev, ID_REV, &val); + if (ret) + return ret; + debug("LAN75xx ID_REV = 0x%08x\n", val); + + priv->chipid = (val & ID_REV_CHIP_ID_MASK) >> 16; + + /* Respond to the IN token with a NAK */ + ret = lan7x_read_reg(udev, HW_CFG, &val); + if (ret) + return ret; + val |= LAN75XX_HW_CFG_BIR; + return lan7x_write_reg(udev, HW_CFG, val); +} + +#ifdef CONFIG_DM_ETH +int lan75xx_write_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + unsigned char *enetaddr = pdata->enetaddr; + u32 addr_lo = get_unaligned_le32(&enetaddr[0]); + u32 addr_hi = (u32)get_unaligned_le16(&enetaddr[4]); + int ret; + + /* set hardware address */ + ret = lan7x_write_reg(udev, RX_ADDRL, addr_lo); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, RX_ADDRH, addr_hi); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_ADDR_FILTX + 4, addr_lo); + if (ret) + return ret; + + addr_hi |= LAN75XX_ADDR_FILTX_FB_VALID; + ret = lan7x_write_reg(udev, LAN75XX_ADDR_FILTX, addr_hi); + if (ret) + return ret; + + debug("MAC addr %pM written\n", enetaddr); + + return 0; +} + +static int lan75xx_eth_start(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + int ret; + u32 write_buf; + + /* Reset and read Mac addr were done in probe() */ + ret = lan75xx_write_hwaddr(dev); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, INT_STS, 0xFFFFFFFF); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_BURST_CAP, 0); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); + if (ret) + return ret; + + /* set FIFO sizes */ + write_buf = (MAX_RX_FIFO_SIZE - 512) / 512; + ret = lan7x_write_reg(udev, LAN75XX_FCT_RX_FIFO_END, write_buf); + if (ret) + return ret; + + write_buf = (MAX_TX_FIFO_SIZE - 512) / 512; + ret = lan7x_write_reg(udev, LAN75XX_FCT_TX_FIFO_END, write_buf); + if (ret) + return ret; + + /* Init Tx */ + ret = lan7x_write_reg(udev, FLOW, 0); + if (ret) + return ret; + + /* Init Rx. Set Vlan, keep defult for VLAN on 75xx */ + ret = lan75xx_set_receive_filter(udev); + if (ret) + return ret; + + /* phy workaround for gig link */ + ret = lan75xx_phy_gig_workaround(udev, ueth); + if (ret) + return ret; + + /* Init PHY, autonego, and link */ + ret = lan7x_eth_phylib_connect(dev, &priv->ueth); + if (ret) + return ret; + ret = lan7x_eth_phylib_config_start(dev); + if (ret) + return ret; + + /* + * MAC_CR has to be set after PHY init. + * MAC will auto detect the PHY speed. + */ + ret = lan7x_read_reg(udev, MAC_CR, &write_buf); + if (ret) + return ret; + write_buf |= MAC_CR_AUTO_DUPLEX | MAC_CR_AUTO_SPEED | MAC_CR_ADP; + ret = lan7x_write_reg(udev, MAC_CR, write_buf); + if (ret) + return ret; + + lan75xx_start_tx_path(udev); + lan75xx_start_rx_path(udev); + + return lan75xx_update_flowcontrol(udev, ueth); +} + +int lan75xx_read_rom_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + ret = lan75xx_read_mac(pdata->enetaddr, udev); + if (ret) + memset(pdata->enetaddr, 0, 6); + + return 0; +} + +static int lan75xx_eth_probe(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + struct eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + /* Do a reset in order to get the MAC address from HW */ + if (lan75xx_basic_reset(udev, ueth, priv)) + return 0; + + /* Get the MAC address */ + /* + * We must set the eth->enetaddr from HW because the upper layer + * will force to use the environmental var (usbethaddr) or random if + * there is no valid MAC address in eth->enetaddr. + */ + lan75xx_read_mac(pdata->enetaddr, udev); + /* Do not return 0 for not finding MAC addr in HW */ + + ret = usb_ether_register(dev, ueth, RX_URB_SIZE); + if (ret) + return ret; + + /* Register phylib */ + return lan7x_phylib_register(dev); +} + +static const struct eth_ops lan75xx_eth_ops = { + .start = lan75xx_eth_start, + .send = lan7x_eth_send, + .recv = lan7x_eth_recv, + .free_pkt = lan7x_free_pkt, + .stop = lan7x_eth_stop, + .write_hwaddr = lan75xx_write_hwaddr, + .read_rom_hwaddr = lan75xx_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(lan75xx_eth) = { + .name = "lan75xx_eth", + .id = UCLASS_ETH, + .probe = lan75xx_eth_probe, + .remove = lan7x_eth_remove, + .ops = &lan75xx_eth_ops, + .priv_auto_alloc_size = sizeof(struct lan7x_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +static const struct usb_device_id lan75xx_eth_id_table[] = { + { USB_DEVICE(0x0424, 0x7500) }, /* LAN7500 USB Ethernet */ + { } /* Terminating entry */ +}; + +U_BOOT_USB_DEVICE(lan75xx_eth, lan75xx_eth_id_table); +#endif diff --git a/drivers/usb/eth/lan78xx.c b/drivers/usb/eth/lan78xx.c new file mode 100644 index 0000000..5160db7 --- /dev/null +++ b/drivers/usb/eth/lan78xx.c @@ -0,0 +1,479 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <usb.h> +#include "usb_ether.h" +#include "lan7x.h" + +/* LAN78xx specific register/bit defines */ +#define LAN78XX_HW_CFG_LED1_EN BIT(21) /* Muxed with EEDO */ +#define LAN78XX_HW_CFG_LED0_EN BIT(20) /* Muxed with EECLK */ + +#define LAN78XX_USB_CFG0 0x080 +#define LAN78XX_USB_CFG0_BIR BIT(6) + +#define LAN78XX_BURST_CAP 0x090 + +#define LAN78XX_BULK_IN_DLY 0x094 + +#define LAN78XX_RFE_CTL 0x0B0 + +#define LAN78XX_FCT_RX_CTL 0x0C0 + +#define LAN78XX_FCT_TX_CTL 0x0C4 + +#define LAN78XX_FCT_RX_FIFO_END 0x0C8 + +#define LAN78XX_FCT_TX_FIFO_END 0x0CC + +#define LAN78XX_FCT_FLOW 0x0D0 + +#define LAN78XX_MAF_BASE 0x400 +#define LAN78XX_MAF_HIX 0x00 +#define LAN78XX_MAF_LOX 0x04 +#define LAN78XX_MAF_HI_BEGIN (LAN78XX_MAF_BASE + LAN78XX_MAF_HIX) +#define LAN78XX_MAF_LO_BEGIN (LAN78XX_MAF_BASE + LAN78XX_MAF_LOX) +#define LAN78XX_MAF_HI(index) (LAN78XX_MAF_BASE + (8 * (index)) + \ + LAN78XX_MAF_HIX) +#define LAN78XX_MAF_LO(index) (LAN78XX_MAF_BASE + (8 * (index)) + \ + LAN78XX_MAF_LOX) +#define LAN78XX_MAF_HI_VALID BIT(31) + +/* OTP registers */ +#define LAN78XX_OTP_BASE_ADDR 0x00001000 + +#define LAN78XX_OTP_PWR_DN (LAN78XX_OTP_BASE_ADDR + 4 * 0x00) +#define LAN78XX_OTP_PWR_DN_PWRDN_N BIT(0) + +#define LAN78XX_OTP_ADDR1 (LAN78XX_OTP_BASE_ADDR + 4 * 0x01) +#define LAN78XX_OTP_ADDR1_15_11 0x1F + +#define LAN78XX_OTP_ADDR2 (LAN78XX_OTP_BASE_ADDR + 4 * 0x02) +#define LAN78XX_OTP_ADDR2_10_3 0xFF + +#define LAN78XX_OTP_RD_DATA (LAN78XX_OTP_BASE_ADDR + 4 * 0x06) + +#define LAN78XX_OTP_FUNC_CMD (LAN78XX_OTP_BASE_ADDR + 4 * 0x08) +#define LAN78XX_OTP_FUNC_CMD_READ BIT(0) + +#define LAN78XX_OTP_CMD_GO (LAN78XX_OTP_BASE_ADDR + 4 * 0x0A) +#define LAN78XX_OTP_CMD_GO_GO BIT(0) + +#define LAN78XX_OTP_STATUS (LAN78XX_OTP_BASE_ADDR + 4 * 0x0C) +#define LAN78XX_OTP_STATUS_BUSY BIT(0) + +#define LAN78XX_OTP_INDICATOR_1 0xF3 +#define LAN78XX_OTP_INDICATOR_2 0xF7 + +/* + * Lan78xx infrastructure commands + */ +static int lan78xx_read_raw_otp(struct usb_device *udev, u32 offset, + u32 length, u8 *data) +{ + int i; + int ret; + u32 buf; + + ret = lan7x_read_reg(udev, LAN78XX_OTP_PWR_DN, &buf); + if (ret) + return ret; + + if (buf & LAN78XX_OTP_PWR_DN_PWRDN_N) { + /* clear it and wait to be cleared */ + ret = lan7x_write_reg(udev, LAN78XX_OTP_PWR_DN, 0); + if (ret) + return ret; + + ret = lan7x_wait_for_bit(udev, "LAN78XX_OTP_PWR_DN_PWRDN_N", + LAN78XX_OTP_PWR_DN, + LAN78XX_OTP_PWR_DN_PWRDN_N, + false, 1000, 0); + if (ret) + return ret; + } + + for (i = 0; i < length; i++) { + ret = lan7x_write_reg(udev, LAN78XX_OTP_ADDR1, + ((offset + i) >> 8) & + LAN78XX_OTP_ADDR1_15_11); + if (ret) + return ret; + ret = lan7x_write_reg(udev, LAN78XX_OTP_ADDR2, + ((offset + i) & LAN78XX_OTP_ADDR2_10_3)); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_OTP_FUNC_CMD, + LAN78XX_OTP_FUNC_CMD_READ); + if (ret) + return ret; + ret = lan7x_write_reg(udev, LAN78XX_OTP_CMD_GO, + LAN78XX_OTP_CMD_GO_GO); + + if (ret) + return ret; + + ret = lan7x_wait_for_bit(udev, "LAN78XX_OTP_STATUS_BUSY", + LAN78XX_OTP_STATUS, + LAN78XX_OTP_STATUS_BUSY, + false, 1000, 0); + if (ret) + return ret; + + ret = lan7x_read_reg(udev, LAN78XX_OTP_RD_DATA, &buf); + if (ret) + return ret; + + data[i] = (u8)(buf & 0xFF); + } + + return 0; +} + +static int lan78xx_read_otp(struct usb_device *udev, u32 offset, + u32 length, u8 *data) +{ + u8 sig; + int ret; + + ret = lan78xx_read_raw_otp(udev, 0, 1, &sig); + + if (!ret) { + if (sig == LAN78XX_OTP_INDICATOR_1) + offset = offset; + else if (sig == LAN78XX_OTP_INDICATOR_2) + offset += 0x100; + else + return -EINVAL; + ret = lan78xx_read_raw_otp(udev, offset, length, data); + if (ret) + return ret; + } + debug("LAN78x: MAC address from OTP = %pM\n", data); + + return ret; +} + +static int lan78xx_read_otp_mac(unsigned char *enetaddr, + struct usb_device *udev) +{ + int ret; + + memset(enetaddr, 0, 6); + + ret = lan78xx_read_otp(udev, + EEPROM_MAC_OFFSET, + ETH_ALEN, + enetaddr); + if (!ret && is_valid_ethaddr(enetaddr)) { + /* eeprom values are valid so use them */ + debug("MAC address read from OTP %pM\n", enetaddr); + return 0; + } + debug("MAC address read from OTP invalid %pM\n", enetaddr); + + memset(enetaddr, 0, 6); + return -EINVAL; +} + +static int lan78xx_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev) +{ + uint32_t flow = 0, fct_flow = 0; + int ret; + + ret = lan7x_update_flowcontrol(udev, dev, &flow, &fct_flow); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_FCT_FLOW, fct_flow); + if (ret) + return ret; + return lan7x_write_reg(udev, FLOW, flow); +} + +static int lan78xx_read_mac(unsigned char *enetaddr, + struct usb_device *udev, + struct lan7x_private *priv) +{ + u32 val; + int ret; + int saved = 0, done = 0; + + /* + * Depends on chip, some EEPROM pins are muxed with LED function. + * disable & restore LED function to access EEPROM. + */ + if ((priv->chipid == ID_REV_CHIP_ID_7800) || + (priv->chipid == ID_REV_CHIP_ID_7850)) { + ret = lan7x_read_reg(udev, HW_CFG, &val); + if (ret) + return ret; + saved = val; + val &= ~(LAN78XX_HW_CFG_LED1_EN | LAN78XX_HW_CFG_LED0_EN); + ret = lan7x_write_reg(udev, HW_CFG, val); + if (ret) + goto restore; + } + + /* + * Refer to the doc/README.enetaddr and doc/README.usb for + * the U-Boot MAC address policy + */ + /* try reading mac address from EEPROM, then from OTP */ + ret = lan7x_read_eeprom_mac(enetaddr, udev); + if (!ret) + done = 1; + +restore: + if ((priv->chipid == ID_REV_CHIP_ID_7800) || + (priv->chipid == ID_REV_CHIP_ID_7850)) { + ret = lan7x_write_reg(udev, HW_CFG, saved); + if (ret) + return ret; + } + /* if the EEPROM mac address is good, then exit */ + if (done) + return 0; + + /* try reading mac address from OTP if the device is LAN78xx */ + return lan78xx_read_otp_mac(enetaddr, udev); +} + +static int lan78xx_set_receive_filter(struct usb_device *udev) +{ + /* No multicast in u-boot for now */ + return lan7x_write_reg(udev, LAN78XX_RFE_CTL, + RFE_CTL_BCAST_EN | RFE_CTL_DA_PERFECT); +} + +/* starts the TX path */ +static void lan78xx_start_tx_path(struct usb_device *udev) +{ + /* Enable Tx at MAC */ + lan7x_write_reg(udev, MAC_TX, MAC_TX_TXEN); + + /* Enable Tx at SCSRs */ + lan7x_write_reg(udev, LAN78XX_FCT_TX_CTL, FCT_TX_CTL_EN); +} + +/* Starts the Receive path */ +static void lan78xx_start_rx_path(struct usb_device *udev) +{ + /* Enable Rx at MAC */ + lan7x_write_reg(udev, MAC_RX, + LAN7X_MAC_RX_MAX_SIZE_DEFAULT | + MAC_RX_FCS_STRIP | MAC_RX_RXEN); + + /* Enable Rx at SCSRs */ + lan7x_write_reg(udev, LAN78XX_FCT_RX_CTL, FCT_RX_CTL_EN); +} + +static int lan78xx_basic_reset(struct usb_device *udev, + struct ueth_data *dev, + struct lan7x_private *priv) +{ + int ret; + u32 val; + + ret = lan7x_basic_reset(udev, dev); + if (ret) + return ret; + + /* Keep the chip ID */ + ret = lan7x_read_reg(udev, ID_REV, &val); + if (ret) + return ret; + debug("LAN78xx ID_REV = 0x%08x\n", val); + + priv->chipid = (val & ID_REV_CHIP_ID_MASK) >> 16; + + /* Respond to the IN token with a NAK */ + ret = lan7x_read_reg(udev, LAN78XX_USB_CFG0, &val); + if (ret) + return ret; + val |= LAN78XX_USB_CFG0_BIR; + return lan7x_write_reg(udev, LAN78XX_USB_CFG0, val); +} + +#ifdef CONFIG_DM_ETH +int lan78xx_write_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + unsigned char *enetaddr = pdata->enetaddr; + u32 addr_lo = get_unaligned_le32(&enetaddr[0]); + u32 addr_hi = (u32)get_unaligned_le16(&enetaddr[4]); + int ret; + + /* set hardware address */ + ret = lan7x_write_reg(udev, RX_ADDRL, addr_lo); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, RX_ADDRH, addr_hi); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_MAF_LO(0), addr_lo); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_MAF_HI(0), + addr_hi | LAN78XX_MAF_HI_VALID); + if (ret) + return ret; + + debug("MAC addr %pM written\n", enetaddr); + + return 0; +} + +static int lan78xx_eth_start(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + + int ret; + u32 write_buf; + + /* Reset and read Mac addr were done in probe() */ + ret = lan78xx_write_hwaddr(dev); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_BURST_CAP, 0); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, INT_STS, 0xFFFFFFFF); + if (ret) + return ret; + + /* set FIFO sizes */ + ret = lan7x_write_reg(udev, LAN78XX_FCT_RX_FIFO_END, + (MAX_RX_FIFO_SIZE - 512) / 512); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_FCT_TX_FIFO_END, + (MAX_TX_FIFO_SIZE - 512) / 512); + if (ret) + return ret; + + /* Init Tx */ + ret = lan7x_write_reg(udev, FLOW, 0); + if (ret) + return ret; + + /* Init Rx. Set Vlan, keep defult for VLAN on 78xx */ + ret = lan78xx_set_receive_filter(udev); + if (ret) + return ret; + + /* Init PHY, autonego, and link */ + ret = lan7x_eth_phylib_connect(dev, &priv->ueth); + if (ret) + return ret; + ret = lan7x_eth_phylib_config_start(dev); + if (ret) + return ret; + + /* + * MAC_CR has to be set after PHY init. + * MAC will auto detect the PHY speed. + */ + ret = lan7x_read_reg(udev, MAC_CR, &write_buf); + if (ret) + return ret; + write_buf |= MAC_CR_AUTO_DUPLEX | MAC_CR_AUTO_SPEED | MAC_CR_ADP; + ret = lan7x_write_reg(udev, MAC_CR, write_buf); + if (ret) + return ret; + + lan78xx_start_tx_path(udev); + lan78xx_start_rx_path(udev); + + return lan78xx_update_flowcontrol(udev, &priv->ueth); +} + +int lan78xx_read_rom_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct lan7x_private *priv = dev_get_priv(dev); + int ret; + + ret = lan78xx_read_mac(pdata->enetaddr, udev, priv); + if (ret) + memset(pdata->enetaddr, 0, 6); + + return 0; +} + +static int lan78xx_eth_probe(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + struct eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + /* Do a reset in order to get the MAC address from HW */ + if (lan78xx_basic_reset(udev, ueth, priv)) + return 0; + + /* Get the MAC address */ + /* + * We must set the eth->enetaddr from HW because the upper layer + * will force to use the environmental var (usbethaddr) or random if + * there is no valid MAC address in eth->enetaddr. + */ + lan78xx_read_mac(pdata->enetaddr, udev, priv); + /* Do not return 0 for not finding MAC addr in HW */ + + ret = usb_ether_register(dev, ueth, RX_URB_SIZE); + if (ret) + return ret; + + /* Register phylib */ + return lan7x_phylib_register(dev); +} + +static const struct eth_ops lan78xx_eth_ops = { + .start = lan78xx_eth_start, + .send = lan7x_eth_send, + .recv = lan7x_eth_recv, + .free_pkt = lan7x_free_pkt, + .stop = lan7x_eth_stop, + .write_hwaddr = lan78xx_write_hwaddr, + .read_rom_hwaddr = lan78xx_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(lan78xx_eth) = { + .name = "lan78xx_eth", + .id = UCLASS_ETH, + .probe = lan78xx_eth_probe, + .remove = lan7x_eth_remove, + .ops = &lan78xx_eth_ops, + .priv_auto_alloc_size = sizeof(struct lan7x_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +static const struct usb_device_id lan78xx_eth_id_table[] = { + { USB_DEVICE(0x0424, 0x7800) }, /* LAN7800 USB Ethernet */ + { USB_DEVICE(0x0424, 0x7850) }, /* LAN7850 USB Ethernet */ + { } /* Terminating entry */ +}; + +U_BOOT_USB_DEVICE(lan78xx_eth, lan78xx_eth_id_table); +#endif diff --git a/drivers/usb/eth/lan7x.c b/drivers/usb/eth/lan7x.c new file mode 100644 index 0000000..a2ebbeb --- /dev/null +++ b/drivers/usb/eth/lan7x.c @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <malloc.h> +#include <miiphy.h> +#include <memalign.h> +#include <usb.h> +#include <linux/ethtool.h> +#include <linux/mii.h> +#include "usb_ether.h" +#include "lan7x.h" + +/* + * Lan7x infrastructure commands + */ +int lan7x_write_reg(struct usb_device *udev, u32 index, u32 data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); + + cpu_to_le32s(&data); + tmpbuf[0] = data; + + len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + USB_VENDOR_REQUEST_WRITE_REGISTER, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0, index, tmpbuf, sizeof(data), + USB_CTRL_SET_TIMEOUT_MS); + if (len != sizeof(data)) { + debug("%s failed: index=%d, data=%d, len=%d", + __func__, index, data, len); + return -EIO; + } + return 0; +} + +int lan7x_read_reg(struct usb_device *udev, u32 index, u32 *data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); + + len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + USB_VENDOR_REQUEST_READ_REGISTER, + USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0, index, tmpbuf, sizeof(*data), + USB_CTRL_GET_TIMEOUT_MS); + *data = tmpbuf[0]; + if (len != sizeof(*data)) { + debug("%s failed: index=%d, len=%d", __func__, index, len); + return -EIO; + } + + le32_to_cpus(data); + return 0; +} + +static int lan7x_phy_wait_not_busy(struct usb_device *udev) +{ + return lan7x_wait_for_bit(udev, __func__, + MII_ACC, MII_ACC_MII_BUSY, + false, 100, 0); +} + +int lan7x_mdio_read(struct usb_device *udev, int phy_id, int idx) +{ + u32 val, addr; + + /* confirm MII not busy */ + if (lan7x_phy_wait_not_busy(udev)) { + debug("MII is busy in %s\n", __func__); + return -ETIMEDOUT; + } + + /* set the address, index & direction (read from PHY) */ + addr = (phy_id << 11) | (idx << 6) | + MII_ACC_MII_READ | MII_ACC_MII_BUSY; + lan7x_write_reg(udev, MII_ACC, addr); + + if (lan7x_phy_wait_not_busy(udev)) { + debug("Timed out reading MII reg %02X\n", idx); + return -ETIMEDOUT; + } + + lan7x_read_reg(udev, MII_DATA, &val); + + return val & 0xFFFF; +} + +void lan7x_mdio_write(struct usb_device *udev, int phy_id, int idx, int regval) +{ + u32 addr; + + /* confirm MII not busy */ + if (lan7x_phy_wait_not_busy(udev)) { + debug("MII is busy in %s\n", __func__); + return; + } + + lan7x_write_reg(udev, MII_DATA, regval); + + /* set the address, index & direction (write to PHY) */ + addr = (phy_id << 11) | (idx << 6) | + MII_ACC_MII_WRITE | MII_ACC_MII_BUSY; + lan7x_write_reg(udev, MII_ACC, addr); + + if (lan7x_phy_wait_not_busy(udev)) + debug("Timed out writing MII reg %02X\n", idx); +} + +/* + * Lan7x phylib wrappers + */ +static int lan7x_phylib_mdio_read(struct mii_dev *bus, + int addr, int devad, int reg) +{ + struct usb_device *udev = dev_get_parent_priv(bus->priv); + + return lan7x_mdio_read(udev, addr, reg); +} + +static int lan7x_phylib_mdio_write(struct mii_dev *bus, + int addr, int devad, int reg, u16 val) +{ + struct usb_device *udev = dev_get_parent_priv(bus->priv); + + lan7x_mdio_write(udev, addr, reg, (int)val); + + return 0; +} + +/* + * Lan7x eeprom functions + */ +static int lan7x_eeprom_confirm_not_busy(struct usb_device *udev) +{ + return lan7x_wait_for_bit(udev, __func__, + E2P_CMD, E2P_CMD_EPC_BUSY, + false, 100, 0); +} + +static int lan7x_wait_eeprom(struct usb_device *udev) +{ + return lan7x_wait_for_bit(udev, __func__, + E2P_CMD, + (E2P_CMD_EPC_BUSY | E2P_CMD_EPC_TIMEOUT), + false, 100, 0); +} + +static int lan7x_read_eeprom(struct usb_device *udev, + u32 offset, u32 length, u8 *data) +{ + u32 val; + int i, ret; + + ret = lan7x_eeprom_confirm_not_busy(udev); + if (ret) + return ret; + + for (i = 0; i < length; i++) { + val = E2P_CMD_EPC_BUSY | E2P_CMD_EPC_CMD_READ | + (offset & E2P_CMD_EPC_ADDR_MASK); + lan7x_write_reg(udev, E2P_CMD, val); + + ret = lan7x_wait_eeprom(udev); + if (ret) + return ret; + + lan7x_read_reg(udev, E2P_DATA, &val); + data[i] = val & 0xFF; + offset++; + } + return ret; +} + +/* + * Lan7x phylib functions + */ +int lan7x_phylib_register(struct udevice *udev) +{ + struct lan7x_private *priv = dev_get_priv(udev); + int ret; + + priv->mdiobus = mdio_alloc(); + if (!priv->mdiobus) { + printf("mdio_alloc failed\n"); + return -ENOMEM; + } + priv->mdiobus->read = lan7x_phylib_mdio_read; + priv->mdiobus->write = lan7x_phylib_mdio_write; + strcpy(priv->mdiobus->name, "lan78x_mdiobus"); + priv->mdiobus->priv = (void *)udev; + + ret = mdio_register(priv->mdiobus); + if (ret) { + printf("mdio_register failed\n"); + free(priv->mdiobus); + return -ENOMEM; + } + + return 0; +} + +int lan7x_eth_phylib_connect(struct udevice *udev, struct ueth_data *dev) +{ + struct lan7x_private *priv = dev_get_priv(udev); + + priv->phydev = phy_connect(priv->mdiobus, dev->phy_id, + udev, PHY_INTERFACE_MODE_MII); + + if (!priv->phydev) { + printf("phy_connect failed\n"); + return -ENODEV; + } + return 0; +} + +int lan7x_eth_phylib_config_start(struct udevice *udev) +{ + struct lan7x_private *priv = dev_get_priv(udev); + int ret; + + /* configure supported modes */ + priv->phydev->supported = PHY_BASIC_FEATURES | + SUPPORTED_1000baseT_Full | + SUPPORTED_Pause | + SUPPORTED_Asym_Pause; + + priv->phydev->advertising = ADVERTISED_10baseT_Half | + ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | + ADVERTISED_100baseT_Full | + ADVERTISED_1000baseT_Full | + ADVERTISED_Pause | + ADVERTISED_Asym_Pause | + ADVERTISED_Autoneg; + + priv->phydev->autoneg = AUTONEG_ENABLE; + + ret = genphy_config_aneg(priv->phydev); + if (ret) { + printf("genphy_config_aneg failed\n"); + return ret; + } + ret = phy_startup(priv->phydev); + if (ret) { + printf("phy_startup failed\n"); + return ret; + } + + debug("** %s() speed %i duplex %i adv %X supp %X\n", __func__, + priv->phydev->speed, priv->phydev->duplex, + priv->phydev->advertising, priv->phydev->supported); + + return 0; +} + +int lan7x_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev, + uint32_t *flow, uint32_t *fct_flow) +{ + uint32_t lcladv, rmtadv; + u8 cap = 0; + struct lan7x_private *priv = dev_get_priv(udev->dev); + + debug("** %s()\n", __func__); + debug("** %s() priv->phydev->speed %i duplex %i\n", __func__, + priv->phydev->speed, priv->phydev->duplex); + + if (priv->phydev->duplex == DUPLEX_FULL) { + lcladv = lan7x_mdio_read(udev, dev->phy_id, MII_ADVERTISE); + rmtadv = lan7x_mdio_read(udev, dev->phy_id, MII_LPA); + cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); + + debug("TX Flow "); + if (cap & FLOW_CTRL_TX) { + *flow = (FLOW_CR_TX_FCEN | 0xFFFF); + /* set fct_flow thresholds to 20% and 80% */ + *fct_flow = ((MAX_RX_FIFO_SIZE * 2) / (10 * 512)) + & 0x7FUL; + *fct_flow <<= 8UL; + *fct_flow |= ((MAX_RX_FIFO_SIZE * 8) / (10 * 512)) + & 0x7FUL; + debug("EN "); + } else { + debug("DIS "); + } + debug("RX Flow "); + if (cap & FLOW_CTRL_RX) { + *flow |= FLOW_CR_RX_FCEN; + debug("EN"); + } else { + debug("DIS"); + } + } + debug("\n"); + return 0; +} + +int lan7x_read_eeprom_mac(unsigned char *enetaddr, struct usb_device *udev) +{ + int ret; + + memset(enetaddr, 0, 6); + + ret = lan7x_read_eeprom(udev, 0, 1, enetaddr); + + if ((ret == 0) && (enetaddr[0] == EEPROM_INDICATOR)) { + ret = lan7x_read_eeprom(udev, + EEPROM_MAC_OFFSET, ETH_ALEN, + enetaddr); + if ((ret == 0) && is_valid_ethaddr(enetaddr)) { + /* eeprom values are valid so use them */ + debug("MAC address read from EEPROM %pM\n", + enetaddr); + return 0; + } + } + debug("MAC address read from EEPROM invalid %pM\n", enetaddr); + + memset(enetaddr, 0, 6); + return -EINVAL; +} + +int lan7x_pmt_phy_reset(struct usb_device *udev, + struct ueth_data *dev) +{ + int ret; + u32 data; + + ret = lan7x_read_reg(udev, PMT_CTL, &data); + if (ret) + return ret; + ret = lan7x_write_reg(udev, PMT_CTL, data | PMT_CTL_PHY_RST); + if (ret) + return ret; + + /* for LAN7x, we need to check PMT_CTL_READY asserted */ + ret = lan7x_wait_for_bit(udev, "PMT_CTL_PHY_RST", + PMT_CTL, PMT_CTL_PHY_RST, + false, 1000, 0); /* could take over 125mS */ + if (ret) + return ret; + + return lan7x_wait_for_bit(udev, "PMT_CTL_READY", + PMT_CTL, PMT_CTL_READY, + true, 1000, 0); +} + +int lan7x_basic_reset(struct usb_device *udev, + struct ueth_data *dev) +{ + int ret; + + dev->phy_id = LAN7X_INTERNAL_PHY_ID; /* fixed phy id */ + + ret = lan7x_write_reg(udev, HW_CFG, HW_CFG_LRST); + if (ret) + return ret; + + ret = lan7x_wait_for_bit(udev, "HW_CFG_LRST", + HW_CFG, HW_CFG_LRST, + false, 1000, 0); + if (ret) + return ret; + + return lan7x_pmt_phy_reset(udev, dev); +} + +#ifdef CONFIG_DM_ETH +void lan7x_eth_stop(struct udevice *dev) +{ + debug("** %s()\n", __func__); +} + +int lan7x_eth_send(struct udevice *dev, void *packet, int length) +{ + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + int err; + int actual_len; + u32 tx_cmd_a; + u32 tx_cmd_b; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, + PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); + + debug("** %s(), len %d, buf %#x\n", __func__, length, + (unsigned int)(ulong) msg); + if (length > PKTSIZE) + return -ENOSPC; + + /* LAN7x disable all TX offload features for u-boot */ + tx_cmd_a = (u32) (length & TX_CMD_A_LEN_MASK) | TX_CMD_A_FCS; + tx_cmd_b = 0; + cpu_to_le32s(&tx_cmd_a); + cpu_to_le32s(&tx_cmd_b); + + /* prepend cmd_a and cmd_b */ + memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); + memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); + memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, + length); + err = usb_bulk_msg(ueth->pusb_dev, + usb_sndbulkpipe(ueth->pusb_dev, ueth->ep_out), + (void *)msg, + length + sizeof(tx_cmd_a) + + sizeof(tx_cmd_b), + &actual_len, USB_BULK_SEND_TIMEOUT_MS); + debug("Tx: len = %u, actual = %u, err = %d\n", + (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)), + (unsigned int)actual_len, err); + + return err; +} + +int lan7x_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE); + unsigned char *buf_ptr; + int err; + int actual_len = 0; + u32 packet_len = 0; + u32 rx_cmd_a = 0; + + err = usb_bulk_msg(ueth->pusb_dev, + usb_rcvbulkpipe(ueth->pusb_dev, ueth->ep_in), + (void *)recv_buf, RX_URB_SIZE, &actual_len, + USB_BULK_RECV_TIMEOUT_MS); + + debug("Rx: RX_URB_SIZE = %u, actual = %u, err = %d\n", RX_URB_SIZE, + actual_len, err); + if (err != 0) { + debug("Rx: failed to receive\n"); + return err; + } + if (actual_len > RX_URB_SIZE) { + debug("Rx: received too many bytes %d\n", actual_len); + return -ENOSPC; + } + + buf_ptr = recv_buf; + + /* + * No multiple Ethernet Frames per USB Packet (MEF) used + * for the U-boot for now. + */ + if (actual_len > 0) { + if (actual_len < sizeof(rx_cmd_a)) { + debug("Rx: incomplete packet length\n"); + return -EIO; + } + memcpy(&rx_cmd_a, buf_ptr, sizeof(rx_cmd_a)); + le32_to_cpus(&rx_cmd_a); + if (rx_cmd_a & RX_CMD_A_RXE) { + debug("Rx: Error header=%#x", rx_cmd_a); + return -EIO; + } + packet_len = (u16) (rx_cmd_a & RX_CMD_A_LEN_MASK); + + if (packet_len > actual_len - sizeof(packet_len)) { + debug("Rx: too large packet: %d\n", packet_len); + return -EIO; + } + + /* + * For LAN7x, the length in command A does not + * include command A, B, and C length. + * So use it as is. + */ + + debug("Rx: cmd_a 0x%08X packet_len %d\n", rx_cmd_a, packet_len); + + /* Notify net stack */ + net_process_received_packet(buf_ptr + 10, packet_len); + } + + return err; +} + +int lan7x_free_pkt(struct udevice *dev, uchar *packet, int packet_len) +{ + struct lan7x_private *priv = dev_get_priv(dev); + + packet_len = ALIGN(packet_len, 4); + usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len); + + return 0; +} + +int lan7x_eth_remove(struct udevice *dev) +{ + struct lan7x_private *priv = dev_get_priv(dev); + + debug("** %s()\n", __func__); + free(priv->phydev); + mdio_unregister(priv->mdiobus); + mdio_free(priv->mdiobus); + + return 0; +} +#endif /* CONFIG_DM_ETH */ diff --git a/drivers/usb/eth/lan7x.h b/drivers/usb/eth/lan7x.h new file mode 100644 index 0000000..6f4647a --- /dev/null +++ b/drivers/usb/eth/lan7x.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <console.h> +#include <watchdog.h> + +/* USB Vendor Requests */ +#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 +#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 +#define USB_VENDOR_REQUEST_GET_STATS 0xA2 + +/* Tx Command A */ +#define TX_CMD_A_FCS BIT(22) +#define TX_CMD_A_LEN_MASK 0x000FFFFF + +/* Rx Command A */ +#define RX_CMD_A_RXE BIT(18) +#define RX_CMD_A_LEN_MASK 0x00003FFF + +/* SCSRs */ +#define ID_REV 0x00 +#define ID_REV_CHIP_ID_MASK 0xFFFF0000 +#define ID_REV_CHIP_ID_7500 0x7500 +#define ID_REV_CHIP_ID_7800 0x7800 +#define ID_REV_CHIP_ID_7850 0x7850 + +#define INT_STS 0x0C + +#define HW_CFG 0x010 +#define HW_CFG_LRST BIT(1) + +#define PMT_CTL 0x014 +#define PMT_CTL_PHY_PWRUP BIT(10) +#define PMT_CTL_READY BIT(7) +#define PMT_CTL_PHY_RST BIT(4) + +#define E2P_CMD 0x040 +#define E2P_CMD_EPC_BUSY BIT(31) +#define E2P_CMD_EPC_CMD_READ 0x00000000 +#define E2P_CMD_EPC_TIMEOUT BIT(10) +#define E2P_CMD_EPC_ADDR_MASK 0x000001FF + +#define E2P_DATA 0x044 + +#define RFE_CTL_BCAST_EN BIT(10) +#define RFE_CTL_DA_PERFECT BIT(1) + +#define FCT_RX_CTL_EN BIT(31) + +#define FCT_TX_CTL_EN BIT(31) + +#define MAC_CR 0x100 +#define MAC_CR_ADP BIT(13) +#define MAC_CR_AUTO_DUPLEX BIT(12) +#define MAC_CR_AUTO_SPEED BIT(11) + +#define MAC_RX 0x104 +#define MAC_RX_FCS_STRIP BIT(4) +#define MAC_RX_RXEN BIT(0) + +#define MAC_TX 0x108 +#define MAC_TX_TXEN BIT(0) + +#define FLOW 0x10C +#define FLOW_CR_TX_FCEN BIT(30) +#define FLOW_CR_RX_FCEN BIT(29) + +#define RX_ADDRH 0x118 +#define RX_ADDRL 0x11C + +#define MII_ACC 0x120 +#define MII_ACC_MII_READ 0x00000000 +#define MII_ACC_MII_WRITE 0x00000002 +#define MII_ACC_MII_BUSY BIT(0) + +#define MII_DATA 0x124 + +#define SS_USB_PKT_SIZE 1024 +#define HS_USB_PKT_SIZE 512 +#define FS_USB_PKT_SIZE 64 + +#define MAX_RX_FIFO_SIZE (12 * 1024) +#define MAX_TX_FIFO_SIZE (12 * 1024) +#define DEFAULT_BULK_IN_DELAY 0x0800 + +#define EEPROM_INDICATOR 0xA5 +#define EEPROM_MAC_OFFSET 0x01 + +/* Some extra defines */ +#define LAN7X_INTERNAL_PHY_ID 1 + +#define LAN7X_MAC_RX_MAX_SIZE(mtu) \ + ((mtu) << 16) /* Max frame size */ +#define LAN7X_MAC_RX_MAX_SIZE_DEFAULT \ + LAN7X_MAC_RX_MAX_SIZE(ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */) + +/* Timeouts */ +#define USB_CTRL_SET_TIMEOUT_MS 5000 +#define USB_CTRL_GET_TIMEOUT_MS 5000 +#define USB_BULK_SEND_TIMEOUT_MS 5000 +#define USB_BULK_RECV_TIMEOUT_MS 5000 +#define TIMEOUT_RESOLUTION_MS 50 +#define PHY_CONNECT_TIMEOUT_MS 5000 + +#define RX_URB_SIZE 2048 + +/* driver private */ +struct lan7x_private { + struct ueth_data ueth; + u32 chipid; /* Chip or device ID */ + struct mii_dev *mdiobus; + struct phy_device *phydev; +}; + +/* + * Lan7x infrastructure commands + */ + +int lan7x_write_reg(struct usb_device *udev, u32 index, u32 data); + +int lan7x_read_reg(struct usb_device *udev, u32 index, u32 *data); + +static inline int lan7x_wait_for_bit(struct usb_device *udev, + const char *prefix, const u32 reg, + const u32 mask, const bool set, + const unsigned int timeout_ms, + const bool breakable) +{ + u32 val; + unsigned long start = get_timer(0); + + while (1) { + lan7x_read_reg(udev, reg, &val); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > timeout_ms) + break; + + if (breakable && ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + + udelay(1); + WATCHDOG_RESET(); + } + + debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg, + mask, set); + + return -ETIMEDOUT; +} + +int lan7x_mdio_read(struct usb_device *udev, int phy_id, int idx); + +void lan7x_mdio_write(struct usb_device *udev, int phy_id, int idx, + int regval); + +static inline int lan7x_mdio_wait_for_bit(struct usb_device *udev, + const char *prefix, + int phy_id, const u32 reg, + const u32 mask, const bool set, + const unsigned int timeout_ms, + const bool breakable) +{ + u32 val; + unsigned long start = get_timer(0); + + while (1) { + val = lan7x_mdio_read(udev, phy_id, reg); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > timeout_ms) + break; + + if (breakable && ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + + udelay(1); + WATCHDOG_RESET(); + } + + debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg, + mask, set); + + return -ETIMEDOUT; +} + +int lan7x_phylib_register(struct udevice *udev); + +int lan7x_eth_phylib_connect(struct udevice *udev, struct ueth_data *dev); + +int lan7x_eth_phylib_config_start(struct udevice *udev); + +int lan7x_pmt_phy_reset(struct usb_device *udev, + struct ueth_data *dev); + +int lan7x_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev, + uint32_t *flow, uint32_t *fct_flow); + +int lan7x_read_eeprom_mac(unsigned char *enetaddr, struct usb_device *udev); + +int lan7x_basic_reset(struct usb_device *udev, + struct ueth_data *dev); + +#ifdef CONFIG_DM_ETH +void lan7x_eth_stop(struct udevice *dev); + +int lan7x_eth_send(struct udevice *dev, void *packet, int length); + +int lan7x_eth_recv(struct udevice *dev, int flags, uchar **packetp); + +int lan7x_free_pkt(struct udevice *dev, uchar *packet, int packet_len); + +int lan7x_eth_remove(struct udevice *dev); +#endif /* CONFIG_DM_ETH */ -- 2.7.4 Resending the patch adding Joe and Tom. I would appreciate your feedback. Yuiko

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[U-Boot] Rockchip nand boot image support in u-boot
by Paweł Jarosz 27 Jul '17

27 Jul '17

Hi, i wan't to add rockchip nand boot image support to u-boot. Format: * 512b rc4 encrypted boot header with size aligned to nand page size, * first 2048b rc4 encrypted tpl data aligned to nand page size * empty page * second 2048b rc4 encrypted tpl data aligned to nand page size * empty page * n 2048b rc4 encrypted tpl data aligned to nand page size ... * empty page * n 2048b rc4 encrypted spl data aligned to nand page size ... All must fit in one nand block/erase size. I can do it in two ways: 1. support it in mkimage, but to do that i need to pass some extra parameters to mkimage: nand page size, nand block size, number of empty pages in iteration, tpl and spl file name. 2. write an external tool. What is the best way to do that? (1 or 2) If 1 then what is the best way to pass this extra parameters (add a new arg option to mkimage ... -X mabe for extra params, or use external configuration file)? Regards Paweł

1 0

[U-Boot] [PATCH 1/2] rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) before SPL
by Philipp Tomsich 27 Jul '17

27 Jul '17

As our SPL stage can grow quite large (80KB+ are not unusual) on the RK3399-Q7, the default setting for the environment location (in include/configs/rockchip-common.h) can overlap our SPL. This change finally makes use of the 'u-boot,mmc-env-offset' DTS property to override the environment location and put it at 16KB into the device, which is right before the SPL (located at 32KB). Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- arch/arm/dts/rk3399-puma.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 1aad6c5..0491886 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -12,7 +12,8 @@ compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399"; config { - u-boot,spl-payload-offset = <0x40000>; /* 256kbyte */ + u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ + u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ u-boot,boot-led = "module_led"; }; -- 2.1.4

2 5

[U-Boot] [PATCH 1/4] rockchip: dts: correct vdd_log setting for firefly-rk3399
by Kever Yang 27 Jul '17

27 Jul '17

Add regulator-init-microvolt for driver to init the regulator, and the min output value is not 800000mV for the PWM2 io domain has changed to VCC3V0 instead of VCC1V8 in rockchip evb, we need to correct it with the value measured when PWM2 output HIGH. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/dts/rk3399-firefly.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index a3e9ddf..3d3f507 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -157,8 +157,9 @@ regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <430000>; regulator-max-microvolt = <1400000>; + regulator-init-microvolt = <950000>; }; vccadc_ref: vccadc-ref { -- 1.9.1

3 19

[U-Boot] [RFC PATCH] OMAP2PLUS boards' CONFIG_SYS_LOAD_ADDR to Kconfig
by Adam Ford 27 Jul '17

27 Jul '17

ti_armv7_common.h states the following: /* * Our DDR memory always starts at 0x80000000 and U-Boot shall have * relocated itself to higher in memory by the time this value is used. * However, set this to a 32MB offset to allow for easier Linux kernel * booting as the default is often used as the kernel load address. */ So when ARCH_OMAP2PLUS is defined, we'll default CONFIG_SYS_LOAD_ADDR to 0x82000000. However some boards manually defined theirs differently Boards who used OMAP34XX_SDRC_CS0 + 0x02000000 were left to the default Boards who used OMAP34XX_SDRC_CS0 are at 0x80000000 and any boards who had other values were automatically ported with the moveconfig tool. Adam Ford (1): Convert CONFIG_SYS_LOAD_ADDR to Kconfig Kconfig | 6 ++++++ arch/arm/mach-omap2/Kconfig | 3 +++ configs/am3517_crane_defconfig | 1 + configs/am3517_evm_defconfig | 1 + configs/brppt1_mmc_defconfig | 1 + configs/brppt1_nand_defconfig | 1 + configs/brppt1_spi_defconfig | 1 + configs/brxre1_defconfig | 1 + configs/cm_t35_defconfig | 1 + configs/cm_t54_defconfig | 2 +- configs/dra7xx_evm_defconfig | 2 +- configs/dra7xx_hs_evm_defconfig | 2 +- configs/draco_defconfig | 1 + configs/eco5pk_defconfig | 1 + configs/etamin_defconfig | 1 + configs/mcx_defconfig | 1 + configs/mt_ventoux_defconfig | 1 + configs/nokia_rx51_defconfig | 1 + configs/omap3_evm_defconfig | 1 + configs/omap3_ha_defconfig | 1 + configs/omap5_uevm_defconfig | 2 +- configs/pxm2_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/rut_defconfig | 1 + configs/tao3530_defconfig | 1 + configs/thuban_defconfig | 1 + configs/ti814x_evm_defconfig | 1 + configs/twister_defconfig | 1 + 28 files changed, 35 insertions(+), 4 deletions(-) -- 2.7.4

1 1

[U-Boot] [RESENT PATCH] rockchip: puma-rk3399: remove redundance code
by Kever Yang 27 Jul '17

27 Jul '17

Some code are duplicate, remove one of them Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- board/theobroma-systems/puma_rk3399/puma-rk3399.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 36e9cd7..5375247 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -9,22 +9,16 @@ #include <ram.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> -#include <misc.h> #include <asm/setup.h> #include <asm/arch/periph.h> #include <power/regulator.h> #include <u-boot/sha256.h> -#define RK3399_CPUID_OFF 0x7 -#define RK3399_CPUID_LEN 0x10 - DECLARE_GLOBAL_DATA_PTR; #define RK3399_CPUID_OFF 0x7 #define RK3399_CPUID_LEN 0x10 -DECLARE_GLOBAL_DATA_PTR; - int board_init(void) { struct udevice *pinctrl, *regulator; -- 1.9.1

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[U-Boot] [PATCH v3 00/10] make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN
by Andy Yan 27 Jul '17

27 Jul '17

Some platforms like RK3036 has very small sram to run spl code, so it has no enough sapce for so much malloc pool before relocation in spl stage as the normal u-boot stage. As the long discussion in [1] [2], I make this series out, try to make spl and normal u-boot stage use independent SYS_MALLOC_F_LEN. [1]https://lists.denx.de/pipermail/u-boot/2017-July/297370.html [2]https://lists.denx.de/pipermail/u-boot/2017-July/297504.html Changes in v3: - use CONFIG_VAL(), which suggested by Simon - disable SPL_DM_SERIAL - use puts instead of printf, which suggested by Simon Changes in v2: - introduce a new control CONFIG_SPL_SYS_MALLOC_F_LEN, adviced by Simon Andy Yan (10): make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN mips: spl and normal u-boot stage set SYS_MALLOC_F_LEN indepently powerpc: spl and normal u-boot stage set SYS_MALLOC_F_LEN indepently microblaze: spl and normal u-boot stage set SYS_MALLOC_F_LEN indepently sandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool size before relocation rockchip: set malloc pool size to 0 before relocation in spl state on rk3036 based board rockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036 rockchip: enable SPL_LIBGENERIC for rk3036 based boards rockchip: use puts instead of printf when back to bootrom rockchip: add u-boot specific dts for rk3036 sdk Kconfig | 10 ++++++++++ arch/arm/dts/rk3036-sdk-u-boot.dtsi | 11 +++++++++++ arch/arm/mach-rockchip/bootrom.c | 4 ++-- arch/arm/mach-rockchip/rk3036-board-spl.c | 6 ------ arch/microblaze/cpu/start.S | 8 ++++---- arch/mips/cpu/start.S | 6 +++--- arch/powerpc/cpu/mpc83xx/start.S | 8 ++++---- arch/powerpc/cpu/mpc85xx/start.S | 11 +++++------ arch/sandbox/cpu/start.c | 2 +- cmd/bdinfo.c | 4 ++-- common/Makefile | 4 +++- common/board_f.c | 4 ++-- common/board_r.c | 2 +- common/dlmalloc.c | 12 ++++++------ common/init/board_init.c | 8 ++++---- common/spl/spl.c | 8 ++++---- configs/evb-rk3036_defconfig | 7 ++++++- configs/kylin-rk3036_defconfig | 7 ++++++- drivers/core/Kconfig | 8 ++++---- drivers/serial/serial-uclass.c | 4 ++-- include/asm-generic/global_data.h | 2 +- lib/asm-offsets.c | 2 +- lib/efi/efi_app.c | 2 +- 23 files changed, 83 insertions(+), 57 deletions(-) create mode 100644 arch/arm/dts/rk3036-sdk-u-boot.dtsi -- 2.7.4

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[U-Boot] [Patch v2] Makefile: Concatenation of u-boot-spl.bin and u-boot.img
by Ashish Kumar 27 Jul '17

27 Jul '17

Concatenation of u-boot-spl.bin and u-boot.img for NXP layerscape platform SoC: LS1088A/LS2080A and their variants This patch also depricates UBOOT_BINLOAD in favour of SPL_PAYLOAD Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- v2: This is v2 version of https://patchwork.ozlabs.org/patch/755904/ Also considers recommendation made in following mail chain http://linux.freescale.net/pipermail/u-boot/2016-September/041592.html to depricate UBOOT_BINLOAD Makefile | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index 4c4c8d8..ff22bda 100644 --- a/Makefile +++ b/Makefile @@ -1030,8 +1030,20 @@ u-boot.dis: u-boot ifdef CONFIG_TPL SPL_PAYLOAD := tpl/u-boot-with-tpl.bin else +ifeq ($(ARCH),arm) +ifdef CONFIG_OF_CONTROL +SPL_PAYLOAD := u-boot-dtb.img +else +SPL_PAYLOAD := u-boot.img +endif #ifdef CONFIG_OF_CONTROL +else +ifdef CONFIG_OF_CONTROL +SPL_PAYLOAD := u-boot-dtb.bin +else SPL_PAYLOAD := u-boot.bin -endif +endif #ifdef CONFIG_OF_CONTROL +endif #ifdef arm +endif #ifdef CONFIG_TPL OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) @@ -1194,16 +1206,11 @@ MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) -ifeq ($(ARCH),arm) -UBOOT_BINLOAD := u-boot.img -else -UBOOT_BINLOAD := u-boot.bin -endif OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ --gap-fill=0xff -u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE +u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) # PPC4xx needs the SPL at the end of the image, since the reset vector -- 2.7.4

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