May 2017 - U-Boot

[U-Boot] [PATCH v4 0/7] am57xx: cl-som-am57x: fix usb
by Uri Mashiach 08 May '17

08 May '17

Various USB related comits for the CL-SOM-AM57x module. --- V1 -> V2: Replace commit "fix XHCI registers base address" with "reintroduce the CONFIG_AM57XX symbol". V2 -> V3: * New commit "move CONFIG_DRA7XX to Kconfig" * Replace commit "reintroduce the CONFIG_AM57XX symbol" with "xHCI registers based on USB port index" V3 -> V4: Update commit "move CONFIG_DRA7XX to Kconfig" Update commit "xHCI registers based on USB port index" Uri Mashiach (7): arm: dra7xx: move CONFIG_DRA7XX to Kconfig arm: usb: dra7xx: xHCI registers based on USB port index usb: host: xhci-omap: fix double weak board_usb_init functions arm: am57xx: cl-som-am57x: invoke clock API to enable/disable clocks arm: am57xx: cl-som-am57x: fix USB scan arm: am57xx: cl-som-am57x: enable USB storage arm: am57xx: cl-som-am57x: enable USB commands arch/arm/mach-omap2/omap5/Kconfig | 8 ++++++++ board/compulab/cl-som-am57x/cl-som-am57x.c | 10 ---------- board/ti/am43xx/board.c | 4 ++-- board/ti/am57xx/board.c | 4 ++-- board/ti/dra7xx/evm.c | 4 ++-- configs/cl-som-am57x_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 1 + configs/dra7xx_hs_evm_defconfig | 1 + drivers/usb/host/Kconfig | 9 +++++++++ drivers/usb/host/xhci-omap.c | 19 +++++++++++++++++-- include/configs/am57xx_evm.h | 2 -- include/configs/cl-som-am57x.h | 6 ++---- include/configs/dra7xx_evm.h | 2 -- include/linux/usb/xhci-omap.h | 6 ++++-- scripts/config_whitelist.txt | 1 - 15 files changed, 50 insertions(+), 29 deletions(-) -- 2.7.4

5 38

[U-Boot] [PATCHv2 1/5] ARM64: dts: hi3798cv200-poplar: add device tree bindings
by Jorge Ramirez-Ortiz 08 May '17

08 May '17

pulled from linux-next tag 20170505 Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz(a)linaro.org> --- arch/arm/dts/hi3798cv200-poplar.dts | 162 +++++++++++++ arch/arm/dts/hi3798cv200.dtsi | 411 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/histb-clock.h | 66 +++++ include/dt-bindings/reset/ti-syscon.h | 38 +++ 4 files changed, 677 insertions(+) create mode 100644 arch/arm/dts/hi3798cv200-poplar.dts create mode 100644 arch/arm/dts/hi3798cv200.dtsi create mode 100644 include/dt-bindings/clock/histb-clock.h create mode 100644 include/dt-bindings/reset/ti-syscon.h diff --git a/arch/arm/dts/hi3798cv200-poplar.dts b/arch/arm/dts/hi3798cv200-poplar.dts new file mode 100644 index 0000000..b914287 --- /dev/null +++ b/arch/arm/dts/hi3798cv200-poplar.dts @@ -0,0 +1,162 @@ +/* + * DTS File for HiSilicon Poplar Development Board + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "hi3798cv200.dtsi" + +/ { + model = "HiSilicon Poplar Development Board"; + compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; + + aliases { + serial0 = &uart0; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + + user-led0 { + label = "USER-LED0"; + gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user-led1 { + label = "USER-LED1"; + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + user-led2 { + label = "USER-LED2"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + user-led3 { + label = "USER-LED3"; + gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + }; +}; + +&gmac1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&eth_phy1>; + phy-mode = "rgmii"; + hisilicon,phy-reset-delays-us = <10000 10000 30000>; + + eth_phy1: phy@3 { + reg = <3>; + }; +}; + +&gpio1 { + status = "okay"; + gpio-line-names = "LS-GPIO-E", "", + "", "", + "", "LS-GPIO-F", + "", "LS-GPIO-J"; +}; + +&gpio2 { + status = "okay"; + gpio-line-names = "LS-GPIO-H", "LS-GPIO-I", + "LS-GPIO-L", "LS-GPIO-G", + "LS-GPIO-K", "", + "", ""; +}; + +&gpio3 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "LS-GPIO-C", "", + "", "LS-GPIO-B"; +}; + +&gpio4 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "", "LS-GPIO-D", + "", ""; +}; + +&gpio5 { + status = "okay"; + gpio-line-names = "", "USER-LED-1", + "USER-LED-2", "", + "", "LS-GPIO-A", + "", ""; +}; + +&gpio6 { + status = "okay"; + gpio-line-names = "", "", + "", "USER-LED-0", + "", "", + "", ""; +}; + +&gpio10 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "", "", + "USER-LED-3", ""; +}; + +&i2c0 { + status = "okay"; + label = "LS-I2C0"; +}; + +&i2c2 { + status = "okay"; + label = "LS-I2C1"; +}; + +&ir { + status = "okay"; +}; + +&spi0 { + status = "okay"; + label = "LS-SPI0"; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + label = "LS-UART0"; +}; +/* No optional LS-UART1 on Low Speed Expansion Connector. */ diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi new file mode 100644 index 0000000..75865f8 --- /dev/null +++ b/arch/arm/dts/hi3798cv200.dtsi @@ -0,0 +1,411 @@ +/* + * DTS File for HiSilicon Hi3798cv200 SoC. + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <dt-bindings/clock/histb-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/ti-syscon.h> + +/ { + compatible = "hisilicon,hi3798cv200"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ + <0x0 0xf1002000 0x0 0x100>; /* GICC */ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + soc: soc@f0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xf0000000 0x10000000>; + + crg: clock-reset-controller@8a22000 { + compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; + reg = <0x8a22000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + + gmacphyrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = + <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | + DEASSERT_SET|STATUS_NONE)>, + <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | + DEASSERT_SET|STATUS_NONE)>; + }; + }; + + sysctrl: system-controller@8000000 { + compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; + reg = <0x8000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + uart0: serial@8b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x8b00000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl HISTB_UART0_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@8b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x8b02000 0x1000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_UART2_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@8b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b10000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C0_CLK>; + status = "disabled"; + }; + + i2c1: i2c@8b11000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b11000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C1_CLK>; + status = "disabled"; + }; + + i2c2: i2c@8b12000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b12000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C2_CLK>; + status = "disabled"; + }; + + i2c3: i2c@8b13000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b13000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C3_CLK>; + status = "disabled"; + }; + + i2c4: i2c@8b14000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b14000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C4_CLK>; + status = "disabled"; + }; + + spi0: spi@8b1a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x8b1a000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + cs-gpios = <&gpio7 1 0>; + clocks = <&crg HISTB_SPI0_CLK>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emmc: mmc@9830000 { + compatible = "snps,dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>; + clock-names = "ciu", "biu"; + }; + + gpio0: gpio@8b20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b20000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio1: gpio@8b21000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b21000 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio2: gpio@8b22000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b22000 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio3: gpio@8b23000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b23000 0x1000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio4: gpio@8b24000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b24000 0x1000>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio5: gpio@8004000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8004000 0x1000>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio6: gpio@8b26000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b26000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio7: gpio@8b27000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b27000 0x1000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio8: gpio@8b28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b28000 0x1000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio9: gpio@8b29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b29000 0x1000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio10: gpio@8b2a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2a000 0x1000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio11: gpio@8b2b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2b000 0x1000>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio12: gpio@8b2c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2c000 0x1000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gmac0: ethernet@9840000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0x9840000 0x1000>, + <0x984300c 0x4>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH0_MAC_CLK>, + <&crg HISTB_ETH0_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 8>, + <&crg 0xcc 10>, + <&gmacphyrst 0>; + reset-names = "mac_core", "mac_ifc", "phy"; + status = "disabled"; + }; + + gmac1: ethernet@9841000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0x9841000 0x1000>, + <0x9843010 0x4>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH1_MAC_CLK>, + <&crg HISTB_ETH1_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 9>, + <&crg 0xcc 11>, + <&gmacphyrst 1>; + reset-names = "mac_core", "mac_ifc", "phy"; + status = "disabled"; + }; + + ir: ir@8001000 { + compatible = "hisilicon,hix5hd2-ir"; + reg = <0x8001000 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl HISTB_IR_CLK>; + status = "disabled"; + }; + }; +}; diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h new file mode 100644 index 0000000..181c0f0 --- /dev/null +++ b/include/dt-bindings/clock/histb-clock.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __DTS_HISTB_CLOCK_H +#define __DTS_HISTB_CLOCK_H + +/* clocks provided by core CRG */ +#define HISTB_OSC_CLK 0 +#define HISTB_APB_CLK 1 +#define HISTB_AHB_CLK 2 +#define HISTB_UART1_CLK 3 +#define HISTB_UART2_CLK 4 +#define HISTB_UART3_CLK 5 +#define HISTB_I2C0_CLK 6 +#define HISTB_I2C1_CLK 7 +#define HISTB_I2C2_CLK 8 +#define HISTB_I2C3_CLK 9 +#define HISTB_I2C4_CLK 10 +#define HISTB_I2C5_CLK 11 +#define HISTB_SPI0_CLK 12 +#define HISTB_SPI1_CLK 13 +#define HISTB_SPI2_CLK 14 +#define HISTB_SCI_CLK 15 +#define HISTB_FMC_CLK 16 +#define HISTB_MMC_BIU_CLK 17 +#define HISTB_MMC_CIU_CLK 18 +#define HISTB_MMC_DRV_CLK 19 +#define HISTB_MMC_SAMPLE_CLK 20 +#define HISTB_SDIO0_BIU_CLK 21 +#define HISTB_SDIO0_CIU_CLK 22 +#define HISTB_SDIO0_DRV_CLK 23 +#define HISTB_SDIO0_SAMPLE_CLK 24 +#define HISTB_PCIE_AUX_CLK 25 +#define HISTB_PCIE_PIPE_CLK 26 +#define HISTB_PCIE_SYS_CLK 27 +#define HISTB_PCIE_BUS_CLK 28 +#define HISTB_ETH0_MAC_CLK 29 +#define HISTB_ETH0_MACIF_CLK 30 +#define HISTB_ETH1_MAC_CLK 31 +#define HISTB_ETH1_MACIF_CLK 32 +#define HISTB_COMBPHY1_CLK 33 + + +/* clocks provided by mcu CRG */ +#define HISTB_MCE_CLK 1 +#define HISTB_IR_CLK 2 +#define HISTB_TIMER01_CLK 3 +#define HISTB_LEDC_CLK 4 +#define HISTB_UART0_CLK 5 +#define HISTB_LSADC_CLK 6 + +#endif /* __DTS_HISTB_CLOCK_H */ diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h new file mode 100644 index 0000000..884fd91 --- /dev/null +++ b/include/dt-bindings/reset/ti-syscon.h @@ -0,0 +1,38 @@ +/* + * TI Syscon Reset definitions + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ +#define __DT_BINDINGS_RESET_TI_SYSCON_H__ + +/* + * The reset does not support the feature and corresponding + * values are not valid + */ +#define ASSERT_NONE (1 << 0) +#define DEASSERT_NONE (1 << 1) +#define STATUS_NONE (1 << 2) + +/* When set this function is activated by setting(vs clearing) this bit */ +#define ASSERT_SET (1 << 3) +#define DEASSERT_SET (1 << 4) +#define STATUS_SET (1 << 5) + +/* The following are the inverse of the above and are added for consistency */ +#define ASSERT_CLEAR (0 << 3) +#define DEASSERT_CLEAR (0 << 4) +#define STATUS_CLEAR (0 << 5) + +#endif -- 2.7.4

3 10

[U-Boot] [PATCH 1/2] arm: change tbu/l type to unsigned int
by Peng Fan 08 May '17

08 May '17

Change tbu/l type to unsigned int. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> --- arch/arm/include/asm/global_data.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index dfcbcce..92d9c97 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -32,8 +32,8 @@ struct arch_global_data { #endif /* "static data" needed by most of timer.c on ARM platforms */ unsigned long timer_rate_hz; - unsigned long tbu; - unsigned long tbl; + unsigned int tbu; + unsigned int tbl; unsigned long lastinc; unsigned long long timer_reset_value; #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) -- 2.6.6

4 7

[U-Boot] sunxi: support NanoPi Neo2
by Patrick Wildt 08 May '17

08 May '17

Hi, this diff adds basic support for the NanoPi Neo2. It's based on the old NanoPi Neo support and the recent commit of the OrangePi PC2 support. I'm not sure it's 100% correct, but it seems to be a good start to me and makes the machine boot. Tested with Andre's SPL FIT patchset. Patrick diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f3f53f3..4a36036 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -310,6 +310,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ sun8i-v3s-licheepi-zero.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-nanopi-neo2.dtb \ sun50i-h5-orangepi-pc2.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-pine64-plus.dtb \ diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts new file mode 100644 index 0000000..4932855 --- /dev/null +++ b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2016 James Pettigrew <james(a)innovum.com.au> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "FriendlyARM NanoPi NEO2"; + compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; + + cpus { + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x40000000 0x20000000>; + }; + + aliases { + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + status { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ + }; + }; + + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; + }; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + leds_opc: led-pins { + allwinner,pins = "PA10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_opc: led-pins { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB Type-A port's VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <&reg_usb0_vbus>; + status = "okay"; +}; + +&emac { + phy = <&phy1>; + phy-mode = "mii"; + allwinner,use-internal-phy; + allwinner,leds-active-low; + status = "okay"; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig new file mode 100644 index 0000000..74c7d74 --- /dev/null +++ b/configs/nanopi_neo2_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_SPL=y +CONFIG_DRAM_CLK=504 +CONFIG_DRAM_ZQ=3881977 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y

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[U-Boot] [PATCH] power: rk8xx: fix auto-allocation of priv
by Philipp Tomsich 07 May '17

07 May '17

The recent changes to the RK808 driver caused our BSP to sync-abort in the regulator framework, when setting (or rather 'auto-setting') some of the LDOs. Turns out that the auto-allocation of the priv-structure in the rk8xx driver was never properly wired up... this commit fixes this issue by setting the .priv_auto_alloc_size-field in the driver structure. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- drivers/power/pmic/rk8xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 394e2ff..ff3bff0 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -115,4 +115,5 @@ U_BOOT_DRIVER(pmic_rk8xx) = { #endif .probe = rk8xx_probe, .ops = &rk8xx_ops, + .priv_auto_alloc_size = sizeof(struct rk8xx_priv), }; -- 1.9.1

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[U-Boot] reverse engineering a Philips photoframe
by Walter Heck 07 May '17

07 May '17

Hi all, I'm completely new to the world of U-boot, so please forgive me if I spout nonsense. I'm looking for a bit of guidance. I'm reverse engineering an old Philips 10FF2 Photoframe, hoping to one day customize it, just for the fun of it. I've been researching quite a bit and after downloading an updated firmware from the philips site and unpacking it, I notice it contains (among a bunch of others) 3 files of interest: 1) UBLDM350.BIN, sized at about 23k. The binwalk utility tells me it contains "ARM executable code, 32-bit, little endian, at least 984 valid instructions". I'm guessing this is uboot, not sure how I can confirm? 2) A file called Philips.cmd, containing a very simple script which among a lot of other stuff has a line that says: "//[UPDATE BOOTLOADER]" 3) A file called P350MAIN.BIN, which I have no real idea what it contains yet. It's about 2.3MB large and using a tool called mediaextract I was able to extract at least some JPEGs that contain artwork for the menu of the picture frame. Now, I have a bunch of questions: 1) How can I confirm this is indeed uboot? How would I know if it's stock UBoot or a modified version? 2) Can I compile uboot myself and replace this one without bricking my frame? 3) As far as I understand Uboot loads the actual OS. Would it be possible the P350MAIN.BIN file is that OS? Any input is welcome. To be clear here I'm not doing this out of commercial interest, just trying to customise this frame for fun. kind regards, -- Walter Heck

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[U-Boot] [PATCH 1/1] odroid-c2: increase CONFIG_SYS_BOOTM_LEN
by Heinrich Schuchardt 07 May '17

07 May '17

A feature rich Kernel for Linux needs more than 8 MiB. Hence enlarge CONFIG_SYS_BOOTM_LEN to 64 MiB for the Odroid C2. As the Odroid C2 has has 2 GiB of RAM this poses no problem. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- include/configs/meson-gxbb-common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index c3229ea..e993263 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -54,4 +54,6 @@ MESON_FDTFILE_SETTING \ BOOTENV +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ + #endif /* __MESON_GXBB_COMMON_CONFIG_H */ -- 2.1.4

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[U-Boot] [PATCH] board/BuR/common: incorrect check of dtb
by Heinrich Schuchardt 07 May '17

07 May '17

The logical expression to check the dtb is incorrect in load_devicetree. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- I do not have a board for testing. Please, review carefully. --- board/BuR/common/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 876150402c..c0316b9ebd 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -265,7 +265,7 @@ static int load_devicetree(void) char *dtbname = getenv("dtb"); char *dtbdev = getenv("dtbdev"); char *dtppart = getenv("dtbpart"); - if (!dtbdev || !dtbdev || !dtbname) { + if (!dtbdev || !dtbpart || !dtbname) { printf("%s: <dtbdev>/<dtbpart>/<dtb> missing.\n", __func__); return -1; } -- 2.11.0

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[U-Boot] [PATCH 1/1] tools: sunxi: avoid possible null pointer dereference
by Heinrich Schuchardt 07 May '17

07 May '17

If endptr is NULL we should not dereference it. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- tools/sunxi-spl-image-builder.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/sunxi-spl-image-builder.c b/tools/sunxi-spl-image-builder.c index d538a38813..0072a64728 100644 --- a/tools/sunxi-spl-image-builder.c +++ b/tools/sunxi-spl-image-builder.c @@ -433,7 +433,7 @@ int main(int argc, char **argv) break; case 'c': info.ecc_strength = strtol(optarg, &endptr, 0); - if (endptr || *endptr == '/') + if (endptr && *endptr == '/') info.ecc_step_size = strtol(endptr + 1, NULL, 0); break; case 'p': -- 2.11.0

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[U-Boot] [PATCH 1/1] arm64: mvebu: incorrect check of fdt address cells
by Heinrich Schuchardt 07 May '17

07 May '17

In dram_init_banksize there seems to be a typo concerning a plausibility check of the fdt. Testing sc > 2 twice does not make any sense. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- I do not have a board for testing. So review carefully. --- arch/arm/mach-mvebu/arm64-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 1c0477a3ca..2ef5726905 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -94,7 +94,7 @@ int dram_init_banksize(void) ac = fdt_address_cells(fdt, 0); sc = fdt_size_cells(fdt, 0); - if (ac < 1 || sc > 2 || sc < 1 || sc > 2) { + if (ac < 1 || ac > 2 || sc < 1 || sc > 2) { printf("invalid address/size cells\n"); return -ENXIO; } -- 2.11.0

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