May 2017 - U-Boot

[U-Boot] [PATCH 1/2] ARM: dts: exynos5422-odroidxu3: add the LDO's nodes
by Jaehoon Chung 05 Jun '17

05 Jun '17

Add the LDO's nodes that taken from Linux Kernel. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- arch/arm/dts/exynos5422-odroidxu3.dts | 209 ++++++++++++++++++++++++++++++++++ 1 file changed, 209 insertions(+) diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index 690c747..b6f4333 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -40,6 +40,215 @@ s2mps11_pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vddq_mmc0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo4_reg: LDO4 { + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vddq_mmc2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "vdd_ldo16"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "tsp_avdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo18_reg: LDO18 { + regulator-name = "vdd_emmc_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo24_reg: LDO24 { + regulator-name = "tsp_io"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo26_reg: LDO26 { + regulator-name = "vdd_ldo26"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_mem"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1.0v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_1.8v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2.8v_ldo"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3750000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_vmem"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + }; }; }; -- 2.10.2

2 2

[U-Boot] [PATCH 0/2] Enable the CONFIG_DM_MMC for Exynos4 series
by Jaehoon Chung 05 Jun '17

05 Jun '17

Enable the CONFIG_DM_MMC for Exynos4 series. To use this, change the nodes relevant to mmc/sd in each dts. Tested with trats/trats2/universal_c210/odroid. But i didn't test origen board..someone can test it. It's helpful. Jaehoon Chung (2): ARM: dts: exynos4: change the nodes relevant to mmc/sd configs: enable the CONFIG_DM_MMC for exynos4 series arch/arm/dts/exynos4.dtsi | 25 +++++++++------ arch/arm/dts/exynos4210-origen.dts | 24 ++++---------- arch/arm/dts/exynos4210-trats.dts | 40 +++++++++--------------- arch/arm/dts/exynos4210-universal_c210.dts | 36 +++++++++------------ arch/arm/dts/exynos4412-odroid.dts | 50 ++++++++++++------------------ arch/arm/dts/exynos4412-trats2.dts | 49 +++++++++++++++-------------- arch/arm/dts/exynos4x12.dtsi | 13 -------- configs/odroid_defconfig | 1 + configs/origen_defconfig | 1 + configs/s5pc210_universal_defconfig | 1 + configs/trats2_defconfig | 1 + configs/trats_defconfig | 1 + 12 files changed, 99 insertions(+), 143 deletions(-) -- 2.10.2

2 4

[U-Boot] [PATCH 01/33] mmc: select the available type from host_caps and card_caps
by Ziyuan Xu 05 Jun '17

05 Jun '17

The original implementation select HS timing by default, add available type selection for higher speed mode compatibility, such as hs200, hs400, hs400es. By the way, we assume that card run at 1.8V or 1.2V I/O when its timing is ddr52/hs200/hs400(es). Signed-off-by: Ziyuan Xu <xzy.xu(a)rock-chips.com> --- drivers/mmc/mmc.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- include/mmc.h | 16 +++++++++++++++ 2 files changed, 74 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 72fc177..f5b2280 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -546,10 +546,62 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) } +static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd) +{ + u8 card_type; + u32 host_caps, avail_type = 0; + + card_type = ext_csd[EXT_CSD_CARD_TYPE]; + host_caps = mmc->cfg->host_caps; + + if ((host_caps & MMC_MODE_HS) && + (card_type & EXT_CSD_CARD_TYPE_26)) + avail_type |= EXT_CSD_CARD_TYPE_26; + + if ((host_caps & MMC_MODE_HS) && + (card_type & EXT_CSD_CARD_TYPE_52)) + avail_type |= EXT_CSD_CARD_TYPE_52; + + /* + * For the moment, u-boot doesn't support signal voltage + * switch, therefor we assume that host support ddr52 + * at 1.8v or 3.3v I/O(1.2v I/O not supported, hs200 and + * hs400 are the same). + */ + if ((host_caps & MMC_MODE_DDR_52MHz) && + (card_type & EXT_CSD_CARD_TYPE_DDR_1_8V)) + avail_type |= EXT_CSD_CARD_TYPE_DDR_1_8V; + + if ((host_caps & MMC_MODE_HS200) && + (card_type & EXT_CSD_CARD_TYPE_HS200_1_8V)) + avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V; + + /* + * If host can support HS400, it means that host can also + * support HS200. + */ + if ((host_caps & MMC_MODE_HS400) && + (host_caps & MMC_MODE_8BIT) && + (card_type & EXT_CSD_CARD_TYPE_HS400_1_8V)) + avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V | + EXT_CSD_CARD_TYPE_HS400_1_8V; + + if ((host_caps & MMC_MODE_HS400ES) && + (host_caps & MMC_MODE_8BIT) && + ext_csd[EXT_CSD_STROBE_SUPPORT] && + (avail_type & EXT_CSD_CARD_TYPE_HS400_1_8V)) + avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V | + EXT_CSD_CARD_TYPE_HS400_1_8V | + EXT_CSD_CARD_TYPE_HS400ES; + + return avail_type; +} + static int mmc_change_freq(struct mmc *mmc) { ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); char cardtype; + u32 avail_type; int err; mmc->card_caps = 0; @@ -569,8 +621,13 @@ static int mmc_change_freq(struct mmc *mmc) return err; cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; + avail_type = mmc_select_card_type(mmc, ext_csd); - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); + if (avail_type & EXT_CSD_CARD_TYPE_HS) + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_HS_TIMING, 1); + else + err = -EINVAL; if (err) return err; diff --git a/include/mmc.h b/include/mmc.h index fad12d6..0bae1a1 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -58,6 +58,9 @@ #define MMC_MODE_8BIT (1 << 3) #define MMC_MODE_SPI (1 << 4) #define MMC_MODE_DDR_52MHz (1 << 5) +#define MMC_MODE_HS200 (1 << 6) +#define MMC_MODE_HS400 (1 << 7) +#define MMC_MODE_HS400ES (1 << 8) #define SD_DATA_4BIT 0x00040000 @@ -182,6 +185,7 @@ #define EXT_CSD_BOOT_BUS_WIDTH 177 #define EXT_CSD_PART_CONF 179 /* R/W */ #define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_STROBE_SUPPORT 184 /* RO */ #define EXT_CSD_HS_TIMING 185 /* R/W */ #define EXT_CSD_REV 192 /* RO */ #define EXT_CSD_CARD_TYPE 196 /* RO */ @@ -201,6 +205,18 @@ #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_26 | \ + EXT_CSD_CARD_TYPE_52) +#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ + EXT_CSD_CARD_TYPE_HS200_1_2V) +#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) /* Card can run at 200MHz DDR, 1.8V */ +#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) /* Card can run at 200MHz DDR, 1.2V */ +#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ + EXT_CSD_CARD_TYPE_HS400_1_2V) +#define EXT_CSD_CARD_TYPE_HS400ES BIT(8) /* Card can run at HS400ES */ + #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ -- 2.7.4

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[U-Boot] [PATCH] Kconfig: Add description for CMD_POWEROFF
by Michal Simek 04 Jun '17

04 Jun '17

Add poweroff description to Kconfig to make it selectable via menuconfig. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- cmd/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 5ee52f62cc14..e2250cabfe12 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -266,7 +266,10 @@ config CMD_XIMG Extract a part of a multi-image. config CMD_POWEROFF - bool + bool "poweroff" + default n + help + Poweroff/Shutdown the system endmenu -- 1.9.1

3 2

[U-Boot] [PATCH 00/12] Big work on sunxi DW DRAM controllers and some new DDR type support
by Icenowy Zheng 03 Jun '17

03 Jun '17

This patchset contains several works on the sunxi DesignWare DRAM controllers. The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers. The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit). The 4th patch adds bank detection code, in order to support some DDR2 chips. The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3. The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled. The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip. The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source) The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3. Icenowy Zheng (12): sunxi: makes an invisible option for H3-like DRAM controllers sunxi: Rename bus-width related macros in H3 DRAM code sunxi: add option for 16-bit DW DRAM controller sunxi: add bank detection code to H3 DRAM initialization code sunxi: Add selective DRAM type and timing sunxi: enable dual rank detection in DesignWare-like DRAM code sunxi: add support for the DDR2 in V3s SoC sunxi: add support for V3s DRAM controller sunxi: enable DRAM initialization and SPL for V3s SoC sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller sunxi: add LPDDR3 timing from stock boot0 sunxi: add a defconfig for SoPine w/ official baseboard arch/arm/include/asm/arch-sunxi/dram.h | 6 +- .../{dram_sun8i_h3.h => dram_sunxi_dw.h} | 36 +++- arch/arm/mach-sunxi/Makefile | 5 +- .../{dram_sun8i_h3.c => dram_sunxi_dw.c} | 187 +++++++-------------- arch/arm/mach-sunxi/dram_timings/Makefile | 3 + arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c | 84 +++++++++ arch/arm/mach-sunxi/dram_timings/ddr3_1333.c | 87 ++++++++++ arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c | 84 +++++++++ board/sunxi/Kconfig | 75 ++++++++- configs/sopine_baseboard_defconfig | 22 +++ 10 files changed, 454 insertions(+), 135 deletions(-) rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (86%) rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (84%) create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c create mode 100644 configs/sopine_baseboard_defconfig -- 2.12.2

5 25

[U-Boot] [RESEND PATCH v2 0/5] net/pch_gbe: updates for MIPS Boston board
by Daniel Schwierzeck 02 Jun '17

02 Jun '17

This series is a resend of selected net/pch_gbe patches from the original patch series [1] which was blocked by other patch series. This series only contains the net/pch_gbe patches required for MIPS Boston board, but whose can be separately applied. [1] https://lists.denx.de/pipermail/u-boot/2016-September/268137.html Changes in v2: - move the switch to dm_pci_virt_to_mem() in pch_gbe_rx_descs_init() to the next patch as suggested by Bin Meng - move the switch to dm_pci_virt_to_mem() in pch_gbe_rx_descs_init() from the previous patch to this one as suggested by Bin Meng Paul Burton (5): net: pch_gbe: Reset during probe net: pch_gbe: Fix rx descriptor buffer addresses net: pch_gbe: CPU accessible addresses are virtual net: pch_gbe: Add cache maintenance net: pch_gbe: Support PHY reset GPIOs drivers/net/pch_gbe.c | 71 +++++++++++++++++++++++++++++++++++++++++---------- drivers/net/pch_gbe.h | 1 + 2 files changed, 58 insertions(+), 14 deletions(-) -- 2.11.0

4 21

[U-Boot] [PATCH 1/2] net: zynq_gem: Use wait_for_bit with non breakable
by Michal Simek 02 Jun '17

02 Jun '17

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Use wait_for_bit to be non breakable as using it with breakable causes issue of un interruptible auto negotiation. This is due to the ctrlc pressed will taken for wait_for_bit() abort during phy_read() and hence not coming out of auto negotiation. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/zynq_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 357f8c2917d2..9c0f5fba28cd 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -192,7 +192,7 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, int err; err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, - true, 20000, true); + true, 20000, false); if (err) return err; @@ -205,7 +205,7 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, writel(mgtcr, &regs->phymntnc); err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, - true, 20000, true); + true, 20000, false); if (err) return err; -- 1.9.1

2 5

[U-Boot] [PATCH] net: phy: marvell 88e151x: Fix handling of RGMII interface types
by Phil Edworthy 02 Jun '17

02 Jun '17

The 88E1518 code is programming the wrong registers for rgmii-id, rgmii-txid and rgmii-rxid interfaces. Since the PHY defaults to rgmii-id, it would appear that the code was previously only used with sgmii and rgmii-id interfaces. Tested on 88E1512 PHY in rgmii-id mode which is from the same family as 88E1518. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- drivers/net/phy/marvell.c | 45 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index ab0c443..8041922 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -13,6 +13,8 @@ #define PHY_AUTONEGOTIATE_TIMEOUT 5000 +#define MII_MARVELL_PHY_PAGE 22 + /* 88E1011 PHY Status Register */ #define MIIM_88E1xxx_PHY_STATUS 0x11 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 @@ -83,6 +85,11 @@ #define MIIM_88E1310_PHY_PAGE 22 /* 88E151x PHY defines */ +/* Page 2 registers */ +#define MIIM_88E151x_PHY_MSCR 21 +#define MIIM_88E151x_RGMII_RX_DELAY BIT(5) +#define MIIM_88E151x_RGMII_TX_DELAY BIT(4) +#define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4)) /* Page 3 registers */ #define MIIM_88E151x_LED_FUNC_CTRL 16 #define MIIM_88E151x_LED_FLD_SZ 4 @@ -295,6 +302,8 @@ void m88e1518_phy_writebits(struct phy_device *phydev, static int m88e1518_config(struct phy_device *phydev) { + u16 reg; + /* * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 * /88E1514 Rev A0, Errata Section 3.1 @@ -331,7 +340,41 @@ static int m88e1518_config(struct phy_device *phydev) udelay(100); } - return m88e1111s_config(phydev); + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + reg = phy_read(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR); + + reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); + reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; + reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR, reg); + } + + if (phy_interface_is_rgmii(phydev)) { + phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); + reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + reg |= MIIM_88E151x_RGMII_RXTX_DELAY; + else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + reg |= MIIM_88E151x_RGMII_RX_DELAY; + else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + reg |= MIIM_88E151x_RGMII_TX_DELAY; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0); + } + + /* soft reset */ + phy_reset(phydev); + + genphy_config_aneg(phydev); + genphy_restart_aneg(phydev); + + return 0; } /* Marvell 88E1510 */ -- 2.7.4

2 2

[U-Boot] [PATCH 1/1] net: core: avoid possible NULL pointer dereference
by Heinrich Schuchardt 02 Jun '17

02 Jun '17

Checking if dev is NULL after dereferencing it does not make sense. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- net/eth-uclass.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index c3cc3152a2..b659961a5d 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -181,7 +181,7 @@ int eth_get_dev_index(void) static int eth_write_hwaddr(struct udevice *dev) { - struct eth_pdata *pdata = dev->platdata; + struct eth_pdata *pdata; int ret = 0; if (!dev || !device_active(dev)) @@ -189,6 +189,7 @@ static int eth_write_hwaddr(struct udevice *dev) /* seq is valid since the device is active */ if (eth_get_ops(dev)->write_hwaddr && !eth_mac_skip(dev->seq)) { + pdata = dev->platdata; if (!is_valid_ethaddr(pdata->enetaddr)) { printf("\nError: %s address %pM illegal value\n", dev->name, pdata->enetaddr); -- 2.11.0

2 2

[U-Boot] [PATCH] drivers: net: cpsw: abort init() on aneg timeout
by Sekhar Nori 02 Jun '17

02 Jun '17

Abort CPSW driver init when auto-negotiation of link times out. Currently, the code ignores return status of phy_startup(), and goes ahead with network operation (like DHCP) even though the link may be down. Instead, abort init process if link is down or if there is another error, so phy_startup() can easily be retried again. This also helps quick fallback to next network interface (like USB RNDIS) without inordinate delay. Tested on AM571x IDK and AM335x BeagleBone black. Signed-off-by: Sekhar Nori <nsekhar(a)ti.com> --- drivers/net/cpsw.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 5fbab9e492f8..d85a25904d02 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -612,21 +612,25 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave, #endif } -static void cpsw_slave_update_link(struct cpsw_slave *slave, +static int cpsw_slave_update_link(struct cpsw_slave *slave, struct cpsw_priv *priv, int *link) { struct phy_device *phy; u32 mac_control = 0; + int ret = -ENODEV; phy = priv->phydev; - if (!phy) - return; + goto out; + + ret = phy_startup(phy); + if (ret) + goto out; - phy_startup(phy); - *link = phy->link; + if (link) + *link = phy->link; - if (*link) { /* link up */ + if (phy->link) { /* link up */ mac_control = priv->data.mac_control; if (phy->speed == 1000) mac_control |= GIGABITEN; @@ -637,7 +641,7 @@ static void cpsw_slave_update_link(struct cpsw_slave *slave, } if (mac_control == slave->mac_control) - return; + goto out; if (mac_control) { printf("link up on port %d, speed %d, %s duplex\n", @@ -649,17 +653,20 @@ static void cpsw_slave_update_link(struct cpsw_slave *slave, __raw_writel(mac_control, &slave->sliver->mac_control); slave->mac_control = mac_control; + +out: + return ret; } static int cpsw_update_link(struct cpsw_priv *priv) { - int link = 0; + int ret = -ENODEV; struct cpsw_slave *slave; for_active_slave(slave, priv) - cpsw_slave_update_link(slave, priv, &link); + ret = cpsw_slave_update_link(slave, priv, NULL); - return link; + return ret; } static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) @@ -822,7 +829,9 @@ static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr) for_active_slave(slave, priv) cpsw_slave_init(slave, priv); - cpsw_update_link(priv); + ret = cpsw_update_link(priv); + if (ret) + goto out; /* init descriptor pool */ for (i = 0; i < NUM_DESCS; i++) { @@ -897,7 +906,8 @@ static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr) } } - return 0; +out: + return ret; } static void _cpsw_halt(struct cpsw_priv *priv) -- 2.9.0

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