April 2017 - U-Boot

[U-Boot] [PATCH v1] cpu: Add Intel Tangier support
by Andy Shevchenko 05 Jul '17

05 Jul '17

From: Felipe Balbi <felipe.balbi(a)linux.intel.com> Add Intel Tangier SoC support. Intel Tangier SoC is a core part of Intel Merrifield platform. For example, Intel Edison board is based on such platform. The patch is based on work done by the following people (in alphabetical order): Aiden Park <aiden.park(a)intel.com> Dukjoon Jeon <dukjoon.jeon(a)intel.com> eric.park <eric.park(a)intel.com> Fabien Chereau <fabien.chereau(a)intel.com> Scott D Phillips <scott.d.phillips(a)intel.com> Sebastien Colleur <sebastienx.colleur(a)intel.com> Steve Sakoman <steve.sakoman(a)intel.com> Vincent Tinelli <vincent.tinelli(a)intel.com> Signed-off-by: Vincent Tinelli <vincent.tinelli(a)intel.com> Signed-off-by: Felipe Balbi <felipe.balbi(a)linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- arch/x86/Kconfig | 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/tangier/Kconfig | 20 ++++ arch/x86/cpu/tangier/Makefile | 1 + arch/x86/cpu/tangier/car.S | 13 +++ arch/x86/cpu/tangier/sdram.c | 234 +++++++++++++++++++++++++++++++++++++ arch/x86/cpu/tangier/tangier.c | 36 ++++++ arch/x86/include/asm/dma-mapping.h | 41 +++++++ 8 files changed, 347 insertions(+) create mode 100644 arch/x86/cpu/tangier/Kconfig create mode 100644 arch/x86/cpu/tangier/Makefile create mode 100644 arch/x86/cpu/tangier/car.S create mode 100644 arch/x86/cpu/tangier/sdram.c create mode 100644 arch/x86/cpu/tangier/tangier.c create mode 100644 arch/x86/include/asm/dma-mapping.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9ead3ebccf..31f2d154d4 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -114,6 +114,7 @@ source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/qemu/Kconfig" source "arch/x86/cpu/quark/Kconfig" source "arch/x86/cpu/queensbay/Kconfig" +source "arch/x86/cpu/tangier/Kconfig" # architecture-specific options below diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 92a9023b0b..6f3535d216 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_QEMU) += qemu/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ +obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-y += lapic.o ioapic.o obj-y += irq.o ifndef CONFIG_$(SPL_)X86_64 diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig new file mode 100644 index 0000000000..3545886a65 --- /dev/null +++ b/arch/x86/cpu/tangier/Kconfig @@ -0,0 +1,20 @@ +# +# Copyright (C) 2015 Intel, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_TANGIER + bool + depends on INTEL_MID + +config SYS_CAR_ADDR + hex + default 0x19200000 + +config SYS_CAR_SIZE + hex + default 0x4000 + help + Space in bytes in eSRAM used as Cache-As-RAM (CAR). + Note this size must not exceed eSRAM's total size. diff --git a/arch/x86/cpu/tangier/Makefile b/arch/x86/cpu/tangier/Makefile new file mode 100644 index 0000000000..d937737057 --- /dev/null +++ b/arch/x86/cpu/tangier/Makefile @@ -0,0 +1 @@ +obj-y += car.o tangier.o sdram.o diff --git a/arch/x86/cpu/tangier/car.S b/arch/x86/cpu/tangier/car.S new file mode 100644 index 0000000000..6982106c19 --- /dev/null +++ b/arch/x86/cpu/tangier/car.S @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010-2011 + * Graeme Russ, <graeme.russ(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.section .text + +.globl car_init +car_init: + jmp car_init_ret diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c new file mode 100644 index 0000000000..da046559a1 --- /dev/null +++ b/arch/x86/cpu/tangier/sdram.c @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 + * Graeme Russ, <graeme.russ(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/bootparam.h> +#include <asm/e820.h> +#include <asm/global_data.h> +#include <asm/processor.h> +#include <asm/sections.h> +#include <asm/sfi.h> +#include <asm/u-boot-x86.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Memory type definitions */ +enum sfi_mem_type { + SFI_MEM_RESERVED, + SFI_LOADER_CODE, + SFI_LOADER_DATA, + SFI_BOOT_SERVICE_CODE, + SFI_BOOT_SERVICE_DATA, + SFI_RUNTIME_SERVICE_CODE, + SFI_RUNTIME_SERVICE_DATA, + SFI_MEM_CONV, + SFI_MEM_UNUSABLE, + SFI_ACPI_RECLAIM, + SFI_ACPI_NVS, + SFI_MEM_MMIO, + SFI_MEM_IOPORT, + SFI_PAL_CODE, + SFI_MEM_TYPEMAX, +}; + +#define SFI_BASE_ADDR 0x000E0000 +#define SFI_LENGTH 0x00020000 +#define SFI_TABLE_LENGTH 16 + +static int sfi_table_check(struct sfi_table_header *sbh) +{ + char chksum = 0; + char *pos = (char *)sbh; + int i; + + if (sbh->len < SFI_TABLE_LENGTH) + return -1; + + if (sbh->len > SFI_LENGTH) + return -1; + + for (i = 0; i < sbh->len; i++) + chksum += *pos++; + + if (chksum) + error("sfi: Invalid checksum\n"); + + /* Checksum is OK if zero */ + return chksum; +} + +static int sfi_table_is_type(struct sfi_table_header *sbh, const char *signature) +{ + return !strncmp(sbh->sig, signature, SFI_SIGNATURE_SIZE) && + !sfi_table_check(sbh); +} + +static struct sfi_table_simple *sfi_get_table_by_sig(unsigned long addr, + const char *signature) +{ + struct sfi_table_simple *sb = NULL; + int i; + + for (i = 0; i < SFI_LENGTH; i += SFI_TABLE_LENGTH) { + sb = (struct sfi_table_simple *)(addr + i); + if (sfi_table_is_type(&sb->header, signature)) + break; + } + + if (i >= SFI_LENGTH || !sb) + return NULL; + + return sb; +} + +static struct sfi_table_simple *sfi_search_mmap(void) +{ + struct sfi_table_header *sbh; + struct sfi_table_simple *sb; + u32 sys_entry_cnt; + u32 i; + + /* Find SYST table */ + sb = sfi_get_table_by_sig(SFI_BASE_ADDR, SFI_SIG_SYST); + if (!sb) { + error("failed to locate SYST table\n"); + return NULL; + } + + sys_entry_cnt = (sb->header.len - sizeof(*sbh)) / 8; + + /* Search through each SYST entry for MMAP table */ + for (i = 0; i < sys_entry_cnt; i++) { + sbh = (struct sfi_table_header *)(unsigned long)sb->pentry[i]; + + if (sfi_table_is_type(sbh, SFI_SIG_MMAP)) + return (struct sfi_table_simple *) sbh; + } + + error("failed to locate SFI MMAP table\n"); + return NULL; +} + +#define sfi_for_each_mentry(i, sb, mentry) \ + for (i = 0, mentry = (struct sfi_mem_entry *)sb->pentry; \ + i < SFI_GET_NUM_ENTRIES(sb, struct sfi_mem_entry); \ + i++, mentry++) \ + +static unsigned sfi_setup_e820(unsigned max_entries, struct e820entry *entries) +{ + struct sfi_table_simple *sb; + struct sfi_mem_entry *mentry; + unsigned long long start, end, size; + int type, total = 0; + int i; + + sb = sfi_search_mmap(); + if (!sb) + return 0; + + sfi_for_each_mentry(i, sb, mentry) { + start = mentry->phys_start; + size = mentry->pages << 12; + end = start + size; + + if (start > end) + continue; + + /* translate SFI mmap type to E820 map type */ + switch (mentry->type) { + case SFI_MEM_CONV: + type = E820_RAM; + break; + case SFI_MEM_UNUSABLE: + case SFI_RUNTIME_SERVICE_DATA: + continue; + default: + type = E820_RESERVED; + } + + if (total == E820MAX) + break; + entries[total].addr = start; + entries[total].size = size; + entries[total].type = type; + + total++; + } + + return total; +} + +static int sfi_get_bank_size(void) +{ + struct sfi_table_simple *sb; + struct sfi_mem_entry *mentry; + int bank = 0; + int i; + + sb = sfi_search_mmap(); + if (!sb) + return -ENXIO; + + sfi_for_each_mentry(i, sb, mentry) { + if (mentry->type != SFI_MEM_CONV) + continue; + + gd->bd->bi_dram[bank].start = mentry->phys_start; + gd->bd->bi_dram[bank].size = mentry->pages << 12; + bank++; + } + + return bank; +} + +static phys_size_t sfi_get_ram_size(void) +{ + struct sfi_table_simple *sb; + struct sfi_mem_entry *mentry; + phys_size_t ram = 0; + int i; + + sb = sfi_search_mmap(); + if (!sb) + return 0; + + sfi_for_each_mentry(i, sb, mentry) { + if (mentry->type != SFI_MEM_CONV) + continue; + + ram += (mentry->pages << 12); + } + + debug("RAM size %llu\n", ram); + + return ram; +} + +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +{ + return sfi_setup_e820(max_entries, entries); +} + +int dram_init_banksize(void) +{ + int ret; + + ret = sfi_get_bank_size(); + if (ret < 0) + return ret; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = sfi_get_ram_size(); + + return 0; +} diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c new file mode 100644 index 0000000000..c06767b915 --- /dev/null +++ b/arch/x86/cpu/tangier/tangier.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ(a)gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/scu.h> +#include <asm/u-boot-x86.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ +int arch_cpu_init(void) +{ + return x86_cpu_init_f(); +} + +int checkcpu(void) +{ + return 0; +} + +int print_cpuinfo(void) +{ + return default_print_cpuinfo(); +} + +void reset_cpu(ulong addr) +{ + scu_ipc_simple_command(IPCMSG_COLD_RESET, 0); +} diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h new file mode 100644 index 0000000000..7de4c08e36 --- /dev/null +++ b/arch/x86/include/asm/dma-mapping.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2007 + * Stelian Pop <stelian(a)popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_X86_DMA_MAPPING_H +#define __ASM_X86_DMA_MAPPING_H + +#define dma_mapping_error(x, y) 0 + +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, +}; + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); + return (void *)*handle; +} + +static inline void dma_free_coherent(void *addr) +{ + free(addr); +} + +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, + enum dma_data_direction dir) +{ + return (unsigned long)vaddr; +} + +static inline void dma_unmap_single(volatile void *vaddr, size_t len, + unsigned long paddr) +{ +} + +#endif /* __ASM_X86_DMA_MAPPING_H */ -- 2.11.0

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[U-Boot] [PATCH v1] watchdog: Introduce watchdog driver for Intel Tangier
by Andy Shevchenko 05 Jul '17

05 Jul '17

From: Felipe Balbi <felipe.balbi(a)linux.intel.com> Add watchdog driver for Intel Tangier based platforms. Signed-off-by: Vincent Tinelli <vincent.tinelli(a)intel.com> Signed-off-by: Felipe Balbi <felipe.balbi(a)linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- common/board_f.c | 1 + drivers/watchdog/Kconfig | 8 ++++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/tangier_wdt.c | 63 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 drivers/watchdog/tangier_wdt.c diff --git a/common/board_f.c b/common/board_f.c index d9431ee79a..ad1eae98a5 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -91,6 +91,7 @@ static int init_func_watchdog_init(void) (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ defined(CONFIG_DESIGNWARE_WATCHDOG) || \ + defined(CONFIG_TANGIER_WATCHDOG) || \ defined(CONFIG_IMX_WATCHDOG)) hw_watchdog_init(); puts(" Watchdog enabled\n"); diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index dbdaafc149..66fe70dba1 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1,5 +1,13 @@ menu "WATCHDOG support" +config TANGIER_WATCHDOG + bool "Intel Tangier watchdog" + depends on INTEL_MID + help + This enables support for watchdog controller available on + Intel Tangier SoC. If you're using a board with Intel Tangier + SoC, say Y here. + config ULP_WATCHDOG bool "i.MX7ULP watchdog" help diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index dea18363ca..7b77d8379f 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -15,4 +15,5 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o +obj-$(CONFIG_TANGIER_WATCHDOG) += tangier_wdt.o obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o diff --git a/drivers/watchdog/tangier_wdt.c b/drivers/watchdog/tangier_wdt.c new file mode 100644 index 0000000000..23be71a42f --- /dev/null +++ b/drivers/watchdog/tangier_wdt.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <watchdog.h> +#include <asm/scu.h> + +/* Hardware timeout in seconds */ +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS +#define WATCHDOG_HEARTBEAT 60000 +#else +#define WATCHDOG_HEARTBEAT CONFIG_WATCHDOG_TIMEOUT_MSECS +#endif + +enum { + SCU_WATCHDOG_START = 0, + SCU_WATCHDOG_STOP = 1, + SCU_WATCHDOG_KEEPALIVE = 2, + SCU_WATCHDOG_SET_ACTION_ON_TIMEOUT = 3, +}; + +void hw_watchdog_reset(void) +{ + static unsigned long prev; + unsigned long now; + + if (gd->timer) + now = timer_get_us(); + else + now = rdtsc() / 1000000; + + /* Do not flood SCU */ + if (unlikely((now - prev) > (WATCHDOG_HEARTBEAT * 1000))) { + prev = now; + scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_KEEPALIVE); + } +} + +int hw_watchdog_disable(void) +{ + return scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_STOP); +} + +void hw_watchdog_init(void) +{ + u32 timeout = WATCHDOG_HEARTBEAT / 1000; + int in_size; + struct ipc_wd_start { + u32 pretimeout; + u32 timeout; + } ipc_wd_start = { timeout, timeout }; + + /* + * SCU expects the input size for watchdog IPC + * to be based on 4 bytes + */ + in_size = DIV_ROUND_UP(sizeof(ipc_wd_start), 4); + + scu_ipc_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_START, + (u32 *)&ipc_wd_start, in_size, NULL, 0); +} -- 2.11.0

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[U-Boot] [PATCH 1/2] efi_loader: run CreateEvent() notify function based on flags
by Jonathan Gray 03 Jul '17

03 Jul '17

The UEFI specification states that the tpl, function and context arguments are to be ignored if neither EVT_NOTIFY_WAIT or EVT_NOTIFY_SIGNAL are specified. This matches observed behaviour with an AMI EDK2 based UEFI implementation. Skip calling the notify function if neither flag is present. Signed-off-by: Jonathan Gray <jsg(a)jsg.id.au> --- include/efi_api.h | 3 +++ lib/efi_loader/efi_boottime.c | 4 +++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/efi_api.h b/include/efi_api.h index 5c3836a51b..f071b36b53 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -28,6 +28,9 @@ enum efi_event_type { EFI_TIMER_RELATIVE = 2 }; +#define EVT_NOTIFY_WAIT 0x00000100 +#define EVT_NOTIFY_SIGNAL 0x00000200 + /* EFI Boot Services table */ struct efi_boot_services { struct efi_table_hdr hdr; diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 51080cbeed..eb5946a959 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -210,7 +210,9 @@ void efi_timer_check(void) /* Triggering! */ if (efi_event.trigger_type == EFI_TIMER_PERIODIC) efi_event.trigger_next += efi_event.trigger_time / 10; - efi_event.notify_function(&efi_event, efi_event.notify_context); + if (efi_event.type & (EVT_NOTIFY_WAIT | EVT_NOTIFY_SIGNAL)) + efi_event.notify_function(&efi_event, + efi_event.notify_context); } WATCHDOG_RESET(); -- 2.12.0

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[U-Boot] [PATCH] am335x_evm_usbspl_defconfig: Fix USB RNDIS boot
by Vignesh R 27 Jun '17

27 Jun '17

It seems few config options are missing in the current am335x_evm_usbspl_defconfig causing USB RNDIS boot to fail on AM335x EVM. Fix this by adding required configs. Signed-off-by: Vignesh R <vigneshr(a)ti.com> --- configs/am335x_evm_usbspl_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig index a79470e88685..0a32d41eae67 100644 --- a/configs/am335x_evm_usbspl_defconfig +++ b/configs/am335x_evm_usbspl_defconfig @@ -44,3 +44,7 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 CONFIG_OF_LIBFDT=y +CONFIG_SPL_ETH_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USBETH_SUPPORT=y +CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" -- 2.11.0

2 5

[U-Boot] [PATCH 0/2] x86: Convert all boards to use MMC to driver model
by Simon Glass 27 Jun '17

27 Jun '17

This serial converts x86 boards to use MMC for driver model. It has to disable SCSI to make this work, for now. Once SCSI is sorted out, we can apply the patch. Simon Glass (2): WIP: Disable SCSI on x86 x86: Convert MMC to driver model arch/Kconfig | 1 + arch/x86/cpu/baytrail/valleyview.c | 12 ------ arch/x86/cpu/quark/quark.c | 10 ----- arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/topcliff.c | 20 --------- drivers/mmc/pci_mmc.c | 86 ++++++++++++++++++++++++++------------ include/configs/x86-common.h | 6 ++- include/mmc.h | 12 ------ 8 files changed, 66 insertions(+), 83 deletions(-) delete mode 100644 arch/x86/cpu/queensbay/topcliff.c -- 2.12.2.715.g7642488e1d-goog

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[U-Boot] [ANN] U-Boot v2017.05-rc2 released
by Tom Rini 26 Jun '17

26 Jun '17

Hey all, It's release day and v2017.05-rc2 is out. I think my patchwork queue is looking good currently. I have some outstanding removal patches to take from Masahiro related to architectures that I removed as promised. The release is bigger than I really wanted, but since I was on vacation for most of the normal -rc1 window, stuff came in that would have come in then now, instead. Things are on track for -rc3 on the 1st. Thanks all! -- Tom

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[U-Boot] [PATCH] libfdt: fix build with Python 3
by Stefan Agner 25 Jun '17

25 Jun '17

From: Stefan Agner <stefan.agner(a)toradex.com> For some reason Python 3 seems to think it does not need to build the library. Using the --force parameter makes sure that the library gets built always. This is especially important since we move the library in the next step of the Makefile, hence forcing a rebuild every time the higher level Makefile triggers a rebuild is required to make sure the library is always there. Signed-off-by: Stefan Agner <stefan.agner(a)toradex.com> --- lib/libfdt/setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/libfdt/setup.py b/lib/libfdt/setup.py index 62e7bcc1ac..845a0c2b10 100644 --- a/lib/libfdt/setup.py +++ b/lib/libfdt/setup.py @@ -27,7 +27,7 @@ libfdt_module = Extension( extra_compile_args = cflags ) -sys.argv = [progname, '--quiet', 'build_ext', '--inplace'] +sys.argv = [progname, '--quiet', 'build_ext', '--inplace', '--force'] setup (name = 'libfdt', version = '0.1', -- 2.12.1

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[U-Boot] [PATCH] SECURE_BOOT: Unify memory map for Layerscape based platforms
by Sumit Garg 19 Jun '17

19 Jun '17

Unify memory map for Layerscape based platforms as per DASH SDK memory map. This patch includes changes in bootscript, bootscript header and PPA header addresses change as per unified memory map. Signed-off-by: Sumit Garg <sumit.garg(a)nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 +++---- arch/arm/include/asm/fsl_secure_boot.h | 54 +++++++++++++------------------ 2 files changed, 28 insertions(+), 38 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 8270431..c849c05 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -206,12 +206,12 @@ config SYS_LS_PPA_FW_ADDR config SYS_LS_PPA_ESBC_ADDR hex "hdr address of PPA firmware loading from" depends on FSL_LS_PPA && CHAIN_OF_TRUST - default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A - default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A - default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A - default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 - default 0x700000 if SYS_LS_PPA_FW_IN_MMC - default 0x700000 if SYS_LS_PPA_FW_IN_NAND + default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A + default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A + default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A + default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 + default 0x680000 if SYS_LS_PPA_FW_IN_MMC + default 0x680000 if SYS_LS_PPA_FW_IN_NAND help If the PPA header firmware locate at XIP flash, such as NOR or QSPI flash, this address is a directly memory-mapped. diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 7bff8b7..42ae4e2 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -1,5 +1,6 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -77,55 +78,44 @@ * DDR memory map */ #ifdef CONFIG_FSL_LSCH3 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000 -#define CONFIG_BS_ADDR_DEVICE 0x580e00000 -#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000 -#define CONFIG_BS_ADDR_RAM 0xa0e00000 -#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BS_ADDR_DEVICE 0x580600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000 #define CONFIG_BS_SIZE 0x00001000 +#define CONFIG_BS_HDR_SIZE 0x00004000 +#define CONFIG_BS_ADDR_RAM 0xa0600000 +#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000 #else #ifdef CONFIG_SD_BOOT /* For SD boot address and size are assigned in terms of sector * offset and no. of sectors respectively. */ -#if defined(CONFIG_LS1043A) || defined(CONFIG_ARCH_LS1046A) -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920 -#else -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900 -#endif -#define CONFIG_BS_ADDR_DEVICE 0x00000940 -#define CONFIG_BS_HDR_SIZE 0x00000010 +#define CONFIG_BS_ADDR_DEVICE 0x00003000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200 #define CONFIG_BS_SIZE 0x00000008 +#define CONFIG_BS_HDR_SIZE 0x00000010 #elif defined(CONFIG_NAND_BOOT) -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 -#define CONFIG_BS_ADDR_DEVICE 0x00802000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#define CONFIG_BS_SIZE 0x00001000 -#elif defined(CONFIG_QSPI_BOOT) -#ifdef CONFIG_ARCH_LS1046A -#define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000 -#define CONFIG_BS_ADDR_DEVICE 0x40800000 -#elif defined(CONFIG_ARCH_LS1012A) -#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000 -#define CONFIG_BS_ADDR_DEVICE 0x40060000 -#else -#error "Platform not supported" -#endif +#define CONFIG_BS_ADDR_DEVICE 0x00600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000 +#define CONFIG_BS_SIZE 0x00001000 #define CONFIG_BS_HDR_SIZE 0x00002000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_BS_ADDR_DEVICE 0x40600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000 #define CONFIG_BS_SIZE 0x00001000 -#else /* Default NOR Boot */ -#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 -#define CONFIG_BS_ADDR_DEVICE 0x60060000 #define CONFIG_BS_HDR_SIZE 0x00002000 +#else /* Default NOR Boot */ +#define CONFIG_BS_ADDR_DEVICE 0x60600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000 #define CONFIG_BS_SIZE 0x00001000 +#define CONFIG_BS_HDR_SIZE 0x00002000 #endif -#define CONFIG_BS_HDR_ADDR_RAM 0x81000000 -#define CONFIG_BS_ADDR_RAM 0x81020000 +#define CONFIG_BS_ADDR_RAM 0x81000000 +#define CONFIG_BS_HDR_ADDR_RAM 0x81020000 #endif #ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM #else #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE /* BOOTSCRIPT_ADDR is not required */ -- 1.9.1

2 5

[U-Boot] [RESEND PATCH] include: nand: move endif to end of file
by Grygorii Strashko 16 Jun '17

16 Jun '17

From: Mugunthan V N <mugunthanvnm(a)ti.com> The terminator endif of ifdef _NAND_H_ should be at the end of file as a fail safe. Signed-off-by: Mugunthan V N <mugunthanvnm(a)ti.com> Reviewed-by: Tom Rini <trini(a)konsulko.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Grygorii Strashko <grygorii.strashko(a)ti.com> --- Link on prev version [1] https://patchwork.ozlabs.org/patch/604738/ I've kept "Reviewed-by" from [1], pls inform me in case of any issues. include/nand.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/nand.h b/include/nand.h index b6eb223..692c4db 100644 --- a/include/nand.h +++ b/include/nand.h @@ -131,8 +131,6 @@ void board_nand_select_device(struct nand_chip *nand, int chip); __attribute__((noreturn)) void nand_boot(void); -#endif - #ifdef CONFIG_ENV_OFFSET_OOB #define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored as block number*/ @@ -145,3 +143,5 @@ int spl_nand_erase_one(int block, int page); /* platform specific init functions */ void sunxi_nand_init(void); + +#endif /* _NAND_H_ */ -- 2.10.1.dirty

2 1

[U-Boot] [PATCH v2 7/8] mvebu: Support Synology DS414
by Phil Sutter 16 Jun '17

16 Jun '17

This adds support for the MV78230 based DS414 NAS by Synology. The relevant bits have been extracted from the 'synogpl-5004-armadaxp' package Synology kindly published, garnished with a fair amount of trial-and-error. Sadly, support is far from perfect. The major parts I have failed in are SATA and XHCI support. Details about these and some other things follow: Device Tree ----------- The device tree file armada-xp-synology-ds414.dts has been copied from Linux and enhanced by recent U-Boot specific changes to armada-xp-gp.dts. SATA Support ------------ There is a Marvell 88SX7042 controller attached to PCIe which is supported by Linux's sata_mv driver but sadly not U-Boot's sata_mv. I'm not sure if extending the latter to support PCI devices is worth the effort at all. Porting sata_mv from Linux exceeded my brain's capacities. :( XHCI Support ------------ There is an EtronTech EJ168A XHCI controller attached to PCIe which drives the two rear USB3 ports. After a bit of playing around I managed to get it recognized by xhci-pci, but never was able to access any devices attached to it. Enabling it in ds414 board config shows that it does not respond to commands for whatever reason. The (somewhat) bright side to it is that it is not even supported in Synology's customized U-Boot, but that also means nowhere to steal the relevant bits from. EHCI Support ------------ This seems functional after issuing 'usb start'. At least it detects USB storage devices, and IIRC reading from them was OK. OTOH Linux fails to register the controller if 'usb start' wasn't given before in U-Boot. According to Synology sources, this board seems to support USB device (gadget?) mode. Though I didn't play around with it. PCIe Support ------------ This is fine, but trying to gate the clocks of unused lanes will hang PCI enum. In addition to that, pci_mvebu seems not to support DM_PCI. DDR3 Training ------------- Marvell/Synology uses eight PUPs instead of four. Does not look like this is meant to be customized in mainline U-Boot at all. OTOH I have no idea what a "PUP" actually is. PEX Init -------- Synology uses different values than mainline U-Boot with this patch: pex_max_unit_get returns 2, pex_max_if_get returns 7 and max_serdes_lines is set to 7. Not changing this seems to not have an impact, although I'm not entirely sure it does not cause issues I am not aware of. Static Environment ------------------ This allows to boot stock Synology firmware at least. In order to be a little more flexible when it comes to booting custom kernels, do not only load zImage partition, but also rd.gz into memory. This way it is possible to use about 7MB for kernel with piggyback initramfs. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/armada-xp-synology-ds414.dts | 337 +++++++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 3 + arch/arm/mach-mvebu/serdes/axp/board_env_spec.h | 5 +- .../arm/mach-mvebu/serdes/axp/high_speed_env_lib.c | 3 + board/Synology/ds414/Kconfig | 12 + board/Synology/ds414/Makefile | 1 + board/Synology/ds414/ds414.c | 173 +++++++++++ board/Synology/ds414/kwbimage.cfg | 12 + configs/ds414_defconfig | 18 ++ include/configs/ds414.h | 164 ++++++++++ 12 files changed, 729 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/armada-xp-synology-ds414.dts create mode 100644 board/Synology/ds414/Kconfig create mode 100644 board/Synology/ds414/Makefile create mode 100644 board/Synology/ds414/ds414.c create mode 100644 board/Synology/ds414/kwbimage.cfg create mode 100644 configs/ds414_defconfig create mode 100644 include/configs/ds414.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 867303a..96c3a7c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -813,6 +813,7 @@ source "board/hisilicon/hikey/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" source "board/maxbcm/Kconfig" +source "board/Synology/ds414/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" source "board/phytec/pcm051/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6e2a95f..26fd2f8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -53,6 +53,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb +dtb-$(CONFIG_TARGET_DS414) += armada-xp-synology-ds414.dtb + dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-ld4-ref.dtb \ uniphier-ph1-ld6b-ref.dtb \ diff --git a/arch/arm/dts/armada-xp-synology-ds414.dts b/arch/arm/dts/armada-xp-synology-ds414.dts new file mode 100644 index 0000000..0a60ddf --- /dev/null +++ b/arch/arm/dts/armada-xp-synology-ds414.dts @@ -0,0 +1,337 @@ +/* + * Device Tree file for Synology DS414 + * + * Copyright (C) 2014, Arnaud EBALARD <arno(a)natisbad.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the old 0xd0000000). + * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot + * bootloaders provided by Marvell. It is used in recent versions of + * DSM software provided by Synology. Nonetheless, some earlier boards + * were delivered with an older version of u-boot that left internal + * registers mapped at 0xd0000000. If you have such a device you will + * not be able to directly boot a kernel based on this Device Tree. In + * that case, the preferred solution is to update your bootloader (e.g. + * by upgrading to latest version of DSM, or building a new one and + * installing it from u-boot prompt) or adjust the Devive Tree + * (s/0xf1000000/0xd0000000/ in 'ranges' below). + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Synology DS414"; + compatible = "synology,ds414", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; /* 1GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; + + pcie-controller { + status = "okay"; + + /* + * Connected to Marvell 88SX7042 SATA-II controller + * handling the four disks. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * Connected to EtronTech EJ168A XHCI controller + * providing the two rear USB 3.0 ports. + */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + + /* RTC is provided by Seiko S-35390A below */ + rtc@10300 { + status = "disabled"; + }; + + spi0: spi@10600 { + status = "okay"; + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@00000000 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000d0000>; /* 832KB */ + }; + + partition@000c0000 { /* uImage */ + label = "zImage"; + reg = <0x000d0000 0x002d0000>; /* 2880KB */ + }; + + partition@003a0000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x003a0000 0x00430000>; /* 4250KB */ + }; + + partition@007d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@007e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@007f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; + }; + + i2c@11000 { + clock-frequency = <400000>; + status = "okay"; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + /* Connected to a header on device's PCB. This + * provides the main console for the device. + * + * Warning: the device may not boot with a 3.3V + * USB-serial converter connected when the power + * button is pressed. The converter needs to be + * connected a few seconds after pressing the + * power button. This is possibly due to UART0_TXD + * pin being sampled at reset (bit 0 of SAR). + */ + serial@12000 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + + /* Connected to a Microchip PIC16F883 for power control */ + serial@12100 { + status = "okay"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&coreclk 0>; + }; + + /* Front USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1512 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; + }; + + ethernet@70000 { + status = "okay"; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin + &sata3_pwr_pin &sata4_pwr_pin>; + pinctrl-names = "default"; + + sata1_regulator: sata1-regulator { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + sata2_regulator: sata2-regulator { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA2 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + sata3_regulator: sata3-regulator { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "SATA3 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <6000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + + sata4_regulator: sata4-regulator { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "SATA4 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <8000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + sata1_pwr_pin: sata1-pwr-pin { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + sata2_pwr_pin: sata2-pwr-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata3_pwr_pin: sata3-pwr-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + sata4_pwr_pin: sata4-pwr-pin { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + syno_id_bit0_pin: syno-id-bit0-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + syno_id_bit1_pin: syno-id-bit1-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + syno_id_bit2_pin: syno-id-bit2-pin { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + fan1_alarm_pin: fan1-alarm-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + fan2_alarm_pin: fan2-alarm-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 82a439e..50fc8ee 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -16,6 +16,9 @@ config TARGET_DB_MV784MP_GP config TARGET_MAXBCM bool "Support maxbcm" +config TARGET_DS414 + bool "Support Synology DS414" + endchoice config SYS_SOC diff --git a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h index f00f327..3dca6a1 100644 --- a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h +++ b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h @@ -43,8 +43,9 @@ #define RD_78460_SERVER_REV2_ID (DB_78X60_PCAC_REV2_ID + 1) #define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1) #define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1) -#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1) -#define INVALID_BAORD_ID 0xFFFFFFFF +#define SYNOLOGY_DS414_ID (RD_78460_CUSTOMER_ID + 1) +#define MV_MAX_BOARD_ID (SYNOLOGY_DS414_ID + 1) +#define INVALID_BOARD_ID 0xFFFFFFFF /* Sample at Reset */ #define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4)) diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index 0e2a905..a789a60 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -66,6 +66,8 @@ static u32 board_id_get(void) return DB_784MP_GP_ID; #elif defined(CONFIG_RD_78460_CUSTOMER) return RD_78460_CUSTOMER_ID; +#elif defined(CONFIG_SYNOLOGY_DS414) + return SYNOLOGY_DS414_ID; #else /* * Return 0 here for custom board as this should not be used @@ -262,6 +264,7 @@ int serdes_phy_config(void) case RD_78460_SERVER_ID: case RD_78460_SERVER_REV2_ID: case DB_78X60_PCAC_ID: + case SYNOLOGY_DS414_ID: satr11 = (0x1 << 1) | 1; break; case FPGA_88F78XX0_ID: diff --git a/board/Synology/ds414/Kconfig b/board/Synology/ds414/Kconfig new file mode 100644 index 0000000..4d30852 --- /dev/null +++ b/board/Synology/ds414/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DS414 + +config SYS_BOARD + default "ds414" + +config SYS_VENDOR + default "Synology" + +config SYS_CONFIG_NAME + default "ds414" + +endif diff --git a/board/Synology/ds414/Makefile b/board/Synology/ds414/Makefile new file mode 100644 index 0000000..aad8c43 --- /dev/null +++ b/board/Synology/ds414/Makefile @@ -0,0 +1 @@ +obj-y := ds414.o diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c new file mode 100644 index 0000000..88252f6 --- /dev/null +++ b/board/Synology/ds414/ds414.c @@ -0,0 +1,173 @@ +#include <common.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <linux/mbus.h> + +#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" +#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" +#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */ + +#define DS414_GPP_OUT_VAL_LOW (BIT(25) | BIT(30)) +#define DS414_GPP_OUT_VAL_MID (BIT(10) | BIT(15)) +#define DS414_GPP_OUT_VAL_HIGH (0) + +#define DS414_GPP_OUT_POL_LOW (0) +#define DS414_GPP_OUT_POL_MID (0) +#define DS414_GPP_OUT_POL_HIGH (0) + +#define DS414_GPP_OUT_ENA_LOW (~(BIT(25) | BIT(30))) +#define DS414_GPP_OUT_ENA_MID (~(BIT(10) | BIT(12) | \ + BIT(13) | BIT(14) | BIT(15))) +#define DS414_GPP_OUT_ENA_HIGH (~0) + +static const u32 ds414_mpp_control[] = { + 0x11111111, + 0x22221111, + 0x22222222, + 0x00000000, + 0x11110000, + 0x00004000, + 0x00000000, + 0x00000000, + 0x00000000 +}; + +/* DDR3 static MC configuration */ + +/* 1G_v1 (4x2Gbits) adapted by DS414 */ +MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = { + {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ + {0x00001404, 0x30000800}, /*Dunit Control Low Register */ + {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */ + /* {0x0000140C, 0x38000C6}, */ /*DDR SDRAM Timing (High) Register */ + {0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */ + + {0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */ + + {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */ + {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */ + {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */ + {0x00001424, 0x0000F3FF}, /*Dunit Control High Register */ + {0x00001428, 0x000F8830}, /*Dunit Control High Register */ + {0x0000142C, 0x054C36F4}, /*Dunit Control High Register */ + {0x0000147C, 0x0000C671}, + + {0x000014a0, 0x00000001}, + {0x000014a8, 0x00000100}, /*2:1 */ + {0x00020220, 0x00000006}, + + {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */ + {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */ + {0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */ + + {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */ + {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */ + + {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/ + {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */ + + {0x0001504, 0x3FFFFFE1}, /* CS0 Size */ + {0x000150C, 0x00000000}, /* CS1 Size */ + {0x0001514, 0x00000000}, /* CS2 Size */ + {0x000151C, 0x00000000}, /* CS3 Size */ + + /* {0x00001524, 0x0000C800}, */ + {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */ + {0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */ + + {0x000015D0, 0x00000650}, /*MR0 */ + {0x000015D4, 0x00000044}, /*MR1 */ + {0x000015D8, 0x00000010}, /*MR2 */ + {0x000015DC, 0x00000000}, /*MR3 */ + + {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */ + {0x000015EC, 0xF800A225}, /*DDR PHY */ + + {0x0, 0x0} +}; + +MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = { + {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL}, +}; + +extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; + +MV_BIN_SERDES_CFG ds414_serdes_cfg[] = { + { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000, + { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, + PEX_BUS_DISABLED }, + 0x0040, serdes_change_m_phy + } +}; + +MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) +{ + return &ds414_ddr_modes[0]; +} + +MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +{ + return &ds414_serdes_cfg[0]; +} + +int board_early_init_f(void) +{ + int i; + + /* Set GPP Out value */ + reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW); + reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID); + reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH); + + /* set GPP polarity */ + reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW); + reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID); + reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH); + + /* Set GPP Out Enable */ + reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW); + reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID); + reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH); + + for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++) + reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]); + + return 0; +} + +int board_init(void) +{ + u32 pwr_mng_ctrl_reg; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* gate unused clocks */ + /* Note: disabling unused PCIe lanes will hang PCI bus scan */ + pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); + pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */ + pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */ + //pwr_mng_ctrl_reg &= ~(BIT(10) | BIT(11) | BIT(12)); /* PCIe11 - PCIe13 */ + pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */ + pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */ + pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */ + pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */ + //pwr_mng_ctrl_reg &= ~(BIT(26) | BIT(27)); /* PCIe20 and PCIe30 */ + pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */ + reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); + + return 0; +} + +int checkboard(void) +{ + puts("Board: DS414\n"); + + return 0; +} diff --git a/board/Synology/ds414/kwbimage.cfg b/board/Synology/ds414/kwbimage.cfg new file mode 100644 index 0000000..1f748db --- /dev/null +++ b/board/Synology/ds414/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr(a)denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig new file mode 100644 index 0000000..4c3c1df --- /dev/null +++ b/configs/ds414_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_DS414=y +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414" +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y diff --git a/include/configs/ds414.h b/include/configs/ds414.h new file mode 100644 index 0000000..8148571 --- /dev/null +++ b/include/configs/ds414.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_SYNOLOGY_DS414_H +#define _CONFIG_SYNOLOGY_DS414_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_MV78230 /* SoC Version */ +#define CONFIG_SYNOLOGY_DS414 /* board target name for DDR training and PCIe init */ +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TEXT_BASE 0x00800000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TFTPPUT +#define CONFIG_CMD_TIME +#define CONFIG_CMD_USB + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define CONFIG_PHY_ADDR { 0x1, 0x0 } +#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII + +#define CONFIG_SYS_ALT_MEMTEST + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM +#define CONFIG_PCI_MVEBU +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* USB/EHCI/XHCI configuration */ + +/* FIXME: broken XHCI support + * Below defines should enable support for the two rear USB3 ports. Sadly, this + * does not work because: + * - xhci-pci seems not to support DM_USB, so with that enabled it is not + * found. To workaround, comment out CONFIG_DM_USB define. + * - USB init fails, controller seems not to respond in time */ +#if 0 +#define CONFIG_DM_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_PCI +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#if !defined(CONFIG_USB_XHCI) || defined(CONFIG_DM_USB) +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MARVELL +#define CONFIG_EHCI_IS_TDI +#endif + +/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */ +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#define CONFIG_SYS_MVFS + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40004030 +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_SYS_MVEBU_DDR_AXP +#define MV_DDR_32BIT + +/* Use random ethernet address if not configured */ +#define CONFIG_LIB_RAND +#define CONFIG_NET_RANDOM_ETHADDR + +/* Default Environment */ +#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200" +#define CONFIG_LOADADDR 0x80000 +#undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */ +#define CONFIG_PREBOOT "usb start; sf probe" + +#endif /* _CONFIG_SYNOLOGY_DS414_H */ -- 2.5.3

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