April 2017 - U-Boot

[U-Boot] __FILE__ usage and and SPL limits for SRAM
by Nishanth Menon 31 May '17

31 May '17

Hi, we've kind of run into an interesting situation recently, but might be of interest for various folks trying to reduce the image sizes. our AM335x device has a limited amount of sram.. and the SPL tries to fit into it (a bit tricky given the restricted space we have on it on certain class of devices). arch/arm/mach-omap2/am33xx/u-boot-spl.lds is a bit custom tailored around this. Key in this is: . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram Now, our jenkins build system happens to use a varied build path and uses O= path. to simplify the details: mkdir /tmp/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb/cccccccccccccccccccccccccccccccccccccccccccccccccc mkdir /tmp/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb/cccccccccccccccccccccccccccccccccccccccccccccccccc/b git clone u-boot cd u-boot git clean -fdx make CROSS_COMPILE=arm-linux-gnueabihf- O=../b am335x_evm_defconfig make CROSS_COMPILE=arm-linux-gnueabihf- O=../b all depending on depth of the path, this would fail.. a little bit of headscratching later.. when using O= build system uses absolute paths, which translates to __FILE__ being absolute paths as well.. in u-boot, any printf("%s", __FILE__) makes u-boot allocate this file path in rodata. So, depending on how deep the path is rodata size varies and ends up pushing .data out of sram max range. we dont really care to put a print of complete absolute path anyways, and I am not really sure of a clean way to resolve this: a) override __FILE__ with something.. -Wbuiltin-macro-redefined kicks in b) replace usage of __FILE__ with something like __FILENAME__ as recommended by [1] What is the suggestion we do? [1] http://stackoverflow.com/questions/8487986/file-macro-shows-full-path -- Regards, Nishanth Menon

8 15

Re: [U-Boot] [PATCH 1/4] arm: iproc: add NAND driver
by Steve Rae 31 May '17

31 May '17

On Fri, Mar 11, 2016 at 11:55 AM, Scott Wood <oss(a)buserror.net> wrote: > On Fri, 2016-03-11 at 11:47 -0800, Steve Rae wrote: >> On Fri, Mar 11, 2016 at 11:29 AM, Scott Wood <oss(a)buserror.net> wrote: >> > On Thu, 2016-03-10 at 14:26 -0800, Steve Rae wrote: >> > > From: Jiandong Zheng <jdzheng(a)broadcom.com> >> > > >> > > Add support for the iproc NAND, and enable on Cygnus and NSP boards. >> > > >> > > Signed-off-by: Jiandong Zheng <jdzheng(a)broadcom.com> >> > > Signed-off-by: Steve Rae <srae(a)broadcom.com> >> > > --- >> > > There was a previous attempt to implement this "iproc NAND" >> > > (see: http://patchwork.ozlabs.org/patch/505399), however, due to the >> > > amount of changes required, it seemed better to implement the code >> > > in a series of steps. This is the first step, where the "iproc_nand.c" >> > > is essentially an empty file (with one function required to allow this >> > > commit to build successfully). >> > >> > I don't see the value of applying a such a do-nothing patch. It's fine to >> > leave out unnecessary features, things that improve performance, etc. but >> > to >> > be applied a patchset should accomplish something useful and correct, not >> > just >> > be a staging area for future patches. >> >> I agree -- but with the previous attempt, there where so many things >> that went wrong, that I cannot comprehend what is needed. >> So, I wanted to break it down into pieces, so that I could get clear >> responses to help me get it right. >> right now, I understand that I need to move certain defines to Kconfig .... > > Go through the previous comments and address (or respond to) them one by one, > then submit again. If you want to break it into multiple patches, that's fine > as long as the intermediate states are sane, but it should all be submitted at > once as part of a patchset (again, except for unnecessary features). OK - that was my plan (to address every previous comment)... I was hoping to get "incremental" comments to indicate that I was resolving them acceptably... My plan was to increment v2, v3, vxxx until it was acceptable. Would this be OK? > > Also, please keep discussion on the mailing list. > Sorry.... >> >> > >> > > diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h >> > > b/arch/arm/include/asm/arch-bcmcygnus/configs.h >> > > index 3c07160..3bf7395 100644 >> > > --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h >> > > +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h >> > > @@ -10,6 +10,7 @@ >> > > #include <asm/iproc-common/configs.h> >> > > >> > > /* uArchitecture specifics */ >> > > +#include <../../../drivers/mtd/nand/iproc_nand_cygnus.h> >> > >> > No. >> >> this "include" line is unacceptable? > > Using "../../.." to reach into a code directory's private headers is > unacceptable, yes. > >> could you propose something that would work? > > If you want the info to be in the driver directory, use an ifdef there, based > on a config symbol. This seems like the better approach. Maybe I misinterpreted the comments related to: +#if defined(CONFIG_CYGNUS) +#include "iproc_nand_cygnus.h" +#elif defined(CONFIG_NS_PLUS) +#include "iproc_nand_ns_plus.h" +#else +#error "Unsupported configuration" +#endif Scott - I thought the you did not like this logic -- now I am thinking you didn't like the "CONFIG_*" names.... I'm guessing that the names should be: CONFIG_SYS_BCM_CYGNUS CONFIG_SYS_BCM_NSPLUS and that they should be added to Kconfig? > > If you want the info to come via the config header, move it to someplace the > config header can properly include. > > -Scott >

3 4

[U-Boot] [ PATCH v2] net: move Broadcom SF2 driver to Kconfig
by Steve Rae 30 May '17

30 May '17

From: Suji Velupillai <suji.velupillai(a)broadcom.com> move to Kconfig: CONFIG_BCM_SF2_ETH CONFIG_BCM_SF2_ETH_DEFAULT_PORT CONFIG_BCM_SF2_ETH_GMAC Also modified defconfigs of all platforms that use these configs. Signed-off-by: Suji Velupillai <suji.velupillai(a)broadcom.com> Tested-by: Suji Velupillai <suji.velupillai(a)broadcom.com> Reviewed-by: JD Zheng <jiandong.zheng(a)broadcom.com> Reviewed-by: Scott Branden <scott.branden(a)broadcom.com> Signed-off-by: Steve Rae <steve.rae(a)raedomain.com> --- Changes in v2: - update Kconfig help text - move CONFIG_BCM_SF2_ETH_DEFAULT_PORT to Kconfig arch/arm/include/asm/arch-bcmcygnus/configs.h | 6 +----- configs/bcm28155_w1d_defconfig | 5 +++-- configs/bcm911360_entphn-ns_defconfig | 3 +++ configs/bcm911360_entphn_defconfig | 3 +++ configs/bcm911360k_defconfig | 3 +++ configs/bcm958300k-ns_defconfig | 3 +++ configs/bcm958300k_defconfig | 3 +++ configs/bcm958305k_defconfig | 3 +++ drivers/net/Kconfig | 24 ++++++++++++++++++++++++ drivers/net/bcm-sf2-eth.h | 2 -- scripts/config_whitelist.txt | 3 --- 11 files changed, 46 insertions(+), 12 deletions(-) diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index af7f3bf..92b1c5e 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 Broadcom Corporation. + * Copyright 2014-2017 Broadcom. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -23,10 +23,6 @@ #define CONFIG_SYS_NS16550_COM3 0x18023000 /* Ethernet */ -#define CONFIG_BCM_SF2_ETH -#define CONFIG_BCM_SF2_ETH_GMAC - -#define CONFIG_PHYLIB #define CONFIG_PHY_BROADCOM #define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/ diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig index aa5216e..4adbce6 100644 --- a/configs/bcm28155_w1d_defconfig +++ b/configs/bcm28155_w1d_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_TARGET_BCM28155_AP=y -CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC" CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -15,7 +14,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y @@ -33,3 +31,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation" CONFIG_G_DNL_VENDOR_NUM=0x18d1 CONFIG_G_DNL_PRODUCT_NUM=0x0d02 +CONFIG_NETDEVICES=y +CONFIG_BCM_SF2_ETH=y +CONFIG_BCM_SF2_ETH_GMAC=y diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig index 4f04590..107c99a 100644 --- a/configs/bcm911360_entphn-ns_defconfig +++ b/configs/bcm911360_entphn-ns_defconfig @@ -19,3 +19,6 @@ CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_NETDEVICES=y +CONFIG_BCM_SF2_ETH=y +CONFIG_BCM_SF2_ETH_GMAC=y diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig index 2469792..8e2dc29 100644 --- a/configs/bcm911360_entphn_defconfig +++ b/configs/bcm911360_entphn_defconfig @@ -19,3 +19,6 @@ CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_NETDEVICES=y +CONFIG_BCM_SF2_ETH=y +CONFIG_BCM_SF2_ETH_GMAC=y diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig index 83afce4..446aab0 100644 --- a/configs/bcm911360k_defconfig +++ b/configs/bcm911360k_defconfig @@ -19,3 +19,6 @@ CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_NETDEVICES=y +CONFIG_BCM_SF2_ETH=y +CONFIG_BCM_SF2_ETH_GMAC=y diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig index b21fea4..5abc03a 100644 --- a/configs/bcm958300k-ns_defconfig +++ b/configs/bcm958300k-ns_defconfig @@ -19,3 +19,6 @@ CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_NETDEVICES=y +CONFIG_BCM_SF2_ETH=y +CONFIG_BCM_SF2_ETH_GMAC=y diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig index 83afce4..446aab0 100644 --- a/configs/bcm958300k_defconfig +++ b/configs/bcm958300k_defconfig @@ -19,3 +19,6 @@ CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_NETDEVICES=y +CONFIG_BCM_SF2_ETH=y +CONFIG_BCM_SF2_ETH_GMAC=y diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig index 83afce4..446aab0 100644 --- a/configs/bcm958305k_defconfig +++ b/configs/bcm958305k_defconfig @@ -19,3 +19,6 @@ CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_NETDEVICES=y +CONFIG_BCM_SF2_ETH=y +CONFIG_BCM_SF2_ETH_GMAC=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 8aa9279..16119ab 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -40,6 +40,30 @@ config ALTERA_TSE Please find details on the "Triple-Speed Ethernet MegaCore Function Resource Center" of Altera. +config BCM_SF2_ETH + bool "Broadcom SF2 (Starfighter2) Ethernet support" + select PHYLIB + help + This is an abstract framework which provides a generic interface + to MAC and DMA management for multiple Broadcom SoCs such as + Cygnus, NSP and bcm28155_ap platforms. + +config BCM_SF2_ETH_DEFAULT_PORT + int "Broadcom SF2 (Starfighter2) Ethernet default port number" + depends on BCM_SF2_ETH + default 0 + help + Default port number for the Starfighter2 ethernet driver. + +config BCM_SF2_ETH_GMAC + bool "Broadcom SF2 (Starfighter2) GMAC Ethernet support" + depends on BCM_SF2_ETH + help + This flag enables the ethernet support for Broadcom platforms with + GMAC such as Cygnus. This driver is based on the framework provided + by the BCM_SF2_ETH driver. + Say Y to any bcmcygnus based platforms. + config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" depends on DM_ETH diff --git a/drivers/net/bcm-sf2-eth.h b/drivers/net/bcm-sf2-eth.h index c4e2e01..efeff15 100644 --- a/drivers/net/bcm-sf2-eth.h +++ b/drivers/net/bcm-sf2-eth.h @@ -20,8 +20,6 @@ /* Support 2 Ethernet ports now */ #define BCM_ETH_MAX_PORT_NUM 2 -#define CONFIG_BCM_SF2_ETH_DEFAULT_PORT 0 - enum { MAC_DMA_TX = 1, MAC_DMA_RX = 2 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 330bc58..5c86d0c 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -230,9 +230,6 @@ CONFIG_BCH_CONST_PARAMS CONFIG_BCH_CONST_T CONFIG_BCM2835_GPIO CONFIG_BCM283X_MU_SERIAL -CONFIG_BCM_SF2_ETH -CONFIG_BCM_SF2_ETH_DEFAULT_PORT -CONFIG_BCM_SF2_ETH_GMAC CONFIG_BD_NUM_CPUS CONFIG_BFIN_ATA_MODE CONFIG_BFIN_MAC_PINS -- 2.7.4

3 2

[U-Boot] [PATCHv5 00/21] Retrieve MAC address from EEPROM
by Olliver Schinagl 30 May '17

30 May '17

First off: P.S. Joe, for some reason my previous patches where added with me as: "oliver(a)schinagl.nl <oliver(a)schinagl.nl>" I see that it comes from patchwork as such. Is there some way to fix this to "Olliver Schinagl <oliver(a)schinagl.nl>"? Below the updated summary: This patch-series introduces methods to retrieve the MAC address from an onboard EEPROM. The series does a few small cleanups at the start, as either I ran into them while doing this series and fixed them along the way or actually depended on them. A manufacturer wants to produce boards and may even have MAC addresses for boards. Maintaining unique environments on a per-board basis however is horrible. Also this data should be very persistent, and not easily deletable by simply wiping the environment or device tree. Finally there are chips available on the market with a pre-programmed MAC address chips (proms) that a board manufacturer wants to use. Because of this, the MAC needs to be stored be able to read from such an 'external' source. The current idea of the eeprom layout, is to skip the first 8 bytes, so that other information can be stored there if needed, for example a header with some magic to identify the EEPROM. Or equivalent purposes. After those 8 bytes the MAC address follows the first macaddress. The macaddress is appended by a CRC8 byte and then padded to make for nice 8 bytes. Following the first macaddress one can store a second, or a third etc etc macaddress. The CRC8 is optional (via a define) but is strongly recommended to have. It helps preventing user error and more importantly, checks if the bytes read are actually a user inserted address. E.g. only writing 1 macaddress into the eeprom but trying to consume 2. These patches where tested on Olimex OLinuXino Lime1 (A10/A20), Lime2 (NAND and eMMC) and A20-OLinuXino-MICRO-4G variants and have been in use internally on our production systems since v2 of this patch set. TODO in a follow up series: * Replace the I2C specific read function to a generic function using Maxime Ripard's EEPROM uclass once merged. * Upgrade to use the EERPOM layout functionality. ======= Changes since v4: * Some patches have been merged, so those are no longer included in the set. * Reworked review comments * Added the source of a MAC address * Made sunxi-gmac a subclassed driver * Switch sunxi-[eg]mac to Kconfig * Drop the FDT injection code for now, this needs more thought/discussion Changes since v3: * Split off board specific stuff and only modify the generic functions * Make reading of an eeprom available to every board. By default this is unconfigure and thus should just fall through * Clean some minor bits up (ARP_HLEN) and use it more generically * Update the gen_ethaddr_crc as suggested by simon * Let the fixup_ethernet from fdt_common insert mac addresses to the environment for unconfigured devices. There is a small caveat here however as described in the TODO above. * Print the mac address that u-boot assigned to each device. Changes since v2: * Drop the id byte altogether and just mark it as reserved. The 'index' can be used to indicate the interface instead * Addopt the read_rom_hwaddr hooks * Renamed crc8 tool to gen_ethaddr_crc * Improved the layout EEPROM example * Made a function out of the hwaddress writing function in sunxi_emac so it can be re-used as the write_hwaddr net_ops hook. * No longer handle fdt parameters in board.c Changes since v1: * Do not CRC the id byte, move it just after the crc byte. One of the reasons I decided to move it after the crc8 was mostly due to mass generation of MAC + CRC combo's where the ID is still unknown. Also not crc-ing the ID means that it is much easier for a user to change it (via the u-boot i2c cmd line or from within linux) without having to worry about the crc. * Add a generator to convert a MAC address from the input to a MAC + CRC8 on the output. Olliver Schinagl (21): net: cosmetic: Do not use magic values for ARP_HLEN net: core: Sanitize get/set operations for enetaddr net: core: Inform the user of the device MAC address net: core: Add function to check/set MAC locality net: Add ability to set MAC address via EEPROM net: core: print the source of the MAC address net: cosmetic: A MAC address is not limited to SROM fdt: fixup_eth: Remove code duplication with a function fdt: fixup_eth: improve error catching/reduce identation net: sunxi: Enable I2C bus set via NET_ETHADDR_EEPROM_I2C_BUS net: sunxi_[eg]mac: Convert to Kconfig arm: sunxi: Expose function to generate sunxi-specific a MAC address net: sunxi_emac: Write HW address via net_ops hook net: sunxi: Have sunxi common functions together net: sunxi_emac: Add read_rom_hwaddr hook net: sunxi_gmac: Make the sunxi variant of dw driver a subclass net: dw: Expose designware_eth_start net: sunxi_gmac: Add read_rom_hwaddr hook net: sun8i_gmac: Add read_rom_hwaddr hook net: sun8i: fix whitespace net: core: Check return value of read_rom_hwaddr arch/arm/include/asm/arch-sunxi/sys_proto.h | 7 +- arch/arm/mach-sunxi/board.c | 1 - board/sunxi/Kconfig | 4 + board/sunxi/Makefile | 1 - board/sunxi/board.c | 145 ++++++++++++++++--------- common/fdt_support.c | 33 +++--- configs/A10-OLinuXino-Lime_defconfig | 4 +- configs/A10s-OLinuXino-M_defconfig | 2 +- configs/A20-OLinuXino-Lime2_defconfig | 5 +- configs/A20-OLinuXino-Lime_defconfig | 5 +- configs/A20-OLinuXino_MICRO_defconfig | 5 +- configs/A20-Olimex-SOM-EVB_defconfig | 4 +- configs/Bananapi_defconfig | 4 +- configs/Bananapro_defconfig | 4 +- configs/CSQ_CS908_defconfig | 3 +- configs/Colombus_defconfig | 4 +- configs/Cubieboard2_defconfig | 4 +- configs/Cubieboard_defconfig | 3 +- configs/Cubietruck_defconfig | 4 +- configs/Hummingbird_A31_defconfig | 4 +- configs/Itead_Ibox_A20_defconfig | 4 +- configs/Lamobo_R1_defconfig | 4 +- configs/Linksprite_pcDuino3_Nano_defconfig | 4 +- configs/Linksprite_pcDuino3_defconfig | 4 +- configs/Linksprite_pcDuino_defconfig | 2 +- configs/Marsboard_A10_defconfig | 2 +- configs/Mele_A1000G_quad_defconfig | 3 +- configs/Mele_A1000_defconfig | 3 +- configs/Mele_I7_defconfig | 3 +- configs/Mele_M3_defconfig | 3 +- configs/Mele_M5_defconfig | 3 +- configs/Mele_M9_defconfig | 3 +- configs/Orangepi_defconfig | 4 +- configs/Orangepi_mini_defconfig | 4 +- configs/Sinlinx_SinA31s_defconfig | 3 +- configs/Sinovoip_BPI_M2_defconfig | 4 +- configs/Wits_Pro_A20_DKT_defconfig | 4 +- configs/ba10_tv_box_defconfig | 2 +- configs/i12-tvbox_defconfig | 4 +- configs/icnova-a20-swac_defconfig | 4 +- configs/jesurun_q5_defconfig | 3 +- configs/mixtile_loftq_defconfig | 4 +- doc/README.enetaddr | 99 +++++++++++++++++ drivers/net/Kconfig | 33 +++++- drivers/net/Makefile | 5 +- drivers/net/designware.c | 3 +- drivers/net/designware.h | 1 + drivers/net/sun8i_emac.c | 15 ++- drivers/net/sunxi_common.c | 33 ++++++ drivers/net/sunxi_common.h | 13 +++ drivers/net/sunxi_emac.c | 15 +++ board/sunxi/gmac.c => drivers/net/sunxi_gmac.c | 54 ++++++++- include/configs/sunxi-common.h | 5 - include/net.h | 53 ++++++++- net/Kconfig | 59 ++++++++++ net/eth-uclass.c | 65 ++++++----- net/eth_common.c | 53 ++++++++- net/eth_legacy.c | 7 +- 58 files changed, 626 insertions(+), 207 deletions(-) create mode 100644 drivers/net/sunxi_common.c create mode 100644 drivers/net/sunxi_common.h rename board/sunxi/gmac.c => drivers/net/sunxi_gmac.c (67%) -- 2.11.0

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[U-Boot] [PATCH] Add support for Microchip LAN75xx and LAN78xx
by Yuiko.Oshino＠microchip.com 30 May '17

30 May '17

From: Yuiko Oshino <yuiko.oshino(a)microchip.com> Add support for Microchip LAN7500, LAN7800 and 7850, USB to 10/100/1000 Ethernet Controllers Signed-off-by: Yuiko Oshino <yuiko.oshino(a)microchip.com> Cc: Marek Vasut <marex(a)denx.de> --- drivers/usb/Kconfig | 2 + drivers/usb/eth/Kconfig | 18 ++ drivers/usb/eth/Makefile | 2 + drivers/usb/eth/lan75xx.c | 463 ++++++++++++++++++++++++++++++ drivers/usb/eth/lan78xx.c | 611 +++++++++++++++++++++++++++++++++++++++ drivers/usb/eth/lan7x.c | 680 ++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/eth/lan7x.h | 189 ++++++++++++ drivers/usb/eth/usb_ether.c | 14 + include/usb_ether.h | 12 + 9 files changed, 1991 insertions(+) create mode 100644 drivers/usb/eth/Kconfig create mode 100644 drivers/usb/eth/lan75xx.c create mode 100644 drivers/usb/eth/lan78xx.c create mode 100644 drivers/usb/eth/lan7x.c create mode 100644 drivers/usb/eth/lan7x.h diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index da3ec2f..62126aa 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -94,4 +94,6 @@ endif source "drivers/usb/gadget/Kconfig" +source "drivers/usb/eth/Kconfig" + endif diff --git a/drivers/usb/eth/Kconfig b/drivers/usb/eth/Kconfig new file mode 100644 index 0000000..a07243f --- /dev/null +++ b/drivers/usb/eth/Kconfig @@ -0,0 +1,18 @@ +comment "USB to Ethernet Controller Drivers" + +config USB_ETHER_LAN75XX + bool "Microchip LAN75XX support" + ---help--- + Say Y here if you would like to support Microchip LAN75XX Hi-Speed + USB 2.0 to 10/100/1000 Gigabit Ethernet controller. + Supports 10Base-T/ 100Base-TX/1000Base-T. + This driver supports the internal PHY. + +config USB_ETHER_LAN78XX + bool "Microchip LAN78XX support" + ---help--- + Say Y here if you would like to support Microchip LAN78XX USB 3.1 + Gen 1 to 10/100/1000 Gigabit Ethernet controller. + Supports 10Base-T/ 100Base-TX/1000Base-T. + This driver supports the internal PHY. + diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile index 4c44efc..4b935a3 100644 --- a/drivers/usb/eth/Makefile +++ b/drivers/usb/eth/Makefile @@ -9,4 +9,6 @@ obj-$(CONFIG_USB_ETHER_ASIX) += asix.o obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o +obj-$(CONFIG_USB_ETHER_LAN75XX) += lan7x.o lan75xx.o +obj-$(CONFIG_USB_ETHER_LAN78XX) += lan7x.o lan78xx.o obj-$(CONFIG_USB_ETHER_RTL8152) += r8152.o r8152_fw.o diff --git a/drivers/usb/eth/lan75xx.c b/drivers/usb/eth/lan75xx.c new file mode 100644 index 0000000..f67b216 --- /dev/null +++ b/drivers/usb/eth/lan75xx.c @@ -0,0 +1,463 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <usb.h> +#include <linux/mii.h> +#include "usb_ether.h" +#include "lan7x.h" + +/* SCSRs */ +#define LAN75XX_HW_CFG_BIR BIT(7) + +#define LAN75XX_BURST_CAP 0x034 + +#define LAN75XX_BULK_IN_DLY 0x03C + +#define LAN75XX_RFE_CTL 0x060 + +#define LAN75XX_FCT_RX_CTL 0x090 + +#define LAN75XX_FCT_TX_CTL 0x094 + +#define LAN75XX_FCT_RX_FIFO_END 0x098 + +#define LAN75XX_FCT_TX_FIFO_END 0x09C + +#define LAN75XX_FCT_FLOW 0x0A0 + +/* MAC ADDRESS PERFECT FILTER For LAN75xx */ +#define LAN75XX_ADDR_FILTX 0x300 +#define LAN75XX_ADDR_FILTX_FB_VALID BIT(31) + +#ifndef CONFIG_DM_ETH +/* local vars */ +static int curr_eth_dev; /* index for name of next device detected */ + +/* local defines */ +#define LAN75XX_BASE_NAME "lan75xx" +#endif + +/* + * Lan75xx infrastructure commands + */ +static int lan75xx_phy_gig_workaround(struct usb_device *udev, + struct ueth_data *dev) +{ + int ret = 0; + + /* Only internal phy */ + /* Set the phy in Gig loopback */ + lan7x_mdio_write(udev, dev->phy_id, MII_BMCR, + (BMCR_LOOPBACK | BMCR_SPEED1000)); + + /* Wait for the link up */ + ret = lan7x_mdio_wait_for_bit(udev, "BMSR_LSTATUS", + dev->phy_id, MII_BMSR, BMSR_LSTATUS, + true, PHY_CONNECT_TIMEOUT_MS); + if (ret) + return ret; + + /* phy reset */ + ret = lan7x_pmt_phy_reset(udev, dev); + return ret; +} + +static int lan75xx_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev) +{ + uint32_t flow = 0, fct_flow = 0; + int ret; + + ret = lan7x_update_flowcontrol(udev, dev, &flow, &fct_flow); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, FLOW, flow); + ret = lan7x_write_reg(udev, LAN75XX_FCT_FLOW, fct_flow); + return ret; +} + +static int lan75xx_read_mac(unsigned char *enetaddr, + struct usb_device *udev) +{ + /* + * Refer to the doc/README.enetaddr and doc/README.usb for + * the U-Boot MAC address policy + */ + return lan7x_read_eeprom_mac(enetaddr, udev); +} + +static int lan75xx_write_hwaddr_common(struct usb_device *udev, + struct lan7x_private *priv, + unsigned char *enetaddr) +{ + u32 addr_lo = get_unaligned_le32(&enetaddr[0]); + u32 addr_hi = (u32)get_unaligned_le16(&enetaddr[4]); + int ret; + + /* set hardware address */ + ret = lan7x_write_reg(udev, RX_ADDRL, addr_lo); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, RX_ADDRH, addr_hi); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_ADDR_FILTX + 4, addr_lo); + if (ret) + return ret; + + addr_hi |= LAN75XX_ADDR_FILTX_FB_VALID; + ret = lan7x_write_reg(udev, LAN75XX_ADDR_FILTX, addr_hi); + if (ret) + return ret; + + debug("MAC addr %pM written\n", enetaddr); + priv->have_hwaddr = 1; + + return 0; +} + +static int lan75xx_set_multicast(struct usb_device *udev) +{ + int ret; + u32 write_buf; + + /* No multicast in u-boot */ + write_buf = RFE_CTL_BCAST_EN | RFE_CTL_DA_PERFECT; + ret = lan7x_write_reg(udev, LAN75XX_RFE_CTL, write_buf); + + return ret; +} + +/* starts the TX path */ +static void lan75xx_start_tx_path(struct usb_device *udev) +{ + u32 reg_val; + + /* Enable Tx at MAC */ + reg_val = MAC_TX_TXEN; + lan7x_write_reg(udev, MAC_TX, reg_val); + + /* Enable Tx at SCSRs */ + reg_val = FCT_TX_CTL_EN; + lan7x_write_reg(udev, LAN75XX_FCT_TX_CTL, reg_val); +} + +/* Starts the Receive path */ +static void lan75xx_start_rx_path(struct usb_device *udev) +{ + u32 reg_val; + + /* Enable Rx at MAC */ + reg_val = LAN7X_MAC_RX_MAX_SIZE_DEFAULT | + MAC_RX_FCS_STRIP | MAC_RX_RXEN; + lan7x_write_reg(udev, MAC_RX, reg_val); + + /* Enable Rx at SCSRs */ + reg_val = FCT_RX_CTL_EN; + lan7x_write_reg(udev, LAN75XX_FCT_RX_CTL, reg_val); +} + +static int lan75xx_basic_reset(struct usb_device *udev, + struct ueth_data *dev, + struct lan7x_private *priv) +{ + int ret; + u32 write_buf; + + ret = lan7x_basic_reset(udev, dev); + if (ret) + return ret; + + /* Keep the chip ID */ + ret = lan7x_read_reg(udev, ID_REV, &priv->chipid); + if (ret) + return ret; + debug("LAN75xx ID_REV = 0x%08x\n", priv->chipid); + + priv->chipid = (priv->chipid & ID_REV_CHIP_ID_MASK) >> 16; + + /* Respond to the IN token with a NAK */ + ret = lan7x_read_reg(udev, HW_CFG, &write_buf); + if (ret) + return ret; + write_buf |= LAN75XX_HW_CFG_BIR; + ret = lan7x_write_reg(udev, HW_CFG, write_buf); + + return ret; +} + +static int lan75xx_init_common(struct usb_device *udev, + struct ueth_data *dev, + struct lan7x_private *priv, + unsigned char *enetaddr) +{ + int ret; + u32 write_buf; + + /* Reset and read Mac addr were done in get_info() or in probe() */ + +#ifndef CONFIG_DM_ETH + if (!priv->have_hwaddr && is_valid_ethaddr(enetaddr)) { + priv->have_hwaddr = 1; + debug("LAN75xx: MAC address found and set %pM\n", enetaddr); + } +#endif + if (!priv->have_hwaddr) { + printf("Error: LAN75xx: No MAC address set - set usbethaddr\n"); + return -EADDRNOTAVAIL; + } + ret = lan75xx_write_hwaddr_common(udev, priv, enetaddr); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, INT_STS, 0xFFFFFFFF); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_BURST_CAP, 0); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN75XX_BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); + if (ret) + return ret; + + /* set FIFO sizes */ + write_buf = (MAX_RX_FIFO_SIZE - 512) / 512; + ret = lan7x_write_reg(udev, LAN75XX_FCT_RX_FIFO_END, write_buf); + if (ret) + return ret; + + write_buf = (MAX_TX_FIFO_SIZE - 512) / 512; + ret = lan7x_write_reg(udev, LAN75XX_FCT_TX_FIFO_END, write_buf); + if (ret) + return ret; + + /* Init Tx */ + ret = lan7x_write_reg(udev, FLOW, 0); + if (ret) + return ret; + + /* Init Rx. Set Vlan, keep defult for VLAN on 75xx */ + ret = lan75xx_set_multicast(udev); + if (ret) + return ret; + + /* phy workaround for gig link */ + ret = lan75xx_phy_gig_workaround(udev, dev); + if (ret) + return ret; + + /* Init PHY, autonego, and link */ + ret = lan7x_phy_initialize(udev, dev); + if (ret) + return ret; + + /* + * MAC_CR has to be set after PHY init. + * MAC will auto detect the PHY speed. + */ + ret = lan7x_read_reg(udev, MAC_CR, &write_buf); + if (ret) + return ret; + write_buf |= MAC_CR_AUTO_DUPLEX | MAC_CR_AUTO_SPEED | MAC_CR_ADP; + ret = lan7x_write_reg(udev, MAC_CR, write_buf); + if (ret) + return ret; + + lan75xx_start_tx_path(udev); + lan75xx_start_rx_path(udev); + + ret = lan75xx_update_flowcontrol(udev, dev); + + return ret; +} + +#ifndef CONFIG_DM_ETH +/* + * lan75xx callbacks + */ +static int lan75xx_init(struct eth_device *eth, bd_t *bd) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct usb_device *udev = dev->pusb_dev; + struct lan7x_private *priv = (struct lan7x_private *)dev->dev_priv; + + return lan75xx_init_common(udev, dev, priv, eth->enetaddr); +} + +static int lan75xx_write_hwaddr(struct eth_device *eth) +{ + struct ueth_data *dev = eth->priv; + struct usb_device *udev = dev->pusb_dev; + struct lan7x_private *priv = dev->dev_priv; + + return lan75xx_write_hwaddr_common(udev, priv, eth->enetaddr); +} + +/* + * Microchip probing functions + */ +void lan75xx_eth_before_probe(void) +{ + curr_eth_dev = 0; +} + +static const struct lan7x_dongle lan75xx_dongles[] = { + {0x0424, 0x7500}, /* LAN7500 USB Ethernet */ + {0x0000, 0x0000} /* END - Do not remove */ +}; + +/* Probe to see if a new device is actually an Microchip device */ +int lan75xx_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss) +{ + int i; + + /* let's examine the device now */ + for (i = 0; lan75xx_dongles[i].vendor != 0; i++) { + if (dev->descriptor.idVendor == lan75xx_dongles[i].vendor && + dev->descriptor.idProduct == lan75xx_dongles[i].product) + /* Found a supported dongle */ + break; + } + if (lan75xx_dongles[i].vendor == 0) + return 0; + + /* At this point, we know we've got a live one */ + debug("\n\nUSB Ethernet device LAN75xx detected\n"); + + /* + * Note that this function needs to return 1 + * for success + */ + return lan7x_eth_probe(dev, ifnum, ss); +} + +int lan75xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, + struct eth_device *eth) +{ + struct lan7x_private *priv = ss->dev_priv; + + printf("LAN75xx name: %s%d\n", LAN75XX_BASE_NAME, curr_eth_dev); + + if (!eth) { + debug("%s: missing parameter.\n", __func__); + return 0; + } + sprintf(eth->name, "%s%d", LAN75XX_BASE_NAME, curr_eth_dev++); + eth->init = lan75xx_init; + eth->send = lan7x_send; + eth->recv = lan7x_recv; + eth->halt = lan7x_halt; + eth->write_hwaddr = lan75xx_write_hwaddr; + eth->priv = ss; + + /* Do a reset in order to get the MAC address from HW */ + if (lan75xx_basic_reset(dev, ss, priv)) + return 0; + + /* Get the MAC address */ + /* + * We must set the eth->enetaddr from HW because the upper layer + * will force to use the environmental var (usbethaddr) or random if + * there is no valid MAC address in eth->enetaddr. + */ + lan75xx_read_mac(eth->enetaddr, dev); + /* Do not return 0 for not finding MAC addr in HW */ + + return 1; +} +#endif /* !CONFIG_DM_ETH */ + +#ifdef CONFIG_DM_ETH +static int lan75xx_eth_start(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + + /* Driver-model Ethernet ensures we have this */ + priv->have_hwaddr = 1; + + return lan75xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr); +} + +int lan75xx_write_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct lan7x_private *priv = dev_get_priv(dev); + + return lan75xx_write_hwaddr_common(udev, priv, pdata->enetaddr); +} + +int lan75xx_read_rom_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + ret = lan75xx_read_mac(pdata->enetaddr, udev); + if (ret) + memset(pdata->enetaddr, 0, 6); + + return 0; +} + +static int lan75xx_eth_probe(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + struct eth_pdata *pdata = dev_get_platdata(dev); + + /* Do a reset in order to get the MAC address from HW */ + if (lan75xx_basic_reset(udev, ueth, priv)) + return 0; + + /* Get the MAC address */ + /* + * We must set the eth->enetaddr from HW because the upper layer + * will force to use the environmental var (usbethaddr) or random if + * there is no valid MAC address in eth->enetaddr. + */ + lan75xx_read_mac(pdata->enetaddr, udev); + /* Do not return 0 for not finding MAC addr in HW */ + + return usb_ether_register(dev, ueth, RX_URB_SIZE); +} + +static const struct eth_ops lan75xx_eth_ops = { + .start = lan75xx_eth_start, + .send = lan7x_eth_send, + .recv = lan7x_eth_recv, + .free_pkt = lan7x_free_pkt, + .stop = lan7x_eth_stop, + .write_hwaddr = lan75xx_write_hwaddr, + .read_rom_hwaddr = lan75xx_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(lan75xx_eth) = { + .name = "lan75xx_eth", + .id = UCLASS_ETH, + .probe = lan75xx_eth_probe, + .ops = &lan75xx_eth_ops, + .priv_auto_alloc_size = sizeof(struct lan7x_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +static const struct usb_device_id lan75xx_eth_id_table[] = { + { USB_DEVICE(0x0424, 0x7500) }, /* LAN7500 USB Ethernet */ + { } /* Terminating entry */ +}; + +U_BOOT_USB_DEVICE(lan75xx_eth, lan75xx_eth_id_table); +#endif diff --git a/drivers/usb/eth/lan78xx.c b/drivers/usb/eth/lan78xx.c new file mode 100644 index 0000000..e450f2c --- /dev/null +++ b/drivers/usb/eth/lan78xx.c @@ -0,0 +1,611 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <usb.h> +#include "usb_ether.h" +#include "lan7x.h" + +/* LAN78xx specific register/bit defines */ +#define LAN78XX_HW_CFG_LED1_EN BIT(21) /* Muxed with EEDO */ +#define LAN78XX_HW_CFG_LED0_EN BIT(20) /* Muxed with EECLK */ + +#define LAN78XX_USB_CFG0 0x080 +#define LAN78XX_USB_CFG0_BIR BIT(6) + +#define LAN78XX_BURST_CAP 0x090 + +#define LAN78XX_BULK_IN_DLY 0x094 + +#define LAN78XX_RFE_CTL 0x0B0 + +#define LAN78XX_FCT_RX_CTL 0x0C0 + +#define LAN78XX_FCT_TX_CTL 0x0C4 + +#define LAN78XX_FCT_RX_FIFO_END 0x0C8 + +#define LAN78XX_FCT_TX_FIFO_END 0x0CC + +#define LAN78XX_FCT_FLOW 0x0D0 + +#define LAN78XX_MAF_BASE 0x400 +#define LAN78XX_MAF_HIX 0x00 +#define LAN78XX_MAF_LOX 0x04 +#define LAN78XX_MAF_HI_BEGIN (LAN78XX_MAF_BASE + LAN78XX_MAF_HIX) +#define LAN78XX_MAF_LO_BEGIN (LAN78XX_MAF_BASE + LAN78XX_MAF_LOX) +#define LAN78XX_MAF_HI(index) (LAN78XX_MAF_BASE + (8 * (index)) + \ + (LAN78XX_MAF_HIX)) +#define LAN78XX_MAF_LO(index) (LAN78XX_MAF_BASE + (8 * (index)) + \ + (LAN78XX_MAF_LOX)) +#define LAN78XX_MAF_HI_VALID BIT(31) + +/* OTP registers */ +#define LAN78XX_OTP_BASE_ADDR 0x00001000 + +#define LAN78XX_OTP_PWR_DN (LAN78XX_OTP_BASE_ADDR + 4 * 0x00) +#define LAN78XX_OTP_PWR_DN_PWRDN_N BIT(0) + +#define LAN78XX_OTP_ADDR1 (LAN78XX_OTP_BASE_ADDR + 4 * 0x01) +#define LAN78XX_OTP_ADDR1_15_11 0x1F + +#define LAN78XX_OTP_ADDR2 (LAN78XX_OTP_BASE_ADDR + 4 * 0x02) +#define LAN78XX_OTP_ADDR2_10_3 0xFF + +#define LAN78XX_OTP_RD_DATA (LAN78XX_OTP_BASE_ADDR + 4 * 0x06) + +#define LAN78XX_OTP_FUNC_CMD (LAN78XX_OTP_BASE_ADDR + 4 * 0x08) +#define LAN78XX_OTP_FUNC_CMD_READ BIT(0) + +#define LAN78XX_OTP_CMD_GO (LAN78XX_OTP_BASE_ADDR + 4 * 0x0A) +#define LAN78XX_OTP_CMD_GO_GO BIT(0) + +#define LAN78XX_OTP_STATUS (LAN78XX_OTP_BASE_ADDR + 4 * 0x0C) +#define LAN78XX_OTP_STATUS_BUSY BIT(0) + +#define LAN78XX_OTP_INDICATOR_1 0xF3 +#define LAN78XX_OTP_INDICATOR_2 0xF7 + +#ifndef CONFIG_DM_ETH +/* local vars */ +static int curr_eth_dev; /* index for name of next device detected */ + +/* local defines */ +#define LAN78XX_BASE_NAME "lan78xx" +#endif + +/* + * Lan78xx infrastructure commands + */ +static int lan78xx_read_raw_otp(struct usb_device *udev, u32 offset, + u32 length, u8 *data) +{ + int i; + int ret; + u32 buf; + + ret = lan7x_read_reg(udev, LAN78XX_OTP_PWR_DN, &buf); + if (ret) + return ret; + + if (buf & LAN78XX_OTP_PWR_DN_PWRDN_N) { + /* clear it and wait to be cleared */ + ret = lan7x_write_reg(udev, LAN78XX_OTP_PWR_DN, 0); + + ret = lan7x_wait_for_bit(udev, "LAN78XX_OTP_PWR_DN_PWRDN_N", + LAN78XX_OTP_PWR_DN, + LAN78XX_OTP_PWR_DN_PWRDN_N, + false, 1000); + if (ret) + return ret; + } + + for (i = 0; i < length; i++) { + ret = lan7x_write_reg(udev, LAN78XX_OTP_ADDR1, + ((offset + i) >> 8) & + LAN78XX_OTP_ADDR1_15_11); + ret = lan7x_write_reg(udev, LAN78XX_OTP_ADDR2, + ((offset + i) & LAN78XX_OTP_ADDR2_10_3)); + + ret = lan7x_write_reg(udev, LAN78XX_OTP_FUNC_CMD, + LAN78XX_OTP_FUNC_CMD_READ); + ret = lan7x_write_reg(udev, LAN78XX_OTP_CMD_GO, + LAN78XX_OTP_CMD_GO_GO); + + if (ret) + return ret; + + ret = lan7x_wait_for_bit(udev, "LAN78XX_OTP_STATUS_BUSY", + LAN78XX_OTP_STATUS, + LAN78XX_OTP_STATUS_BUSY, + false, 1000); + if (ret) + return ret; + + ret = lan7x_read_reg(udev, LAN78XX_OTP_RD_DATA, &buf); + + data[i] = (u8)(buf & 0xFF); + } + + return 0; +} + +static int lan78xx_read_otp(struct usb_device *udev, u32 offset, + u32 length, u8 *data) +{ + u8 sig; + int ret; + + ret = lan78xx_read_raw_otp(udev, 0, 1, &sig); + + if (!ret) { + if (sig == LAN78XX_OTP_INDICATOR_1) + offset = offset; + else if (sig == LAN78XX_OTP_INDICATOR_2) + offset += 0x100; + else + return -EINVAL; + ret = lan78xx_read_raw_otp(udev, offset, length, data); + } + debug("LAN78x: MAC address from OTP = %pM\n", data); + + return ret; +} + +static int lan78xx_read_otp_mac(unsigned char *enetaddr, + struct usb_device *udev) +{ + int ret; + + memset(enetaddr, 0, 6); + + ret = lan78xx_read_otp(udev, + EEPROM_MAC_OFFSET, + ETH_ALEN, + enetaddr); + if (!ret && is_valid_ethaddr(enetaddr)) { + /* eeprom values are valid so use them */ + debug("MAC address read from OTP %pM\n", enetaddr); + return 0; + } + debug("MAC address read from OTP invalid %pM\n", enetaddr); + + memset(enetaddr, 0, 6); + return -1; +} + +static int lan78xx_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev) +{ + uint32_t flow = 0, fct_flow = 0; + int ret; + + ret = lan7x_update_flowcontrol(udev, dev, &flow, &fct_flow); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, FLOW, flow); + ret = lan7x_write_reg(udev, LAN78XX_FCT_FLOW, fct_flow); + return ret; +} + +static int lan78xx_read_mac(unsigned char *enetaddr, + struct usb_device *udev, + struct lan7x_private *priv) +{ + u32 val; + int ret; + int saved = 0, done = 0; + + /* + * Depends on chip, some EEPROM pins are muxed with LED function. + * disable & restore LED function to access EEPROM. + */ + if ((priv->chipid == ID_REV_CHIP_ID_7800) || + (priv->chipid == ID_REV_CHIP_ID_7850)) { + ret = lan7x_read_reg(udev, HW_CFG, &val); + saved = val; + val &= ~(LAN78XX_HW_CFG_LED1_EN | LAN78XX_HW_CFG_LED0_EN); + ret = lan7x_write_reg(udev, HW_CFG, val); + if (ret) + goto restore; + } + + /* + * Refer to the doc/README.enetaddr and doc/README.usb for + * the U-Boot MAC address policy + */ + /* try reading mac address from EEPROM, then from OTP */ + ret = lan7x_read_eeprom_mac(enetaddr, udev); + if (!ret) + done = 1; + +restore: + if ((priv->chipid == ID_REV_CHIP_ID_7800) || + (priv->chipid == ID_REV_CHIP_ID_7850)) { + ret = lan7x_write_reg(udev, HW_CFG, saved); + } + /* if the EEPROM mac address is good, then exit */ + if (done) + return 0; + + /* try reading mac address from OTP if the device is LAN78xx */ + ret = lan78xx_read_otp_mac(enetaddr, udev); + + return ret; +} + +static int lan78xx_write_hwaddr_common(struct usb_device *udev, + struct lan7x_private *priv, + unsigned char *enetaddr) +{ + u32 addr_lo = get_unaligned_le32(&enetaddr[0]); + u32 addr_hi = (u32)get_unaligned_le16(&enetaddr[4]); + int ret; + + /* set hardware address */ + ret = lan7x_write_reg(udev, RX_ADDRL, addr_lo); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, RX_ADDRH, addr_hi); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_MAF_LO(0), addr_lo); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_MAF_HI(0), + addr_hi | LAN78XX_MAF_HI_VALID); + if (ret) + return ret; + + debug("MAC addr %pM written\n", enetaddr); + priv->have_hwaddr = 1; + + return 0; +} + +static int lan78xx_set_multicast(struct usb_device *udev) +{ + int ret; + u32 write_buf; + + /* No multicast in u-boot */ + write_buf = RFE_CTL_BCAST_EN | RFE_CTL_DA_PERFECT; + ret = lan7x_write_reg(udev, LAN78XX_RFE_CTL, write_buf); + if (ret) + return ret; + + return 0; +} + +/* starts the TX path */ +static void lan78xx_start_tx_path(struct usb_device *udev) +{ + u32 reg_val; + + /* Enable Tx at MAC */ + reg_val = MAC_TX_TXEN; + lan7x_write_reg(udev, MAC_TX, reg_val); + + /* Enable Tx at SCSRs */ + reg_val = FCT_TX_CTL_EN; + lan7x_write_reg(udev, LAN78XX_FCT_TX_CTL, reg_val); +} + +/* Starts the Receive path */ +static void lan78xx_start_rx_path(struct usb_device *udev) +{ + u32 reg_val; + + /* Enable Rx at MAC */ + reg_val = LAN7X_MAC_RX_MAX_SIZE_DEFAULT | + MAC_RX_FCS_STRIP | MAC_RX_RXEN; + lan7x_write_reg(udev, MAC_RX, reg_val); + + /* Enable Rx at SCSRs */ + reg_val = FCT_RX_CTL_EN; + lan7x_write_reg(udev, LAN78XX_FCT_RX_CTL, reg_val); +} + +static int lan78xx_basic_reset(struct usb_device *udev, + struct ueth_data *dev, + struct lan7x_private *priv) +{ + int ret; + u32 write_buf; + + ret = lan7x_basic_reset(udev, dev); + if (ret) + return ret; + + /* Keep the chip ID */ + ret = lan7x_read_reg(udev, ID_REV, &priv->chipid); + if (ret) + return ret; + debug("LAN78xx ID_REV = 0x%08x\n", priv->chipid); + + priv->chipid = (priv->chipid & ID_REV_CHIP_ID_MASK) >> 16; + + /* Respond to the IN token with a NAK */ + ret = lan7x_read_reg(udev, LAN78XX_USB_CFG0, &write_buf); + if (ret) + return ret; + write_buf |= LAN78XX_USB_CFG0_BIR; + ret = lan7x_write_reg(udev, LAN78XX_USB_CFG0, write_buf); + + return ret; +} + +static int lan78xx_init_common(struct usb_device *udev, + struct ueth_data *dev, + struct lan7x_private *priv, + unsigned char *enetaddr) +{ + int ret; + u32 write_buf; + + /* Reset and read Mac addr were done in get_info() or in probe() */ + +#ifndef CONFIG_DM_ETH + if (!priv->have_hwaddr && is_valid_ethaddr(enetaddr)) { + priv->have_hwaddr = 1; + debug("LAN78xx: MAC address found and set %pM\n", enetaddr); + } +#endif + if (!priv->have_hwaddr) { + printf("Error: LAN78xx: No MAC address set - set usbethaddr\n"); + return -EADDRNOTAVAIL; + } + ret = lan78xx_write_hwaddr_common(udev, priv, enetaddr); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_BURST_CAP, 0); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, LAN78XX_BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); + if (ret) + return ret; + + ret = lan7x_write_reg(udev, INT_STS, 0xFFFFFFFF); + if (ret) + return ret; + + /* set FIFO sizes */ + write_buf = (MAX_RX_FIFO_SIZE - 512) / 512; + ret = lan7x_write_reg(udev, LAN78XX_FCT_RX_FIFO_END, write_buf); + if (ret) + return ret; + + write_buf = (MAX_TX_FIFO_SIZE - 512) / 512; + ret = lan7x_write_reg(udev, LAN78XX_FCT_TX_FIFO_END, write_buf); + if (ret) + return ret; + + /* Init Tx */ + ret = lan7x_write_reg(udev, FLOW, 0); + if (ret) + return ret; + + /* Init Rx. Set Vlan, keep defult for VLAN on 78xx */ + ret = lan78xx_set_multicast(udev); + if (ret < 0) + return ret; + + /* Init PHY, autonego, and link */ + ret = lan7x_phy_initialize(udev, dev); + if (ret < 0) + return ret; + + /* + * MAC_CR has to be set after PHY init. + * MAC will auto detect the PHY speed. + */ + ret = lan7x_read_reg(udev, MAC_CR, &write_buf); + if (ret) + return ret; + write_buf |= MAC_CR_AUTO_DUPLEX | MAC_CR_AUTO_SPEED | MAC_CR_ADP; + ret = lan7x_write_reg(udev, MAC_CR, write_buf); + if (ret) + return ret; + + lan78xx_start_tx_path(udev); + lan78xx_start_rx_path(udev); + + ret = lan78xx_update_flowcontrol(udev, dev); + + return ret; +} + +#ifndef CONFIG_DM_ETH +/* + * lan78xx callbacks + */ +static int lan78xx_init(struct eth_device *eth, bd_t *bd) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct usb_device *udev = dev->pusb_dev; + struct lan7x_private *priv = (struct lan7x_private *)dev->dev_priv; + + return lan78xx_init_common(udev, dev, priv, eth->enetaddr); +} + +static int lan78xx_write_hwaddr(struct eth_device *eth) +{ + struct ueth_data *dev = eth->priv; + struct usb_device *udev = dev->pusb_dev; + struct lan7x_private *priv = dev->dev_priv; + + return lan78xx_write_hwaddr_common(udev, priv, eth->enetaddr); +} + +/* + * Microchip probing functions + */ +void lan78xx_eth_before_probe(void) +{ + curr_eth_dev = 0; +} + +static const struct lan7x_dongle lan78xx_dongles[] = { + {0x0424, 0x7800}, /* LAN7800 USB Ethernet */ + {0x0424, 0x7850}, /* LAN7850 USB Ethernet */ + {0x0000, 0x0000} /* END - Do not remove */ +}; + +/* Probe to see if a new device is actually an Microchip device */ +int lan78xx_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss) +{ + int i; + + /* let's examine the device now */ + + for (i = 0; lan78xx_dongles[i].vendor != 0; i++) { + if (dev->descriptor.idVendor == lan78xx_dongles[i].vendor && + dev->descriptor.idProduct == lan78xx_dongles[i].product) + /* Found a supported dongle */ + break; + } + if (lan78xx_dongles[i].vendor == 0) + return 0; + + /* At this point, we know we've got a live one */ + debug("\n\nUSB Ethernet device LAN78xx detected\n"); + + /* + * Note that this function needs to return 1 + * for success + */ + return lan7x_eth_probe(dev, ifnum, ss); +} + +int lan78xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, + struct eth_device *eth) +{ + struct lan7x_private *priv = ss->dev_priv; + + printf("LAN78xx name: %s%d\n", LAN78XX_BASE_NAME, curr_eth_dev); + + if (!eth) { + debug("%s: missing parameter.\n", __func__); + return 0; + } + sprintf(eth->name, "%s%d", LAN78XX_BASE_NAME, curr_eth_dev++); + eth->init = lan78xx_init; + eth->send = lan7x_send; + eth->recv = lan7x_recv; + eth->halt = lan7x_halt; + eth->write_hwaddr = lan78xx_write_hwaddr; + eth->priv = ss; + + /* Do a reset in order to get the MAC address from HW */ + if (lan78xx_basic_reset(dev, ss, priv)) + return 0; + + /* Get the MAC address */ + /* + * We must set the eth->enetaddr from HW because the upper layer + * will force to use the environmental var (usbethaddr) or random if + * there is no valid MAC address in eth->enetaddr. + */ + lan78xx_read_mac(eth->enetaddr, dev, priv); + /* Do not return 0 for not finding MAC addr in HW */ + + return 1; +} +#endif /* !CONFIG_DM_ETH */ + +#ifdef CONFIG_DM_ETH +static int lan78xx_eth_start(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + + /* Driver-model Ethernet ensures we have this */ + priv->have_hwaddr = 1; + + return lan78xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr); +} + +int lan78xx_write_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct lan7x_private *priv = dev_get_priv(dev); + + return lan78xx_write_hwaddr_common(udev, priv, pdata->enetaddr); +} + +int lan78xx_read_rom_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct lan7x_private *priv = dev_get_priv(dev); + int ret; + + ret = lan78xx_read_mac(pdata->enetaddr, udev, priv); + if (ret) + memset(pdata->enetaddr, 0, 6); + + return 0; +} + +static int lan78xx_eth_probe(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct lan7x_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + struct eth_pdata *pdata = dev_get_platdata(dev); + + /* Do a reset in order to get the MAC address from HW */ + if (lan78xx_basic_reset(udev, ueth, priv)) + return 0; + + /* Get the MAC address */ + /* + * We must set the eth->enetaddr from HW because the upper layer + * will force to use the environmental var (usbethaddr) or random if + * there is no valid MAC address in eth->enetaddr. + */ + lan78xx_read_mac(pdata->enetaddr, udev, priv); + /* Do not return 0 for not finding MAC addr in HW */ + + return usb_ether_register(dev, ueth, RX_URB_SIZE); +} + +static const struct eth_ops lan78xx_eth_ops = { + .start = lan78xx_eth_start, + .send = lan7x_eth_send, + .recv = lan7x_eth_recv, + .free_pkt = lan7x_free_pkt, + .stop = lan7x_eth_stop, + .write_hwaddr = lan78xx_write_hwaddr, + .read_rom_hwaddr = lan78xx_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(lan78xx_eth) = { + .name = "lan78xx_eth", + .id = UCLASS_ETH, + .probe = lan78xx_eth_probe, + .ops = &lan78xx_eth_ops, + .priv_auto_alloc_size = sizeof(struct lan7x_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +static const struct usb_device_id lan78xx_eth_id_table[] = { + { USB_DEVICE(0x0424, 0x7800) }, /* LAN7800 USB Ethernet */ + { USB_DEVICE(0x0424, 0x7850) }, /* LAN7850 USB Ethernet */ + { } /* Terminating entry */ +}; + +U_BOOT_USB_DEVICE(lan78xx_eth, lan78xx_eth_id_table); +#endif diff --git a/drivers/usb/eth/lan7x.c b/drivers/usb/eth/lan7x.c new file mode 100644 index 0000000..baa778f --- /dev/null +++ b/drivers/usb/eth/lan7x.c @@ -0,0 +1,680 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <malloc.h> +#include <memalign.h> +#include <usb.h> +#include <linux/mii.h> +#include <linux/ethtool.h> +#include "usb_ether.h" +#include "lan7x.h" + +/* + * Lan7x infrastructure commands + */ +int lan7x_write_reg(struct usb_device *udev, u32 index, u32 data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); + + cpu_to_le32s(&data); + tmpbuf[0] = data; + + len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + USB_VENDOR_REQUEST_WRITE_REGISTER, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0, index, tmpbuf, sizeof(data), + USB_CTRL_SET_TIMEOUT_MS); + if (len != sizeof(data)) { + debug("%s failed: index=%d, data=%d, len=%d", + __func__, index, data, len); + return -EIO; + } + return 0; +} + +int lan7x_read_reg(struct usb_device *udev, u32 index, u32 *data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); + + len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + USB_VENDOR_REQUEST_READ_REGISTER, + USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0, index, tmpbuf, sizeof(*data), + USB_CTRL_GET_TIMEOUT_MS); + *data = tmpbuf[0]; + if (len != sizeof(*data)) { + debug("%s failed: index=%d, len=%d", __func__, index, len); + return -EIO; + } + + le32_to_cpus(data); + return 0; +} + +/* Loop until the read is completed with timeout */ +int lan7x_wait_for_bit(struct usb_device *udev, + const char *prefix, const u32 index, + const u32 mask, const bool set, + unsigned int timeout_ms) +{ + u32 val; + + while (--timeout_ms) { + lan7x_read_reg(udev, index, &val); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + mdelay(1); + } + + debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", + prefix, index, mask, set); + + return -ETIMEDOUT; +} + +static int lan7x_phy_wait_not_busy(struct usb_device *udev) +{ + return lan7x_wait_for_bit(udev, __func__, + MII_ACC, MII_ACC_MII_BUSY, + false, 100); +} + +int lan7x_mdio_read(struct usb_device *udev, int phy_id, int idx) +{ + u32 val, addr; + + /* confirm MII not busy */ + if (lan7x_phy_wait_not_busy(udev)) { + debug("MII is busy in %s\n", __func__); + return -ETIMEDOUT; + } + + /* set the address, index & direction (read from PHY) */ + addr = (phy_id << 11) | (idx << 6) | + MII_ACC_MII_READ | MII_ACC_MII_BUSY; + lan7x_write_reg(udev, MII_ACC, addr); + + if (lan7x_phy_wait_not_busy(udev)) { + debug("Timed out reading MII reg %02X\n", idx); + return -ETIMEDOUT; + } + + lan7x_read_reg(udev, MII_DATA, &val); + + return (u16) (val & 0xFFFF); +} + +int lan7x_mdio_wait_for_bit(struct usb_device *udev, + const char *prefix, + int phy_id, const u32 index, + const u32 mask, const bool set, + unsigned int timeout_ms) +{ + u32 val; + + while (--timeout_ms) { + val = lan7x_mdio_read(udev, phy_id, index); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + mdelay(1); + } + + debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", + prefix, index, mask, set); + + return -ETIMEDOUT; +} + +void lan7x_mdio_write(struct usb_device *udev, int phy_id, int idx, int regval) +{ + u32 val, addr; + + /* confirm MII not busy */ + if (lan7x_phy_wait_not_busy(udev)) { + debug("MII is busy in %s\n", __func__); + return; + } + + val = regval; + lan7x_write_reg(udev, MII_DATA, val); + + /* set the address, index & direction (write to PHY) */ + addr = (phy_id << 11) | (idx << 6) | + MII_ACC_MII_WRITE | MII_ACC_MII_BUSY; + lan7x_write_reg(udev, MII_ACC, addr); + + if (lan7x_phy_wait_not_busy(udev)) + debug("Timed out writing MII reg %02X\n", idx); +} + +static int lan7x_eeprom_confirm_not_busy(struct usb_device *udev) +{ + return lan7x_wait_for_bit(udev, __func__, + E2P_CMD, E2P_CMD_EPC_BUSY, + false, 100); +} + +static int lan7x_wait_eeprom(struct usb_device *udev) +{ + return lan7x_wait_for_bit(udev, __func__, + E2P_CMD, + (E2P_CMD_EPC_BUSY | E2P_CMD_EPC_TIMEOUT), + false, 100); +} + +static int lan7x_read_eeprom(struct usb_device *udev, + u32 offset, u32 length, u8 *data) +{ + u32 val; + int i, ret; + + ret = lan7x_eeprom_confirm_not_busy(udev); + if (ret) + return ret; + + for (i = 0; i < length; i++) { + val = E2P_CMD_EPC_BUSY | E2P_CMD_EPC_CMD_READ | + (offset & E2P_CMD_EPC_ADDR_MASK); + lan7x_write_reg(udev, E2P_CMD, val); + + ret = lan7x_wait_eeprom(udev); + if (ret) + return ret; + + lan7x_read_reg(udev, E2P_DATA, &val); + data[i] = val & 0xFF; + offset++; + } + + return ret; +} + +/* + * mii_nway_restart - restart NWay (autonegotiation) for this interface + * + * Returns 0 on success, negative on error. + */ +static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev) +{ + int bmcr; + int r = -1; + + /* if autoneg is off, it's an error */ + bmcr = lan7x_mdio_read(udev, dev->phy_id, MII_BMCR); + + if (bmcr & BMCR_ANENABLE) { + bmcr = BMCR_ANENABLE | BMCR_ANRESTART; + lan7x_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr); + r = 0; + } else { + debug("ERROR! phy autoneg is off. BMCR = 0x%04x\n", bmcr); + } + return r; +} + +int lan7x_phy_initialize(struct usb_device *udev, + struct ueth_data *dev) +{ + int r, link_detected; + + lan7x_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET); + r = lan7x_mdio_wait_for_bit(udev, "BMCR_RESET", + dev->phy_id, MII_BMCR, BMCR_RESET, + false, 1000); + + lan7x_mdio_write(udev, dev->phy_id, MII_ADVERTISE, + ADVERTISE_ALL | ADVERTISE_CSMA | + ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); + + lan7x_mdio_write(udev, dev->phy_id, MII_CTRL1000, + ADVERTISE_1000FULL); + + r = mii_nway_restart(udev, dev); + r = lan7x_mdio_wait_for_bit(udev, "BMSR_ANEGCOMPLETE", + dev->phy_id, MII_BMSR, BMSR_ANEGCOMPLETE, + true, PHY_CONNECT_TIMEOUT_MS); + + if (r == 0) { + debug("phy initialised succesfully\n"); + } else { + debug("phy initialised failed id=%d\n", dev->phy_id); + return r; + } + + printf("LAN7x: Waiting for Ethernet connection... "); + r = lan7x_mdio_wait_for_bit(udev, "BMSR_LSTATUS", + dev->phy_id, MII_BMSR, BMSR_LSTATUS, + true, PHY_CONNECT_TIMEOUT_MS); + + if (r < 0) { + printf("unable to connect.\n"); + return -EIO; + } + printf("done.\n"); + + link_detected = lan7x_mdio_read(udev, dev->phy_id, MII_BMSR); + debug("MII_BMSR=0x%04x\n", link_detected); + + return 0; +} + +static int lan7x_mii_get_an(uint32_t advertising_reg) +{ + int advertising = 0; + + if (advertising_reg & LPA_LPACK) + advertising |= ADVERTISED_Autoneg; + if (advertising_reg & ADVERTISE_10HALF) + advertising |= ADVERTISED_10baseT_Half; + if (advertising_reg & ADVERTISE_10FULL) + advertising |= ADVERTISED_10baseT_Full; + if (advertising_reg & ADVERTISE_100HALF) + advertising |= ADVERTISED_100baseT_Half; + if (advertising_reg & ADVERTISE_100FULL) + advertising |= ADVERTISED_100baseT_Full; + + return advertising; +} + +int lan7x_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev, + uint32_t *flow, uint32_t *fct_flow) +{ + uint32_t lcladv, rmtadv, ctrl1000, stat1000; + uint32_t advertising = 0, lp_advertising = 0, nego = 0; + uint32_t duplex = 0; + u8 cap = 0; + + lcladv = lan7x_mdio_read(udev, dev->phy_id, MII_ADVERTISE); + advertising = lan7x_mii_get_an(lcladv); + + rmtadv = lan7x_mdio_read(udev, dev->phy_id, MII_LPA); + lp_advertising = lan7x_mii_get_an(rmtadv); + + ctrl1000 = lan7x_mdio_read(udev, dev->phy_id, MII_CTRL1000); + stat1000 = lan7x_mdio_read(udev, dev->phy_id, MII_STAT1000); + + if (ctrl1000 & ADVERTISE_1000HALF) + advertising |= ADVERTISED_1000baseT_Half; + + if (ctrl1000 & ADVERTISE_1000FULL) + advertising |= ADVERTISED_1000baseT_Full; + + if (stat1000 & LPA_1000HALF) + lp_advertising |= ADVERTISED_1000baseT_Half; + + if (stat1000 & LPA_1000FULL) + lp_advertising |= ADVERTISED_1000baseT_Full; + + nego = advertising & lp_advertising; + + debug("LAN7x linked at "); + + if (nego & (ADVERTISED_1000baseT_Full | ADVERTISED_1000baseT_Half)) { + debug("1000 "); + duplex = !!(nego & ADVERTISED_1000baseT_Full); + + } else if (nego & (ADVERTISED_100baseT_Full | + ADVERTISED_100baseT_Half)) { + debug("100 "); + duplex = !!(nego & ADVERTISED_100baseT_Full); + } else { + debug("10 "); + duplex = !!(nego & ADVERTISED_10baseT_Full); + } + + if (duplex == DUPLEX_FULL) + debug("full dup "); + else + debug("half dup "); + + if (duplex == DUPLEX_FULL) { + if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) { + cap = FLOW_CTRL_TX | FLOW_CTRL_RX; + } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) { + if (lcladv & ADVERTISE_PAUSE_CAP) + cap = FLOW_CTRL_RX; + else if (rmtadv & LPA_PAUSE_CAP) + cap = FLOW_CTRL_TX; + } + debug("TX Flow "); + if (cap & FLOW_CTRL_TX) { + *flow = (FLOW_CR_TX_FCEN | 0xFFFF); + /* set fct_flow thresholds to 20% and 80% */ + *fct_flow = (((MAX_RX_FIFO_SIZE * 2) / (10 * 512)) + & 0x7FUL); + *fct_flow <<= 8UL; + *fct_flow |= (((MAX_RX_FIFO_SIZE * 8) / (10 * 512)) + & 0x7FUL); + debug("EN "); + } else { + debug("DIS "); + } + debug("RX Flow "); + if (cap & FLOW_CTRL_RX) { + *flow |= FLOW_CR_RX_FCEN; + debug("EN"); + } else { + debug("DIS"); + } + } + debug("\n"); + return 0; +} + +int lan7x_read_eeprom_mac(unsigned char *enetaddr, struct usb_device *udev) +{ + int ret; + + memset(enetaddr, 0, 6); + + ret = lan7x_read_eeprom(udev, 0, 1, enetaddr); + + if ((ret == 0) && (enetaddr[0] == EEPROM_INDICATOR)) { + ret = lan7x_read_eeprom(udev, + EEPROM_MAC_OFFSET, ETH_ALEN, + enetaddr); + if ((ret == 0) && is_valid_ethaddr(enetaddr)) { + /* eeprom values are valid so use them */ + debug("MAC address read from EEPROM %pM\n", + enetaddr); + return 0; + } + } + debug("MAC address read from EEPROM invalid %pM\n", enetaddr); + + memset(enetaddr, 0, 6); + return -1; +} + +int lan7x_pmt_phy_reset(struct usb_device *udev, + struct ueth_data *dev) +{ + int ret; + u32 data; + + ret = lan7x_read_reg(udev, PMT_CTL, &data); + ret = lan7x_write_reg(udev, PMT_CTL, data | PMT_CTL_PHY_RST); + if (ret) + return ret; + + /* for LAN7x, we need to check PMT_CTL_READY asserted */ + ret = lan7x_wait_for_bit(udev, "PMT_CTL_PHY_RST", + PMT_CTL, PMT_CTL_PHY_RST, + false, 1000); /* could take over 125mS */ + if (ret) + return ret; + + ret = lan7x_wait_for_bit(udev, "PMT_CTL_READY", + PMT_CTL, PMT_CTL_READY, + true, 1000); + return ret; +} + +int lan7x_basic_reset(struct usb_device *udev, + struct ueth_data *dev) +{ + int ret; + + dev->phy_id = LAN7X_INTERNAL_PHY_ID; /* fixed phy id */ + + ret = lan7x_write_reg(udev, HW_CFG, HW_CFG_LRST); + if (ret) + return ret; + + ret = lan7x_wait_for_bit(udev, "HW_CFG_LRST", + HW_CFG, HW_CFG_LRST, + false, 1000); + if (ret) + return ret; + + ret = lan7x_pmt_phy_reset(udev, dev); + if (ret) + return ret; + + return 0; +} + +int lan7x_send_common(struct ueth_data *dev, void *packet, int length) +{ + int err; + int actual_len; + u32 tx_cmd_a; + u32 tx_cmd_b; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, + PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); + + debug("** %s(), len %d, buf %#x\n", __func__, length, + (unsigned int)(ulong) msg); + if (length > PKTSIZE) + return -ENOSPC; + + /* LAN7x disable all TX offload features for u-boot */ + tx_cmd_a = (u32) (length & TX_CMD_A_LEN_MASK) | TX_CMD_A_FCS; + tx_cmd_b = 0; + cpu_to_le32s(&tx_cmd_a); + cpu_to_le32s(&tx_cmd_b); + + /* prepend cmd_a and cmd_b */ + memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); + memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); + memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, + length); + err = usb_bulk_msg(dev->pusb_dev, + usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), + (void *)msg, + length + sizeof(tx_cmd_a) + + sizeof(tx_cmd_b), + &actual_len, USB_BULK_SEND_TIMEOUT_MS); + debug("Tx: len = %u, actual = %u, err = %d\n", + (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)), + (unsigned int)actual_len, err); + + return err; +} + +int lan7x_recv_common(struct ueth_data *dev) +{ + DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE); + unsigned char *buf_ptr; + int err; + int actual_len = 0; + u32 packet_len = 0; + u32 rx_cmd_a = 0; + + err = usb_bulk_msg(dev->pusb_dev, + usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), + (void *)recv_buf, RX_URB_SIZE, &actual_len, + USB_BULK_RECV_TIMEOUT_MS); + if (actual_len == 0) { + debug("Rx: actual_len = 0\n"); + return -err; + } + + debug("Rx: RX_URB_SIZE = %u, actual = %u, err = %d\n", RX_URB_SIZE, + actual_len, err); + if (err != 0) { + debug("Rx: failed to receive\n"); + return -err; + } + if (actual_len > RX_URB_SIZE) { + debug("Rx: received too many bytes %d\n", actual_len); + return -ENOSPC; + } + + buf_ptr = recv_buf; + + /* + * No multiple Ethernet Frames per USB Packet (MEF) used + * for the U-boot for now. + */ + if (actual_len > 0) { + if (actual_len < sizeof(rx_cmd_a)) { + debug("Rx: incomplete packet length\n"); + return -EIO; + } + memcpy(&rx_cmd_a, buf_ptr, sizeof(rx_cmd_a)); + le32_to_cpus(&rx_cmd_a); + if (rx_cmd_a & RX_CMD_A_RXE) { + debug("Rx: Error header=%#x", rx_cmd_a); + return -EIO; + } + packet_len = (u16) (rx_cmd_a & RX_CMD_A_LEN_MASK); + + if (packet_len > actual_len - sizeof(packet_len)) { + debug("Rx: too large packet: %d\n", packet_len); + return -EIO; + } + + /* + * For LAN7x, the length in command A does not + * include command A, B, and C length. + * So use it as is. + */ + + debug("Rx: cmd_a 0x%08X packet_len %d\n", rx_cmd_a, packet_len); + + /* Notify net stack */ + net_process_received_packet(buf_ptr + 10, packet_len); + } + + return err; +} + +int lan7x_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss) +{ + struct usb_interface *iface; + struct usb_interface_descriptor *iface_desc; + int i; + + iface = &dev->config.if_desc[ifnum]; + iface_desc = &dev->config.if_desc[ifnum].desc; + + memset(ss, '\0', sizeof(struct ueth_data)); + + /* Initialize the ueth_data structure with some useful info */ + ss->ifnum = ifnum; + ss->pusb_dev = dev; + ss->subclass = iface_desc->bInterfaceSubClass; + ss->protocol = iface_desc->bInterfaceProtocol; + + /* + * We are expecting a minimum of 3 endpoints + * - in, out (bulk), and int. + * We will ignore any others. + */ + for (i = 0; i < iface_desc->bNumEndpoints; i++) { + /* is it an BULK endpoint? */ + if ((iface->ep_desc[i].bmAttributes & + USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { + if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) + ss->ep_in = + iface->ep_desc[i].bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK; + else + ss->ep_out = + iface->ep_desc[i].bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK; + } + + /* is it an interrupt endpoint? */ + if ((iface->ep_desc[i].bmAttributes & + USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { + ss->ep_int = iface->ep_desc[i].bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK; + ss->irqinterval = iface->ep_desc[i].bInterval; + } + } + debug("Endpoints In %d Out %d Int %d\n", + ss->ep_in, ss->ep_out, ss->ep_int); + + /* Do some basic sanity checks, and bail if we find a problem */ + if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || + !ss->ep_in || !ss->ep_out || !ss->ep_int) { + debug("Problems with device\n"); + return 0; + } + dev->privptr = (void *)ss; + +#ifndef CONFIG_DM_ETH + /* alloc driver private */ + ss->dev_priv = calloc(1, sizeof(struct lan7x_private)); + if (!ss->dev_priv) + return 0; +#endif + + return 1; +} + +#ifndef CONFIG_DM_ETH +/* + * lan7x callbacks + */ +int lan7x_send(struct eth_device *eth, void *packet, int length) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + + return lan7x_send_common(dev, packet, length); +} + +int lan7x_recv(struct eth_device *eth) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + + return lan7x_recv_common(dev); +} + +void lan7x_halt(struct eth_device *eth) +{ + debug("** %s()\n", __func__); +} +#endif /* !CONFIG_DM_ETH */ + +#ifdef CONFIG_DM_ETH +void lan7x_eth_stop(struct udevice *dev) +{ + debug("** %s()\n", __func__); +} + +int lan7x_eth_send(struct udevice *dev, void *packet, int length) +{ + struct lan7x_private *priv = dev_get_priv(dev); + + return lan7x_send_common(&priv->ueth, packet, length); +} + +int lan7x_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct lan7x_private *priv = dev_get_priv(dev); + + return lan7x_recv_common(&priv->ueth); +} + +int lan7x_free_pkt(struct udevice *dev, uchar *packet, int packet_len) +{ + struct lan7x_private *priv = dev_get_priv(dev); + + packet_len = ALIGN(packet_len, 4); + usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len); + + return 0; +} +#endif /* CONFIG_DM_ETH */ + diff --git a/drivers/usb/eth/lan7x.h b/drivers/usb/eth/lan7x.h new file mode 100644 index 0000000..b5c1b39 --- /dev/null +++ b/drivers/usb/eth/lan7x.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2017 Microchip Technology Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +/* USB Vendor Requests */ +#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 +#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 +#define USB_VENDOR_REQUEST_GET_STATS 0xA2 + +/* Tx Command A */ +#define TX_CMD_A_FCS BIT(22) +#define TX_CMD_A_LEN_MASK 0x000FFFFF + +/* Rx Command A */ +#define RX_CMD_A_RXE BIT(18) +#define RX_CMD_A_LEN_MASK 0x00003FFF + +/* SCSRs */ +#define ID_REV 0x00 +#define ID_REV_CHIP_ID_MASK 0xFFFF0000 +#define ID_REV_CHIP_ID_7500 0x7500 +#define ID_REV_CHIP_ID_7800 0x7800 +#define ID_REV_CHIP_ID_7850 0x7850 + +#define INT_STS 0x0C + +#define HW_CFG 0x010 +#define HW_CFG_LRST BIT(1) + +#define PMT_CTL 0x014 +#define PMT_CTL_PHY_PWRUP BIT(10) +#define PMT_CTL_READY BIT(7) +#define PMT_CTL_PHY_RST BIT(4) + +#define E2P_CMD 0x040 +#define E2P_CMD_EPC_BUSY BIT(31) +#define E2P_CMD_EPC_CMD_READ 0x00000000 +#define E2P_CMD_EPC_TIMEOUT BIT(10) +#define E2P_CMD_EPC_ADDR_MASK 0x000001FF + +#define E2P_DATA 0x044 + +#define RFE_CTL_BCAST_EN BIT(10) +#define RFE_CTL_DA_PERFECT BIT(1) + +#define FCT_RX_CTL_EN BIT(31) + +#define FCT_TX_CTL_EN BIT(31) + +#define MAC_CR 0x100 +#define MAC_CR_ADP BIT(13) +#define MAC_CR_AUTO_DUPLEX BIT(12) +#define MAC_CR_AUTO_SPEED BIT(11) + +#define MAC_RX 0x104 +#define MAC_RX_FCS_STRIP BIT(4) +#define MAC_RX_RXEN BIT(0) + +#define MAC_TX 0x108 +#define MAC_TX_TXEN BIT(0) + +#define FLOW 0x10C +#define FLOW_CR_TX_FCEN BIT(30) +#define FLOW_CR_RX_FCEN BIT(29) + +#define RX_ADDRH 0x118 +#define RX_ADDRL 0x11C + +#define MII_ACC 0x120 +#define MII_ACC_MII_READ 0x00000000 +#define MII_ACC_MII_WRITE 0x00000002 +#define MII_ACC_MII_BUSY BIT(0) + +#define MII_DATA 0x124 + +#define SS_USB_PKT_SIZE 1024 +#define HS_USB_PKT_SIZE 512 +#define FS_USB_PKT_SIZE 64 + +#define MAX_RX_FIFO_SIZE (12 * 1024) +#define MAX_TX_FIFO_SIZE (12 * 1024) +#define DEFAULT_BULK_IN_DELAY 0x0800 + +#define EEPROM_INDICATOR 0xA5 +#define EEPROM_MAC_OFFSET 0x01 + +/* Some extra defines */ +#define LAN7X_INTERNAL_PHY_ID 1 + +#define LAN7X_MAC_RX_MAX_SIZE(mtu) \ + ((mtu) << 16) /**< Max frame size */ +#define LAN7X_MAC_RX_MAX_SIZE_DEFAULT \ + LAN7X_MAC_RX_MAX_SIZE(ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */) + +/* Timeouts */ +#define USB_CTRL_SET_TIMEOUT_MS 5000 +#define USB_CTRL_GET_TIMEOUT_MS 5000 +#define USB_BULK_SEND_TIMEOUT_MS 5000 +#define USB_BULK_RECV_TIMEOUT_MS 5000 +#define TIMEOUT_RESOLUTION_MS 50 +#define PHY_CONNECT_TIMEOUT_MS 5000 + +#define RX_URB_SIZE 2048 + +/* driver private */ +struct lan7x_private { +#ifdef CONFIG_DM_ETH + struct ueth_data ueth; +#endif + int have_hwaddr; /* 1 if we have a hardware MAC address */ + u32 chipid; /* Chip or device ID */ +}; + +#ifndef CONFIG_DM_ETH +struct lan7x_dongle { + unsigned short vendor; + unsigned short product; +}; +#endif + +/* + * Lan7x infrastructure commands + */ +int lan7x_write_reg(struct usb_device *udev, u32 index, u32 data); + +int lan7x_read_reg(struct usb_device *udev, u32 index, u32 *data); + +int lan7x_wait_for_bit(struct usb_device *udev, + const char *prefix, const u32 index, + const u32 mask, const bool set, + const unsigned int timeout_ms); + +int lan7x_mdio_read(struct usb_device *udev, int phy_id, int idx); + +int lan7x_mdio_wait_for_bit(struct usb_device *udev, + const char *prefix, + int phy_id, const u32 index, + const u32 mask, const bool set, + const unsigned int timeout_ms); + +void lan7x_mdio_write(struct usb_device *udev, int phy_id, int idx, + int regval); + +int lan7x_pmt_phy_reset(struct usb_device *udev, + struct ueth_data *dev); + +int lan7x_phy_initialize(struct usb_device *udev, + struct ueth_data *dev); + +int lan7x_update_flowcontrol(struct usb_device *udev, + struct ueth_data *dev, + uint32_t *flow, uint32_t *fct_flow); + +int lan7x_read_eeprom_mac(unsigned char *enetaddr, struct usb_device *udev); + +int lan7x_basic_reset(struct usb_device *udev, + struct ueth_data *dev); + +int lan7x_send_common(struct ueth_data *dev, void *packet, int length); + +int lan7x_recv_common(struct ueth_data *dev); + +int lan7x_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss); + +#ifndef CONFIG_DM_ETH +/* + * lan7x callbacks + */ +int lan7x_send(struct eth_device *eth, void *packet, int length); + +int lan7x_recv(struct eth_device *eth); + +void lan7x_halt(struct eth_device *eth); +#endif /* !CONFIG_DM_ETH */ + +#ifdef CONFIG_DM_ETH +void lan7x_eth_stop(struct udevice *dev); + +int lan7x_eth_send(struct udevice *dev, void *packet, int length); + +int lan7x_eth_recv(struct udevice *dev, int flags, uchar **packetp); + +int lan7x_free_pkt(struct udevice *dev, uchar *packet, int packet_len); +#endif /* CONFIG_DM_ETH */ + diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c index 36734e2..8f4b5e9 100644 --- a/drivers/usb/eth/usb_ether.c +++ b/drivers/usb/eth/usb_ether.c @@ -180,6 +180,20 @@ static const struct usb_eth_prob_dev prob_dev[] = { .get_info = smsc95xx_eth_get_info, }, #endif +#ifdef CONFIG_USB_ETHER_LAN75XX + { + .before_probe = lan75xx_eth_before_probe, + .probe = lan75xx_eth_probe, + .get_info = lan75xx_eth_get_info, + }, +#endif +#ifdef CONFIG_USB_ETHER_LAN78XX + { + .before_probe = lan78xx_eth_before_probe, + .probe = lan78xx_eth_probe, + .get_info = lan78xx_eth_get_info, + }, +#endif #ifdef CONFIG_USB_ETHER_RTL8152 { .before_probe = r8152_eth_before_probe, diff --git a/include/usb_ether.h b/include/usb_ether.h index 51fce4e..1990b0d 100644 --- a/include/usb_ether.h +++ b/include/usb_ether.h @@ -132,6 +132,18 @@ int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, struct eth_device *eth); +void lan75xx_eth_before_probe(void); +int lan75xx_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss); +int lan75xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, + struct eth_device *eth); + +void lan78xx_eth_before_probe(void); +int lan78xx_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss); +int lan78xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, + struct eth_device *eth); + void r8152_eth_before_probe(void); int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum, struct ueth_data *ss); -- 2.7.4

4 10

Re: [U-Boot] i.Mx6q u-boot stuck
by Fabio Estevam 29 May '17

29 May '17

On Mon, Apr 10, 2017 at 5:07 PM, Fausto Sessego <fausto.sessego(a)infomob.it> wrote: > It is right because it is a custom board designed by my self. > > I renamed CONFIG_TARGET_MX6BOARD=y > > Do you have any hint? You can try removing the line ""mmcbooterror=echo Boot from mmc ERROR!!; " from your CONFIG_EXTRA_ENV_SETTINGS.

4 19

[U-Boot] [PATCH v1 0/8] rockchip: mkimage: refactor rksd/rkspi padding calculation and add dumpimage support
by Philipp Tomsich 27 May '17

27 May '17

We support booting both from SD/MMC images and SPI images on the RK3399-Q7 for different use-cases (e.g. external boot in development from the SD card, internal boot from MMC or SPI depending on whether the SPI flash is populated on any given configuration option). In getting the SPI image support ready for production, we found a few areas that warranted improvements: - we had broken SPI bootstrap earlier in the changes introducting boot0-style images for the RK3399 (this needed fixing) - in fixing the broken SPI padding calculation, it became apparent that it's best to refactor and document things before we make the same mistake again in the future - with both SD/MMC and SPI images being used for various purposes by various people, the wrong image style was inadvertendly used in some tests... so we support for 'dumpimage' (i.e. verify_header and print_header) had to be added to quickly check the image type being handled Note that with the refactored calculation of the image-size, we don't pad the image to the maximum SPL size any longer, but pad SD/MMC to the next 512 byte block (RK_BLK_SIZE) and SPI to the next 2K boundary. Philipp Tomsich (8): rockchip: mkimage: rkspi: include the header sector in the SPI size calculation rockchip: mkimage: rewrite padding calculation for SD/MMC and SPI images rockchip: mkimage: Update comments for header size rockchip: mkimage: rksd: pad SD/MMC images to a full blocksize rockchip: mkimage: clarify header0 initialisation rockchip: mkimage: play nice with dumpimage rockchip: mkimage: remove placeholder functions from rkimage rockchip: mkimage: add support for verify_header/print_header tools/rkcommon.c | 195 ++++++++++++++++++++++++++++++++++++++++++++++++++----- tools/rkcommon.h | 29 ++++++++- tools/rkimage.c | 21 +----- tools/rksd.c | 47 +++++--------- tools/rkspi.c | 62 +++++++++--------- 5 files changed, 255 insertions(+), 99 deletions(-) -- 1.9.1

6 29

[U-Boot] [PATCH][v2] board: ls2080ardb, ls2080aqds: Adjust memory map for NOR-boot
by Santan Kumar 25 May '17

25 May '17

This patch adjusts memory map for images on LS2080ARDB, LS2080AQDS as per below memory map for NOR flash: Image Flash Offset RCW+PBI 0x00000000 Boot firmware (U-Boot) 0x00100000 Boot firmware Environment 0x00300000 PPA firmware 0x00400000 PHY firmware 0x00980000 DPAA2 MC 0x00A00000 DPAA2 DPL 0x00D00000 DPAA2 DPC 0x00E00000 Kernel.itb 0x01000000 Signed-off-by: Santan Kumar <santan.kumar(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v2: 1. Rebase on the top of Priyanka's QSPI patch https://patchwork.ozlabs.org/patch/756222/ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 +- board/freescale/ls2080aqds/README | 12 ++++++++++++ board/freescale/ls2080ardb/README | 13 +++++++++++++ include/configs/ls2080a_common.h | 8 ++++---- include/configs/ls2080aqds.h | 8 ++++---- include/configs/ls2080ardb.h | 12 ++++++------ 6 files changed, 40 insertions(+), 15 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index d0770c0..4d82257 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -162,7 +162,7 @@ config SYS_LS_PPA_FW_ADDR depends on FSL_LS_PPA default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT - default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A + default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A default 0x60500000 if SYS_LS_PPA_FW_IN_XIP default 0x500000 if SYS_LS_PPA_FW_IN_MMC default 0x500000 if SYS_LS_PPA_FW_IN_NAND diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 2808bd5..fd0e25a 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -89,6 +89,18 @@ c) NAND boot d) SD boot e) QSPI boot +Memory map for NOR boot +------------------------- +Image Flash Offset +RCW+PBI 0x00000000 +Boot firmware (U-Boot) 0x00100000 +Boot firmware Environment 0x00300000 +PPA firmware 0x00400000 +DPAA2 MC 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + Environment Variables --------------------- - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index 873aadf..0003b45 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -71,6 +71,19 @@ a) NOR boot b) NAND boot c) QSPI boot +Memory map for NOR boot +------------------------- +Image Flash Offset +RCW+PBI 0x00000000 +Boot firmware (U-Boot) 0x00100000 +Boot firmware Environment 0x00300000 +PPA firmware 0x00400000 +Cortina PHY firmware 0x00980000 +DPAA2 MC 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + cfg_rcw_src switches needs to be changed for booting from different option. Refer to board documentation for correct switch setting. diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index cc61af8..dd56114 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -193,18 +193,18 @@ unsigned long long get_qixis_addr(void); "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581200000\0" \ + "kernel_start=0x581000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "console=ttyAMA0,38400n8\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" + "mcinitcmd=fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500 " \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=256" -#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ +#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ " cp.b $kernel_start $kernel_load" \ " $kernel_size && bootm $kernel_load" diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 16ef350..fc52c26 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -274,7 +274,7 @@ unsigned long get_board_ddr_clk(void); #ifndef CONFIG_QSPI_BOOT #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x2000 #endif @@ -386,12 +386,12 @@ unsigned long get_board_ddr_clk(void); "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581100000\0" \ + "kernel_start=0x581000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcmemsize=0x40000000\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" + "mcinitcmd=fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" #endif /* CONFIG_SECURE_BOOT */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index dd72aa0..f61b82f 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -248,7 +248,7 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x2000 #endif @@ -392,13 +392,13 @@ unsigned long get_board_sys_clk(void); "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581100000\0" \ + "kernel_start=0x581000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcmemsize=0x40000000\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" \ + "mcinitcmd=fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" \ BOOTENV #endif #endif @@ -418,7 +418,7 @@ unsigned long get_board_sys_clk(void); " || run distro_bootcmd" #else /* Try to boot an on-NOR kernel first, then do normal distro boot */ -#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \ +#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580d00000" \ " && cp.b $kernel_start $kernel_load $kernel_size" \ " && bootm $kernel_load" \ " || run distro_bootcmd" @@ -434,7 +434,7 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_QSPI_BOOT #define CONFIG_CORTINA_FW_ADDR 0x20980000 #else -#define CONFIG_CORTINA_FW_ADDR 0x581000000 +#define CONFIG_CORTINA_FW_ADDR 0x580980000 #endif #define CONFIG_CORTINA_FW_LENGTH 0x40000 -- 1.9.1

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[U-Boot] [PATCH 1/2][v2] armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support
by Priyanka Jain 25 May '17

25 May '17

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A-72 CPUs and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2081A has one more similar personality which has four CPUs: LS2041A Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Santan Kumar <santan.kumar(a)nxp.com> --- Changes for v2: Uddated copyright arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 +++- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 11 +++++++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 3 +++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++ drivers/pci/pcie_layerscape.c | 7 +++++-- drivers/pci/pcie_layerscape.h | 3 +++ drivers/pci/pcie_layerscape_fixup.c | 7 +++++-- 7 files changed, 33 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c24f3f1..970e759 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ @@ -102,7 +103,8 @@ static void fix_pcie_mmu_map(void) /* Fix PCIE base and size for LS2088A */ if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) || - (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) { + (ver == SVR_LS2048A) || (ver == SVR_LS2044A) || + (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { for (i = 0; i < ARRAY_SIZE(final_map); i++) { switch (final_map[i].phys) { case CONFIG_SYS_PCIE1_PHYS_ADDR: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index c7496c0..3ae16ae 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -5,6 +5,7 @@ SoC overview 3. LS1012A 4. LS1046A 5. LS2088A + 6. LS2081A LS1043A --------- @@ -227,3 +228,13 @@ LS2088A SoC has 3 more similar SoC personalities 3)LS2044A, few difference w.r.t. LS2084A: a) Four 64-bit ARM v8 Cortex-A72 CPUs + +LS2081A +-------- +LS2081A is 40-pin derivative of LS2084A. +So feature-wise it is same as LS2084A. +Refer to LS2084A(LS2088A) section above for details. + +It has one more similar SoC personality +1)LS2041A, few difference w.r.t. LS2081A: + a) Four 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 95c3e2f..d0e42c5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015, Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ @@ -15,6 +16,8 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), + CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), + CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 426fe8e..6ac534e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ @@ -54,6 +55,8 @@ struct cpu_type { #define SVR_LS2084A 0x870910 #define SVR_LS2048A 0x870920 #define SVR_LS2044A 0x870930 +#define SVR_LS2081A 0x870919 +#define SVR_LS2041A 0x870915 #define SVR_DEV_LS2080A 0x8701 diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 1c5a33a..5b5651a 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver * @@ -170,7 +171,8 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie) /* Fix the pcie memory map for LS2088A series SoCs */ svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A) { + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) { if (io) io->phys_start = (io->phys_start & (PCIE_PHYS_SIZE - 1)) + @@ -531,7 +533,8 @@ static int ls_pcie_probe(struct udevice *dev) svr = get_svr(); svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A) { + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) { pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + LS2088A_PCIE_PHYS_SIZE * pcie->idx; pcie->ctrl = pcie->lut + 0x40000; diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index e3324a5..07a7014 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver * @@ -117,6 +118,8 @@ #define SVR_LS2084A 0x870910 #define SVR_LS2048A 0x870920 #define SVR_LS2044A 0x870930 +#define SVR_LS2081A 0x870919 +#define SVR_LS2041A 0x870915 /* LS1021a PCIE space */ #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index d504bbd..f08c152 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver * @@ -82,7 +83,8 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A) + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) compat = "fsl,ls2088a-pcie"; else compat = CONFIG_FSL_PCIE_COMPAT; @@ -217,7 +219,8 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A) + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) compat = "fsl,ls2088a-pcie"; else compat = CONFIG_FSL_PCIE_COMPAT; -- 1.7.4.1

2 4

[U-Boot] [PATCH 1/2][v7] board: freescale: ls2080ardb: Update QIXIS code
by Priyanka Jain 25 May '17

25 May '17

Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS flag is enabled As per board documentation, default sysclk is 100MHz. In case QIXIS code is not enabled, update default sysclk value to 100MHz Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v4: Added changes for default sysclk as 100MHz board/freescale/ls2080ardb/ls2080ardb.c | 21 +++++++++++++++++---- 1 files changed, 17 insertions(+), 4 deletions(-) diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 52adca0..1379b81 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -23,8 +23,10 @@ #include <asm/arch/ppa.h> #include <fsl_sec.h> +#ifdef CONFIG_FSL_QIXIS #include "../common/qixis.h" #include "ls2080ardb_qixis.h" +#endif #include "../common/vid.h" #define PIN_MUX_SEL_SDHC 0x00 @@ -58,12 +60,15 @@ unsigned long long get_qixis_addr(void) int checkboard(void) { +#ifdef CONFIG_FSL_QIXIS u8 sw; +#endif char buf[15]; cpu_name(buf); printf("Board: %s-RDB, ", buf); +#ifdef CONFIG_FSL_QIXIS sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); @@ -79,7 +84,7 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - +#endif puts("SERDES1 Reference : "); printf("Clock1 = 156.25MHz "); printf("Clock2 = 156.25MHz"); @@ -93,6 +98,7 @@ int checkboard(void) unsigned long get_board_sys_clk(void) { +#ifdef CONFIG_FSL_QIXIS u8 sysclk_conf = QIXIS_READ(brdcfg[1]); switch (sysclk_conf & 0x0F) { @@ -111,7 +117,8 @@ unsigned long get_board_sys_clk(void) case QIXIS_SYSCLK_166: return 166666666; } - return 66666666; +#endif + return 100000000; } int select_i2c_ch_pca9547(u8 ch) @@ -134,6 +141,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel) int config_board_mux(int ctrl_type) { +#ifdef CONFIG_FSL_QIXIS u8 reg5; reg5 = QIXIS_READ(brdcfg[5]); @@ -151,7 +159,7 @@ int config_board_mux(int ctrl_type) } QIXIS_WRITE(brdcfg[5], reg5); - +#endif return 0; } @@ -181,8 +189,9 @@ int board_init(void) #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); +#ifdef CONFIG_FSL_QIXIS QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); - +#endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -319,6 +328,7 @@ int ft_board_setup(void *blob, bd_t *bd) void qixis_dump_switch(void) { +#ifdef CONFIG_FSL_QIXIS int i, nr_of_cfgsw; QIXIS_WRITE(cms[0], 0x00); @@ -329,6 +339,7 @@ void qixis_dump_switch(void) QIXIS_WRITE(cms[0], i); printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } +#endif } /* @@ -339,6 +350,7 @@ void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr) { +#ifdef CONFIG_FSL_QIXIS u8 sw; sw = QIXIS_READ(arch); @@ -348,4 +360,5 @@ void update_spd_address(unsigned int ctrl_num, else if (ctrl_num == 1 && slot == 1) *addr = SPD_EEPROM_ADDRESS3; } +#endif } -- 1.7.4.1

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