April 2017 - U-Boot

[U-Boot] [PATCH 1/2][v5] board: freescale: ls2080ardb: Update QIXIS code
by Priyanka Jain 27 Apr '17

27 Apr '17

Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS flag is enabled As per board documentation, default sysclk is 100MHz. In case QIXIS code is not enabled, update default sysclk value to 100MHz Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v4: Added changes for default sysclk as 100MHz board/freescale/ls2080ardb/ls2080ardb.c | 21 +++++++++++++++++---- 1 files changed, 17 insertions(+), 4 deletions(-) diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c2aa101..10e8ea4 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -23,8 +23,10 @@ #include <asm/arch/ppa.h> #include <fsl_sec.h> +#ifdef CONFIG_FSL_QIXIS #include "../common/qixis.h" #include "ls2080ardb_qixis.h" +#endif #include "../common/vid.h" #define PIN_MUX_SEL_SDHC 0x00 @@ -58,12 +60,15 @@ unsigned long long get_qixis_addr(void) int checkboard(void) { +#ifdef CONFIG_FSL_QIXIS u8 sw; +#endif char buf[15]; cpu_name(buf); printf("Board: %s-RDB, ", buf); +#ifdef CONFIG_FSL_QIXIS sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); @@ -79,7 +84,7 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - +#endif puts("SERDES1 Reference : "); printf("Clock1 = 156.25MHz "); printf("Clock2 = 156.25MHz"); @@ -93,6 +98,7 @@ int checkboard(void) unsigned long get_board_sys_clk(void) { +#ifdef CONFIG_FSL_QIXIS u8 sysclk_conf = QIXIS_READ(brdcfg[1]); switch (sysclk_conf & 0x0F) { @@ -111,7 +117,8 @@ unsigned long get_board_sys_clk(void) case QIXIS_SYSCLK_166: return 166666666; } - return 66666666; +#endif + return 100000000; } int select_i2c_ch_pca9547(u8 ch) @@ -134,6 +141,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel) int config_board_mux(int ctrl_type) { +#ifdef CONFIG_FSL_QIXIS u8 reg5; reg5 = QIXIS_READ(brdcfg[5]); @@ -151,7 +159,7 @@ int config_board_mux(int ctrl_type) } QIXIS_WRITE(brdcfg[5], reg5); - +#endif return 0; } @@ -181,8 +189,9 @@ int board_init(void) #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); +#ifdef CONFIG_FSL_QIXIS QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); - +#endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -319,6 +328,7 @@ int ft_board_setup(void *blob, bd_t *bd) void qixis_dump_switch(void) { +#ifdef CONFIG_FSL_QIXIS int i, nr_of_cfgsw; QIXIS_WRITE(cms[0], 0x00); @@ -329,6 +339,7 @@ void qixis_dump_switch(void) QIXIS_WRITE(cms[0], i); printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } +#endif } /* @@ -339,6 +350,7 @@ void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr) { +#ifdef CONFIG_FSL_QIXIS u8 sw; sw = QIXIS_READ(arch); @@ -348,4 +360,5 @@ void update_spd_address(unsigned int ctrl_num, else if (ctrl_num == 1 && slot == 1) *addr = SPD_EEPROM_ADDRESS3; } +#endif } -- 1.7.4.1

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[U-Boot] [PATCH] mmc: sdhci: Fix maximum clock for programmable clock mode
by Wenyou Yang 27 Apr '17

27 Apr '17

In the programmable clock mode, the SDCLK frequency is incorrectly assigned when the maximum clock has been assigned during probe, this causes the SDHCI not work well. In the programmable clock mode, when calculating the SDCLK Frequency Select, when the maximum clock has been assigned, it is the actual value, should not be multiplied by host->clk_mul. Otherwise, the maximum clock is multiplied host->clk_mul by the base clock achieved from the BASECLKF field of the Capabilities 0 Register. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- drivers/mmc/sdhci.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index b745977b3f..161a6b1399 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -332,8 +332,7 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) */ if (host->clk_mul) { for (div = 1; div <= 1024; div++) { - if ((host->max_clk * host->clk_mul / div) - <= clock) + if ((host->max_clk / div) <= clock) break; } @@ -547,6 +546,14 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, #ifndef CONFIG_DM_MMC_OPS cfg->ops = &sdhci_ops; #endif + + /* Check whether the clock multiplier is supported or not */ + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { + caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); + host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> + SDHCI_CLOCK_MUL_SHIFT; + } + if (host->max_clk == 0) { if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> @@ -555,6 +562,8 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; host->max_clk *= 1000000; + if (host->clk_mul) + host->max_clk *= host->clk_mul; } if (host->max_clk == 0) { printf("%s: Hardware doesn't specify base clock frequency\n", @@ -590,11 +599,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { if (!(caps & SDHCI_CAN_DO_8BIT)) cfg->host_caps &= ~MMC_MODE_8BIT; - - /* Find out whether clock multiplier is supported */ - caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); - host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> - SDHCI_CLOCK_MUL_SHIFT; } if (host->host_caps) -- 2.11.0

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[U-Boot] [PATCH] armv8: layerscape: Fix DDR size calcuation for SPL build
by York Sun 27 Apr '17

27 Apr '17

Commit 088454cd dropped return value from initram(), setting gd->ram_size directly. Three boards were missed for SPL boot. Signed-off-by: York Sun <york.sun(a)nxp.com> --- board/freescale/ls1043aqds/ddr.c | 4 +++- board/freescale/ls1046aqds/ddr.c | 4 +++- board/freescale/ls1046ardb/ddr.c | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 2643f5b..b22d378 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -113,7 +113,9 @@ int fsl_initdram(void) phys_size_t dram_size; #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - return fsl_ddr_sdram_size(); + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; #else puts("Initializing DDR....using SPD\n"); diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index d37af34..5fcfa0f 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -97,7 +97,9 @@ int fsl_initdram(void) phys_size_t dram_size; #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - return fsl_ddr_sdram_size(); + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; #else puts("Initializing DDR....using SPD\n"); diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index a16f7bc..ae5046c 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -101,7 +101,9 @@ int fsl_initdram(void) phys_size_t dram_size; #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - return fsl_ddr_sdram_size(); + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; #else puts("Initializing DDR....using SPD\n"); -- 2.7.4

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[U-Boot] [PATCH v3] arm: psci: make psci usable on single core socs
by Yuantian Tang 27 Apr '17

27 Apr '17

PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao(a)nxp.com> Signed-off-by: Tang Yuantian <andy.tang(a)nxp.com> --- v3: - replace printf with debug v2: - refine the title and commit message arch/arm/cpu/armv8/cpu-dt.c | 13 +++------- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 35 ++++++++++++--------------- arch/arm/cpu/armv8/sec_firmware.c | 2 +- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 4 +++ arch/arm/include/asm/armv8/sec_firmware.h | 7 ++++++ 5 files changed, 31 insertions(+), 30 deletions(-) diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 5156a15..e3c8aa2 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -7,25 +7,19 @@ #include <common.h> #include <asm/psci.h> #include <asm/system.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> -#endif +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT int psci_update_dt(void *fdt) { -#ifdef CONFIG_MP -#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) - -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT /* * If the PSCI in SEC Firmware didn't work, avoid to update the * device node of PSCI. But still return 0 instead of an error * number to support detecting PSCI dynamically and then switching * the SMP boot method between PSCI and spin-table. */ - if (sec_firmware_support_psci_version() == 0xffffffff) + if (sec_firmware_support_psci_version() == PSCI_INVALID_VER) return 0; -#endif fdt_psci(fdt); #if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE) @@ -34,7 +28,6 @@ int psci_update_dt(void *fdt) __secure_end - __secure_start); #endif -#endif -#endif return 0; } +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c24f3f1..bb02960 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -15,18 +15,14 @@ #include <asm/arch/soc.h> #include <asm/arch/cpu.h> #include <asm/arch/speed.h> -#ifdef CONFIG_MP #include <asm/arch/mp.h> -#endif #include <efi_loader.h> #include <fm_eth.h> #include <fsl-mc/fsl_mc.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> -#endif #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr.h> #endif @@ -475,13 +471,19 @@ int cpu_eth_init(bd_t *bis) return error; } -int arch_early_init_r(void) +static inline int check_psci(void) { -#ifdef CONFIG_MP - int rv = 1; - u32 psci_ver = 0xffffffff; -#endif + unsigned int psci_ver; + psci_ver = sec_firmware_support_psci_version(); + if (psci_ver == PSCI_INVALID_VER) + return 1; + + return 0; +} + +int arch_early_init_r(void) +{ #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 u32 svr_dev_id; /* @@ -495,18 +497,13 @@ int arch_early_init_r(void) #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) erratum_a009942_check_cpo(); #endif -#ifdef CONFIG_MP -#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ - defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) - /* Check the psci version to determine if the psci is supported */ - psci_ver = sec_firmware_support_psci_version(); -#endif - if (psci_ver == 0xffffffff) { - rv = fsl_layerscape_wake_seconday_cores(); - if (rv) + if (check_psci()) { + debug("PSCI: PSCI does not exist.\n"); + + /* if PSCI does not exist, boot secondary cores here */ + if (fsl_layerscape_wake_seconday_cores()) printf("Did not wake secondary cores\n"); } -#endif #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index ec9cf40..4afa3ad 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -227,7 +227,7 @@ unsigned int sec_firmware_support_psci_version(void) if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) return _sec_firmware_support_psci_version(); - return 0xffffffff; + return PSCI_INVALID_VER; } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index d0832b5..fd3f851 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -31,7 +31,11 @@ extern u64 __spin_table[]; extern u64 __real_cntfrq; extern u64 *secondary_boot_code; extern size_t __secondary_boot_code_size; +#ifdef CONFIG_MP int fsl_layerscape_wake_seconday_cores(void); +#else +static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } +#endif void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); void secondary_boot_func(void); diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h index bcdb1b0..bc1d97d 100644 --- a/arch/arm/include/asm/armv8/sec_firmware.h +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -7,12 +7,19 @@ #ifndef __SEC_FIRMWARE_H_ #define __SEC_FIRMWARE_H_ +#define PSCI_INVALID_VER 0xffffffff + int sec_firmware_init(const void *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *); bool sec_firmware_is_valid(const void *); #ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI unsigned int sec_firmware_support_psci_version(void); unsigned int _sec_firmware_support_psci_version(void); +#else +static inline unsigned int sec_firmware_support_psci_version(void) +{ + return PSCI_INVALID_VER; +} #endif #endif /* __SEC_FIRMWARE_H_ */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2 1/3] fsl-ppa: Kconfig: Support to load PPA hdr from eMMC/SD and NAND Flash
by Sumit Garg 27 Apr '17

27 Apr '17

Add support to load PPA hdr from eMMC/SD and NAND Flash in Kconfig Signed-off-by: Sumit Garg <sumit.garg(a)nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal(a)nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai(a)nxp.com> --- Changes in v2: Changed order of patch 1 & 2. Also moved assignment of ppa_esbc_hdr to CONFIG_SYS_LS_PPA_ESBC_ADDR in XIP space as it's not required in case of SD/NAND. arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9fb76f0..4c9b6ce 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -179,12 +179,22 @@ config SYS_LS_PPA_ESBC_ADDR default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 + default 0x700000 if SYS_LS_PPA_FW_IN_MMC + default 0x700000 if SYS_LS_PPA_FW_IN_NAND help If the PPA header firmware locate at XIP flash, such as NOR or QSPI flash, this address is a directly memory-mapped. If it is in a serial accessed flash, such as NAND and SD card, it is a byte offset. +config LS_PPA_ESBC_HDR_SIZE + hex "Length of PPA ESBC header" + depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP + default 0x2000 + help + Length (in bytes) of PPA ESBC header to be copied from MMC/SD or + NAND to memory to validate PPA image. + endmenu config SYS_FSL_ERRATUM_A010315 -- 1.9.1

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[U-Boot] [PATCH 1/4] fsl-layerscape/ls1043aqds: Integrate FSL PPA
by Zhiqiang Hou 27 Apr '17

27 Apr '17

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> The PPA is a EL3 firmware, which support PSCI, hotplug, power-management features etc. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- board/freescale/ls1043aqds/ls1043aqds.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 6507c09..0a6c3a8 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#include <asm/arch/ppa.h> #include <asm/arch/fdt.h> #include <asm/arch/mmu.h> #include <asm/arch/soc.h> @@ -324,6 +325,10 @@ int board_init(void) config_serdes_mux(); #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + return 0; } -- 2.1.0.27.g96db324

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[U-Boot] [PATCH][v2] board: ls2080ardb: Add phy number for serdes1 protocol 0x4b
by Santan Kumar 27 Apr '17

27 Apr '17

Signed-off-by: Santan Kumar <santan.kumar(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v2: Changed the subject board/freescale/ls2080ardb/eth_ls2080rdb.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 799799c..ba584c8 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -62,6 +62,13 @@ int board_eth_init(bd_t *bis) wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); break; + case 0x4B: + wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); + + break; default: printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n", srds_s1); -- 1.9.1

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[U-Boot] [PATCH 0/2] Rockchip: USB: added usb phy control to support ...2017-04-27 5:19:38
by Ringo 26 Apr '17

26 Apr '17

Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: Dear Friend, Credit card shape USB flash drives, print your photos and information on both sides, as a best Corporate gifts for your clients. Picture show: [...] Content analysis details: (10.3 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 3.6 RCVD_IN_PBL RBL: Received via a relay in Spamhaus PBL [116.25.248.131 listed in zen.spamhaus.org] 2.6 DEAR_FRIEND BODY: Dear Friend? That's not very dear! 0.0 HTML_MESSAGE BODY: HTML included in message 1.1 MIME_HTML_ONLY BODY: Message only has text/html MIME parts 1.6 RCVD_IN_BRBL_LASTEXT RBL: No description available. [116.25.248.131 listed in bb.barracudacentral.org] 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines 0.1 MISSING_MID Missing Message-Id: header 1.3 RDNS_NONE Delivered to internal network by a host with no rDNS The original message was not completely plain text, and may be unsafe to open with some email clients; in particular, it may contain a virus, or confirm that your address can receive spam. If you wish to view it, it may be safer to save it to a file and open it with an editor.

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[U-Boot] [PATCH v3 0/3] DS1307 RTC update
by Chris Packham 26 Apr '17

26 Apr '17

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[U-Boot] regression: setting the rpi mac address stopped working
by Gerd Hoffmann 26 Apr '17

26 Apr '17

Hi, u-boot 2016.11 & newer doesn't set the mac address on my raspberry pi any more, so the linux kernel picks a random mac address. Bisected to this commit: commit b91c6a1209e7da1a7f989d9ac35d0d8be0b7b710 Author: Simon Glass <sjg(a)chromium.org> Date: Wed Oct 5 20:42:11 2016 -0600 Fix return value in trailing_strtoln() This function should return -1 if there is no trailing integer in the string. Instead it returns 0. Fix it by checking for this condition at the start. Signed-off-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> Appearently this change broke fdt_fixup_ethernet(). cheers, Gerd

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