February 2017 - U-Boot

[U-Boot] [PATCH v2 00/63] x86: Add initial support for 64-bit U-Boot
by Simon Glass 03 Apr '17

03 Apr '17

At present U-Boot runs entirely in 32-bit mode on x86, except for the initial switch from 16-bit mode. On 64-bit machines it is possible to run in 64-bit mode. This series starts the process of adding this support. The main benefit of 64-bit mode for a boot loader is direct access to all available memory. There are also more registers, but this makes very little difference. This feature is implemented by putting all of the 32-bit code in an SPL build. SPL then runs through all the init that has to be done in 32-bit mode, changes to 64-bit mode and then jumps to U-Boot proper. Typically the total code size increases slightly. For example, on link in 32-bit mode, U-Boot has around 480KB of code (admittedly with a large number of features enabled). In 64-bit mode, U-Boot falls to around 460KB, but SPL adds another 60KB, for a net increase of 40KB. Partly this is due to code duplication and partly it is due to the worse code density of 64-bit code on x86. Many major features are not implemented yet, for example: - SDRAM sizing - Booting linux - FSP support - EFI support - SCSI device init - Running video ROMs Still, this is a big step forward towards full 64-bit support. To enable it, select CONFIG_X86_RUN_64BIT. This series is available at u-boot-x86/64-working Changes in v2: - Show the error value in spl_spi_load_image() - Move table-related changes from a later patch - Rebase to mainline - Drop the write_smbios_table_wrapper() function - Drop change to gma.c - Output error code values in debug() statements - Fix cast in bd82x6x_video_probe() also - Fix cast in get_guid_hob_data() also - Move table-related changes to an earlier patch - Add the 'val' parameter to longjmp() - Drop patch 'video: Use ulong for video frame buffer address' - Add a new 64-bit link config instead of changing the existing one Simon Glass (63): console: Don't enable CONFIG-CONSOLE_MUX, etc. in SPL spl: spi: Add a debug message if loading fails spl: Makefile: Define SPL_ earlier spl: Allow CPU drivers to be used in SPL spl: Allow PCI drivers to be used in SPL spl: Allow RTC drivers to be used in SPL spl: Allow timer drivers to be used in SPL spl: Allow PCH drivers to be used in SPL spl: Don't create a BSS padding when it is separate x86: Use unsigned long for address in table generation WIP: x86: Update mpspec to build on 64-bit machines x86: Add basic support for U-Boot as a 64-bit EFI application x86: ivybridge: Declare global data where it is used x86: ivybridge: Add more debugging for failures x86: ivybridge: Fix types for 64-bit compilation x86: dts: Mark serial as needed before relocation x86: fsp: Fix cast for 64-bit compilation x86: lib: Fix types and casts for 64-bit compilation x86: Add Kconfig options to build 64-bit U-Boot x86: Kconfig: Add location options for 16/32-bit init x86: Use X86_16BIT_INIT instead of X86_RESET_VECTOR x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR x86: ivybridge: Allow 32-bit init to move to SPL x86: Add 64-bit start-up code x86: board_f: Update init sequence for 64-bit startup x86: board_r: Set the global data pointer after relocation x86: Do relocation before clearing BSS x86: Refactor relocation to prepare for 64-bit x86: Add support for 64-bit relocation x86: Tidy up use of size_t in relocation x86: Add an SPL implementation x86: Move the i386 code into its own directory x86: Add cpu code for x86_64 x86: Support global_data on x86_64 x86: Fix up CONFIG_X86_64 check x86: Add a link script for 64-bit x86 x86: Add a link script for SPL x86: Add SPL build rules for start-up code x86: Fix up byteorder.h for x86_64 x86: Drop flag_is_changable() on x86_64 x86: Fix up type sizes for 64-bit x86: Mention the MRC region in the README x86: ivybridge: Skipt SATA init in SPL x86: ivybridge: Provide a dummy SDRAM init for 64-bit x86: Don't try to run the VGA BIOS in 64-bit mode x86: Don't build call64 and setjmp on 64-bit x86: Don't build cpu files which are not supported on 64-bit x86: Don't build 32-bit efi files on x86_64 x86: Don't try to boot Linux from SPL x86: Drop interrupt support in 64-bit mode x86: Support jumping from SPL to U-Boot x86: Move pirq_routing_table to global_data x86: Move turbo_state to global_data x86: Change irq_already_routed to a local variable x86: Move call64 to the i386 directory x86: Move setjmp to the i386 directory x86: Add a dummy setjmp implementation for x86_64 x86: link: Add a text base for 64-bit U-Boot x86: link: Add SPL declarations to the binman image x86: link: Set up device tree for SPL x86: link: Add build options for SPL x86: Update compile/link flags to support 64-bit U-Boot x86: link: Add a config for 64-bit U-Boot Makefile | 7 +- arch/x86/Kconfig | 85 ++++ arch/x86/Makefile | 9 +- arch/x86/config.mk | 30 +- arch/x86/cpu/Makefile | 24 +- arch/x86/cpu/config.mk | 8 +- arch/x86/cpu/cpu.c | 504 -------------------- arch/x86/cpu/i386/Makefile | 9 + arch/x86/cpu/{ => i386}/call64.S | 3 + arch/x86/cpu/i386/cpu.c | 599 ++++++++++++++++++++++++ arch/x86/cpu/{interrupts.c => i386/interrupt.c} | 6 +- arch/x86/cpu/{ => i386}/setjmp.S | 0 arch/x86/cpu/intel_common/Makefile | 10 +- arch/x86/cpu/irq.c | 14 +- arch/x86/cpu/ivybridge/Makefile | 9 +- arch/x86/cpu/ivybridge/bd82x6x.c | 2 + arch/x86/cpu/ivybridge/cpu.c | 4 +- arch/x86/cpu/ivybridge/lpc.c | 2 + arch/x86/cpu/ivybridge/model_206ax.c | 2 + arch/x86/cpu/ivybridge/northbridge.c | 2 + arch/x86/cpu/ivybridge/sata.c | 4 +- arch/x86/cpu/ivybridge/sdram.c | 37 +- arch/x86/cpu/ivybridge/sdram_nop.c | 29 ++ arch/x86/cpu/start64.S | 39 ++ arch/x86/cpu/turbo.c | 8 +- arch/x86/cpu/u-boot-64.lds | 76 +++ arch/x86/cpu/u-boot-spl.lds | 74 +++ arch/x86/cpu/u-boot.lds | 2 +- arch/x86/cpu/x86_64/Makefile | 6 + arch/x86/cpu/x86_64/cpu.c | 48 ++ arch/x86/cpu/x86_64/interrupts.c | 30 ++ arch/x86/cpu/x86_64/setjmp.c | 20 + arch/x86/dts/chromebook_link.dts | 15 +- arch/x86/dts/serial.dtsi | 1 + arch/x86/dts/u-boot.dtsi | 19 + arch/x86/include/asm/acpi_table.h | 2 +- arch/x86/include/asm/byteorder.h | 17 +- arch/x86/include/asm/cpu.h | 12 + arch/x86/include/asm/fsp/fsp_hob.h | 4 +- arch/x86/include/asm/global_data.h | 8 +- arch/x86/include/asm/mp.h | 3 + arch/x86/include/asm/mpspec.h | 10 +- arch/x86/include/asm/posix_types.h | 5 + arch/x86/include/asm/sfi.h | 2 +- arch/x86/include/asm/spl.h | 8 + arch/x86/include/asm/tables.h | 2 +- arch/x86/include/asm/types.h | 5 + arch/x86/lib/Makefile | 11 + arch/x86/lib/acpi_table.c | 4 +- arch/x86/lib/bios.c | 4 +- arch/x86/lib/bootm.c | 2 + arch/x86/lib/elf_x86_64_efi.lds | 3 + arch/x86/lib/init_helpers.c | 2 +- arch/x86/lib/interrupts.c | 5 + arch/x86/lib/mpspec.c | 14 +- arch/x86/lib/pinctrl_ich6.c | 2 +- arch/x86/lib/pirq_routing.c | 14 +- arch/x86/lib/reloc_x86_64.c | 90 ++++ arch/x86/lib/relocate.c | 102 +++- arch/x86/lib/sfi.c | 6 +- arch/x86/lib/spl.c | 149 ++++++ arch/x86/lib/tables.c | 11 +- arch/x86/lib/zimage.c | 2 +- board/google/Kconfig | 7 + board/google/chromebook_link/Kconfig | 5 +- board/google/chromebook_link/MAINTAINERS | 7 + common/board_f.c | 14 +- common/board_r.c | 5 + common/console.c | 30 +- common/spl/Kconfig | 47 ++ common/spl/spl_spi.c | 5 +- configs/chromebook_link64_defconfig | 94 ++++ configs/chromebook_link_defconfig | 23 +- doc/README.x86 | 1 + drivers/Makefile | 5 + drivers/misc/qfw.c | 4 +- drivers/pci/pci_rom.c | 2 +- drivers/video/ivybridge_igd.c | 6 +- include/configs/chromebook_link.h | 9 + include/smbios.h | 4 +- lib/smbios.c | 22 +- scripts/Makefile.spl | 18 +- 82 files changed, 1871 insertions(+), 673 deletions(-) create mode 100644 arch/x86/cpu/i386/Makefile rename arch/x86/cpu/{ => i386}/call64.S (98%) create mode 100644 arch/x86/cpu/i386/cpu.c rename arch/x86/cpu/{interrupts.c => i386/interrupt.c} (99%) rename arch/x86/cpu/{ => i386}/setjmp.S (100%) create mode 100644 arch/x86/cpu/ivybridge/sdram_nop.c create mode 100644 arch/x86/cpu/start64.S create mode 100644 arch/x86/cpu/u-boot-64.lds create mode 100644 arch/x86/cpu/u-boot-spl.lds create mode 100644 arch/x86/cpu/x86_64/Makefile create mode 100644 arch/x86/cpu/x86_64/cpu.c create mode 100644 arch/x86/cpu/x86_64/interrupts.c create mode 100644 arch/x86/cpu/x86_64/setjmp.c create mode 100644 arch/x86/include/asm/spl.h create mode 100644 arch/x86/lib/reloc_x86_64.c create mode 100644 arch/x86/lib/spl.c create mode 100644 configs/chromebook_link64_defconfig -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v3] spi: ich: Configure SPI BIOS parameters
by Stefan Roese 01 Apr '17

01 Apr '17

Without configuring these registers in the SPI controller, the Linux MTD device driver is not able to correctly read/write to the SPI NOR chip at all. In fact, the chip is not detected at all. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Jagan Teki <jteki(a)openedev.com> --- v3: - Moved defines from C-file into header file - Changed some enum's into macros in ich.h for consistency - Used these newly introduced defines v2: - Moved code into the ICH SPI driver as suggested by Simon and Bin drivers/spi/ich.c | 18 ++++++++++++++++++ drivers/spi/ich.h | 45 ++++++++++++++++++++++++++++++++++++++------- 2 files changed, 56 insertions(+), 7 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index caf0103dc3..0418455a79 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -111,6 +111,17 @@ static int ich9_can_do_33mhz(struct udevice *dev) return speed == 1; } +/* + * Configure SPI controller so that the Linux MTD driver can fully + * access the SPI NOR chip + */ +static void spi_controller_config(struct ich_spi_priv *ctlr) +{ + ich_writew(ctlr, SPI_OPTYPE, ctlr->optype); + ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu); + ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); +} + static int ich_init_controller(struct udevice *dev, struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) @@ -172,6 +183,13 @@ static int ich_init_controller(struct udevice *dev, ich_set_bbar(ctlr, 0); + /* + * Configure the SPI-NOR controller in a way that the Linux + * MTD SPI-NOR device driver has full read-write access to + * the SPI-NOR chips + */ + spi_controller_config(ctlr); + return 0; } diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index bd0a820809..7282181247 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -102,13 +102,6 @@ enum { }; enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -enum { ICH_MAX_CMD_LEN = 5, }; @@ -127,6 +120,44 @@ struct spi_trans { #define SPI_OPCODE_WREN 0x06 #define SPI_OPCODE_FAST_READ 0x0b +#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 +#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 +#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 +#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 + +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 SPI_OPCODE_TYPE_READ_WITH_ADDRESS + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 SPI_OPCODE_TYPE_READ_NO_ADDRESS + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 SPI_OPCODE_TYPE_READ_NO_ADDRESS + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 SPI_OPCODE_TYPE_READ_WITH_ADDRESS + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) + enum ich_version { ICHV_7, ICHV_9, -- 2.11.1

3 7

[U-Boot] [PATCH 00/22] dm: Add support for a 'live' device tree
by Simon Glass 01 Apr '17

01 Apr '17

So far U-Boot uses a 'flat' device tree, which means that it is decoded on the fly as needed. This uses the libfdt library and avoids needing extra memory for additional tables. For some time there has been discussion about moving U-Boot to use a 'live' tree, where the device tree is decoded at start-up into a set of hierarchical structures with pointers. The advantages are: - It is somewhat faster to access (in particular scanning and looking for a parent) - It permits the device tree to be changed at run-time (this is not recommended at present since devices store the offset of their device tree node and updating the tree may invalidate that). This could be useful for overlays, for example. - It allows nodes to be referenced by a single pointer, instead of the current device tree pointer plus offset The disadvantages are: - It requires more memory - It takes (a little) time to build the live tree - It adds more complexity under the hood, including an additional abstraction layer This series is an attempt to introduce a useful live tree feature into U-Boot. There are many options and trade-offs. This series is the culmination of quite a bit of thought and experimentation. The approach used in this series is: - Before relocation the flat tree is used, to avoid extra memory usage and time. In general, there is not much access before relocation since most drivers are not started up. So there is little benefit in having a live tree - After relocation the live tree is built. At this point the CPU should be running quickly and there is plenty of memory. All available devices will be bound so the overhead of building the live tree may be outweighed by its greater efficiency. As a simplification, this series supports only one tree or the other. When the live tree is active, the flat tree cannot be used. That makes it easy to know the current state and avoids confusion over mixing offset and node pointers. Some drivers will need to be used both before and after relocation. This means that they must support both the flat and the live tree. To support this, the concept of a node 'reference' is defined. A reference can hold either a node offset (for the flat tree) or a node pointer (for the live tree). This allows drivers to access values from the tree regardless of which tree is in use. In addition, since most device tree access happens in the context of a device (struct udevice), a new 'dev_read' layer is provided to read device tree configuration associated with a device. This encapsulates the details of exactly how this information is read. I have taken the view that code compatibility with Linux is desirable. So the of_access.c file brings in code from Linux with very little modification. As new access methods are needed we should be able to bring in more code and avoid writing it ourselves in U-Boot. Conversion of drivers and subsystems to support the live tree (as well as flat tree) is fairly easy. A patch is included to add support to the GPIO uclass, and the cros_ec device is converted over to provide a driver example. Once I have comments on this series I will update it to build for all boards, to pass current tests and to tidy up the code. I will also add tests for the live tree and finish conversion for sandbox. So for now I am just looking for high-level comments, rather than a detailed code review. Simon Glass (22): dm: core: Set return value first in lists_bind_fdt() dm: core: atmel: Dont export dm_scan_fdt_node() Update WARN_ON() to return a value dm: Add livetree definitions dm: Add livetree access functions dm: Add a function to create a 'live' device tree dm: Build a live tree after relocation dm: Add support for device tree references dm: Add a place to put extra device-tree reading functions dm: core: Add device-based functions to access DT properties dm: core: Allow binding a device from a live tree dm: core: Add a method to find a driver for a livetree node dm: core: Scan the live tree when setting up driver model dm: core: Add a way to find a device by its live-tree node dm: core: Add a way to find a device by node reference dm: gpio: Refactor to prepare for live tree support dm: gpio: Add live tree support dm: gpio: Drop blank line in gpio_xlate_offs_flags() comment dm: gpio: sandbox: Use dm_read...() functions to access DT cros_ec: Fix debug() statement in ec_command_inptr() cros_ec: Convert to support live tree sandbox: Move to use live tree common/board_r.c | 12 ++ configs/sandbox_defconfig | 1 + drivers/core/Makefile | 1 + drivers/core/device.c | 27 +++- drivers/core/lists.c | 80 +++++++++- drivers/core/of_dev.c | 55 +++++++ drivers/core/of_extra.c | 37 +++++ drivers/core/of_ref.c | 218 +++++++++++++++++++++++++ drivers/core/root.c | 61 ++++++- drivers/core/uclass.c | 78 +++++++++ drivers/gpio/atmel_pio4.c | 3 +- drivers/gpio/gpio-uclass.c | 100 ++++++++---- drivers/gpio/sandbox.c | 10 +- drivers/misc/cros_ec.c | 36 ++--- drivers/misc/cros_ec_sandbox.c | 2 +- dts/Kconfig | 11 ++ include/asm-generic/global_data.h | 3 + include/asm-generic/gpio.h | 7 +- include/cros_ec.h | 8 +- include/dm/device-internal.h | 6 + include/dm/device.h | 19 ++- include/dm/lists.h | 5 + include/dm/of.h | 53 ++++++ include/dm/of_access.h | 164 +++++++++++++++++++ include/dm/of_dev.h | 68 ++++++++ include/dm/of_extra.h | 46 ++++++ include/dm/of_ref.h | 306 +++++++++++++++++++++++++++++++++++ include/dm/root.h | 16 -- include/dm/uclass-internal.h | 22 +++ include/dm/uclass.h | 23 +++ include/fdtdec.h | 34 ---- include/linux/compat.h | 8 +- include/livetree.h | 24 +++ lib/Makefile | 1 + lib/fdtdec.c | 32 ---- lib/livetree.c | 320 +++++++++++++++++++++++++++++++++++++ lib/of_access.c | 328 ++++++++++++++++++++++++++++++++++++++ 37 files changed, 2066 insertions(+), 159 deletions(-) create mode 100644 drivers/core/of_dev.c create mode 100644 drivers/core/of_extra.c create mode 100644 drivers/core/of_ref.c create mode 100644 include/dm/of.h create mode 100644 include/dm/of_access.h create mode 100644 include/dm/of_dev.h create mode 100644 include/dm/of_extra.h create mode 100644 include/dm/of_ref.h create mode 100644 include/livetree.h create mode 100644 lib/livetree.c create mode 100644 lib/of_access.c -- 2.11.0.483.g087da7b7c-goog

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[U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus
by Ashish Kumar 28 Mar '17

28 Mar '17

CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new CONFIG defination and move existing register space definaton of CCI-400 bus from from immap_lsch2 to fsl_immap, so that it can be used for both chasis 2 and chasis 3. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- v2: Add new Kconfig in alphabetic order README | 9 ++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 48 -------------------- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + include/fsl_immap.h | 51 ++++++++++++++++++++++ 7 files changed, 69 insertions(+), 48 deletions(-) diff --git a/README b/README index 4f0dbd4..34f5bd3 100644 --- a/README +++ b/README @@ -315,6 +315,15 @@ Many of the options are named exactly as the corresponding Linux kernel configuration options. The intention is to make it easier to build a config tool - later. +- ARM Platform Bus Type(CCI): + CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which + provides full cache coherency between two clusters of multi-core + CPUs and I/O coherency for devices and I/O masters + + CONFIG_SYS_FSL_HAS_CCI400 + + Defined For SoC that has cache coherent interconnect + CCN-400 The following options need to be configured: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index adccdf1..64fae17 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -7,6 +7,7 @@ config ARCH_LS1012A select SYS_FSL_ERRATUM_A010315 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_FSL_HAS_CCI400 config ARCH_LS1043A bool @@ -26,6 +27,7 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_FSL_HAS_CCI400 config ARCH_LS1046A bool @@ -45,6 +47,7 @@ config ARCH_LS1046A select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_FSL_HAS_CCI400 config ARCH_LS2080A bool @@ -182,6 +185,9 @@ config SYS_FSL_IFC_BANK_COUNT default 4 if ARCH_LS1046A default 8 if ARCH_LS2080A +config SYS_FSL_HAS_CCI400 + bool + config SYS_FSL_HAS_DP_DDR bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 335f225..a1ac4a0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -29,6 +29,7 @@ #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr.h> #endif +#include <fsl_immap.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 9489f85..d64fe7b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <fsl_immap.h> #include <fsl_ifc.h> #include <ahci.h> #include <scsi.h> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f..5210b8c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -543,54 +543,6 @@ struct ccsr_serdes { u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ }; -#define CCI400_CTRLORD_TERM_BARRIER 0x00000008 -#define CCI400_CTRLORD_EN_BARRIER 0 -#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 -#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 -#define CCI400_SNOOP_REQ_EN 0x00000001 - -/* CCI-400 registers */ -struct ccsr_cci400 { - u32 ctrl_ord; /* Control Override */ - u32 spec_ctrl; /* Speculation Control */ - u32 secure_access; /* Secure Access */ - u32 status; /* Status */ - u32 impr_err; /* Imprecise Error */ - u8 res_14[0x100 - 0x14]; - u32 pmcr; /* Performance Monitor Control */ - u8 res_104[0xfd0 - 0x104]; - u32 pid[8]; /* Peripheral ID */ - u32 cid[4]; /* Component ID */ - struct { - u32 snoop_ctrl; /* Snoop Control */ - u32 sha_ord; /* Shareable Override */ - u8 res_1008[0x1100 - 0x1008]; - u32 rc_qos_ord; /* read channel QoS Value Override */ - u32 wc_qos_ord; /* read channel QoS Value Override */ - u8 res_1108[0x110c - 0x1108]; - u32 qos_ctrl; /* QoS Control */ - u32 max_ot; /* Max OT */ - u8 res_1114[0x1130 - 0x1114]; - u32 target_lat; /* Target Latency */ - u32 latency_regu; /* Latency Regulation */ - u32 qos_range; /* QoS Range */ - u8 res_113c[0x2000 - 0x113c]; - } slave[5]; /* Slave Interface */ - u8 res_6000[0x9004 - 0x6000]; - u32 cycle_counter; /* Cycle counter */ - u32 count_ctrl; /* Count Control */ - u32 overflow_status; /* Overflow Flag Status */ - u8 res_9010[0xa000 - 0x9010]; - struct { - u32 event_select; /* Event Select */ - u32 event_count; /* Event Count */ - u32 counter_ctrl; /* Counter Control */ - u32 overflow_status; /* Overflow Flag Status */ - u8 res_a010[0xb000 - 0xa010]; - } pcounter[4]; /* Performance Counter */ - u8 res_e004[0x10000 - 0xe004]; -}; - /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) #define SMMU_SCR1 (SMMU_BASE + 0x4) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 0678fba..04add3b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -10,6 +10,7 @@ #define __ARCH_FSL_LSCH3_IMMAP_H_ #define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x3090000) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 diff --git a/include/fsl_immap.h b/include/fsl_immap.h index b1c4fe7..4f5a19c 100644 --- a/include/fsl_immap.h +++ b/include/fsl_immap.h @@ -133,4 +133,55 @@ struct ccsr_ddr { u8 res_e5c[164]; u32 debug[64]; /* debug_1 to debug_64 */ }; + +#ifdef CONFIG_SYS_FSL_HAS_CCI400 +#define CCI400_CTRLORD_TERM_BARRIER 0x00000008 +#define CCI400_CTRLORD_EN_BARRIER 0 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 + +/* CCI-400 registers */ +struct ccsr_cci400 { + u32 ctrl_ord; /* Control Override */ + u32 spec_ctrl; /* Speculation Control */ + u32 secure_access; /* Secure Access */ + u32 status; /* Status */ + u32 impr_err; /* Imprecise Error */ + u8 res_14[0x100 - 0x14]; + u32 pmcr; /* Performance Monitor Control */ + u8 res_104[0xfd0 - 0x104]; + u32 pid[8]; /* Peripheral ID */ + u32 cid[4]; /* Component ID */ + struct { + u32 snoop_ctrl; /* Snoop Control */ + u32 sha_ord; /* Shareable Override */ + u8 res_1008[0x1100 - 0x1008]; + u32 rc_qos_ord; /* read channel QoS Value Override */ + u32 wc_qos_ord; /* read channel QoS Value Override */ + u8 res_1108[0x110c - 0x1108]; + u32 qos_ctrl; /* QoS Control */ + u32 max_ot; /* Max OT */ + u8 res_1114[0x1130 - 0x1114]; + u32 target_lat; /* Target Latency */ + u32 latency_regu; /* Latency Regulation */ + u32 qos_range; /* QoS Range */ + u8 res_113c[0x2000 - 0x113c]; + } slave[5]; /* Slave Interface */ + u8 res_6000[0x9004 - 0x6000]; + u32 cycle_counter; /* Cycle counter */ + u32 count_ctrl; /* Count Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_9010[0xa000 - 0x9010]; + struct { + u32 event_select; /* Event Select */ + u32 event_count; /* Event Count */ + u32 counter_ctrl; /* Counter Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_a010[0xb000 - 0xa010]; + } pcounter[4]; /* Performance Counter */ + u8 res_e004[0x10000 - 0xe004]; +}; +#endif + #endif /* __FSL_IMMAP_H */ -- 1.9.1

2 6

[U-Boot] [PATCH v2 0/2] Add support for only one CS in fsl Quad SPI
by Suresh Gupta 28 Mar '17

28 Mar '17

SOC’s like LS1012A has only one chip select signal out to connect with flash and the 64M flash is attached to it. On boards the same CS is connected to different flash via mux. So at one time only one flash is active and it is not possible to scan other flash at run time. Suresh Gupta (2): spi: fsl_qspi: Add support for one chip select armv8: dts: fsl-ls1012a: Change number of CS in SPI node arch/arm/dts/fsl-ls1012a.dtsi | 2 +- drivers/spi/fsl_qspi.c | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) -- 1.9.3

3 6

[U-Boot] [PATCH v2] armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding
by Ashish Kumar 28 Mar '17

28 Mar '17

From: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> SerDes information is not necessary to be present in RCWSR29 register. It may vary from SoC to SoC. So Avoid RCWSR28 register hard-coding. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- v2: Incorporate York's Review comments .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 28 ++++++++++++---------- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++++++ 2 files changed, 25 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index c2fc646..955e0b7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -51,20 +51,22 @@ int is_serdes_configured(enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 cfg = gur_in32(&gur->rcwsr[28]); + u32 cfg = 0; int i; switch (sd) { #ifdef CONFIG_SYS_FSL_SRDS_1 case FSL_SRDS_1: - cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; break; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 case FSL_SRDS_2: - cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT; break; #endif default: @@ -83,8 +85,8 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) return -ENODEV; } -void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, - u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) +void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, + u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 cfg; @@ -95,7 +97,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); - cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; + cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask; cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); @@ -152,15 +154,17 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, + FSL_CHASSIS3_SRDS1_REGSR, + FSL_CHASSIS3_SRDS1_PRTCL_MASK, + FSL_CHASSIS3_SRDS1_PRTCL_SHIFT, serdes1_prtcl_map); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 serdes_init(FSL_SRDS_2, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, + FSL_CHASSIS3_SRDS2_REGSR, + FSL_CHASSIS3_SRDS2_PRTCL_MASK, + FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 43ae686..0678fba 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -232,10 +232,19 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +#if defined(CONFIG_ARCH_LS2080A) #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#endif #define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_MASK 0x00000400 -- 1.9.1

2 2

[U-Boot] [PATCH v2] arm: fsl-layerscape: Move QSGMII wriop_init to SoC file
by Ashish Kumar 28 Mar '17

28 Mar '17

From: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> MAC number used per QSGMII is not fixed. It may wary from SoC to SoC. So move QSGMII wriop_init_dpmac() to SoC file. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- v2: Incorporate York's Review comments .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 25 +++++------------- .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 8 +++--- drivers/net/ldpaa_eth/ls2080a.c | 30 ++++++++++++++++++++++ include/fsl-mc/ldpaa_wriop.h | 1 + 4 files changed, 41 insertions(+), 23 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 7faa86c..c2fc646 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -23,6 +23,11 @@ int xfi_dpmac[XFI8 + 1]; int sgmii_dpmac[SGMII16 + 1]; #endif +__weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) +{ + return; +} + int is_serdes_configured(enum srds_prtcl device) { int ret = 0; @@ -106,28 +111,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, #ifdef CONFIG_FSL_MC_ENET switch (lane_prtcl) { case QSGMII_A: - wriop_init_dpmac(sd, 5, (int)lane_prtcl); - wriop_init_dpmac(sd, 6, (int)lane_prtcl); - wriop_init_dpmac(sd, 7, (int)lane_prtcl); - wriop_init_dpmac(sd, 8, (int)lane_prtcl); - break; case QSGMII_B: - wriop_init_dpmac(sd, 1, (int)lane_prtcl); - wriop_init_dpmac(sd, 2, (int)lane_prtcl); - wriop_init_dpmac(sd, 3, (int)lane_prtcl); - wriop_init_dpmac(sd, 4, (int)lane_prtcl); - break; case QSGMII_C: - wriop_init_dpmac(sd, 13, (int)lane_prtcl); - wriop_init_dpmac(sd, 14, (int)lane_prtcl); - wriop_init_dpmac(sd, 15, (int)lane_prtcl); - wriop_init_dpmac(sd, 16, (int)lane_prtcl); - break; case QSGMII_D: - wriop_init_dpmac(sd, 9, (int)lane_prtcl); - wriop_init_dpmac(sd, 10, (int)lane_prtcl); - wriop_init_dpmac(sd, 11, (int)lane_prtcl); - wriop_init_dpmac(sd, 12, (int)lane_prtcl); + wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl); break; default: if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index d9d948e..70181c5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -48,10 +48,10 @@ enum srds_prtcl { SGMII14, SGMII15, SGMII16, - QSGMII_A, /* A indicates MACs 1-4 */ - QSGMII_B, /* B indicates MACs 5-8 */ - QSGMII_C, /* C indicates MACs 9-12 */ - QSGMII_D, /* D indicates MACs 12-16 */ + QSGMII_A, + QSGMII_B, + QSGMII_C, + QSGMII_D, SERDES_PRCTL_COUNT }; diff --git a/drivers/net/ldpaa_eth/ls2080a.c b/drivers/net/ldpaa_eth/ls2080a.c index 93ed4f1..673e428 100644 --- a/drivers/net/ldpaa_eth/ls2080a.c +++ b/drivers/net/ldpaa_eth/ls2080a.c @@ -79,3 +79,33 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) return PHY_INTERFACE_MODE_NONE; } + +void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) +{ + switch (lane_prtcl) { + case QSGMII_A: + wriop_init_dpmac(sd, 5, (int)lane_prtcl); + wriop_init_dpmac(sd, 6, (int)lane_prtcl); + wriop_init_dpmac(sd, 7, (int)lane_prtcl); + wriop_init_dpmac(sd, 8, (int)lane_prtcl); + break; + case QSGMII_B: + wriop_init_dpmac(sd, 1, (int)lane_prtcl); + wriop_init_dpmac(sd, 2, (int)lane_prtcl); + wriop_init_dpmac(sd, 3, (int)lane_prtcl); + wriop_init_dpmac(sd, 4, (int)lane_prtcl); + break; + case QSGMII_C: + wriop_init_dpmac(sd, 13, (int)lane_prtcl); + wriop_init_dpmac(sd, 14, (int)lane_prtcl); + wriop_init_dpmac(sd, 15, (int)lane_prtcl); + wriop_init_dpmac(sd, 16, (int)lane_prtcl); + break; + case QSGMII_D: + wriop_init_dpmac(sd, 9, (int)lane_prtcl); + wriop_init_dpmac(sd, 10, (int)lane_prtcl); + wriop_init_dpmac(sd, 11, (int)lane_prtcl); + wriop_init_dpmac(sd, 12, (int)lane_prtcl); + break; + } +} diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h index 6dc159d..8ae0fc0 100644 --- a/include/fsl-mc/ldpaa_wriop.h +++ b/include/fsl-mc/ldpaa_wriop.h @@ -68,4 +68,5 @@ phy_interface_t wriop_get_enet_if(int); void wriop_dpmac_disable(int); void wriop_dpmac_enable(int); phy_interface_t wriop_dpmac_enet_if(int, int); +void wriop_init_dpmac_qsgmii(int, int); #endif /* __LDPAA_WRIOP_H */ -- 1.9.1

2 1

[U-Boot] [PATCH] armv8/fsl-layerscape: Update erratum A009635 implementation
by Priyanka Jain 28 Mar '17

28 Mar '17

Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check for execution Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 335f225..99ac374 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -405,7 +405,14 @@ int arch_early_init_r(void) #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 - erratum_a009635(); + u32 svr_dev_id; + /* + * erratum A009635 is valid only for LS2080A SoC and + * its personalitiesi + */ + svr_dev_id = get_svr() >> 16; + if (svr_dev_id == SVR_DEV_LS2080A) + erratum_a009635(); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) erratum_a009942_check_cpo(); -- 1.7.4.1

2 1

[U-Boot] [PATCH] pci: layerscape: enable PCIe config ready
by Zhiqiang Hou 28 Mar '17

28 Mar '17

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> In EP mode, to enable accesses from the Root Complex, the CONFIG_READY bit must be set, otherwise any config attempts from the Root Complex will be returned with config retry status (CRS). Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian(a)nxp.com> --- drivers/pci/pcie_layerscape.c | 7 +++++++ drivers/pci/pcie_layerscape.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 90b9fe2..e597a75 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -409,6 +409,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base) ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); } +static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) +{ + ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG); +} + static void ls_pcie_setup_ep(struct ls_pcie *pcie) { u32 sriov; @@ -432,6 +437,8 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie) ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); ls_pcie_ep_setup_atu(pcie); } + + ls_pcie_ep_enable_cfg(pcie); } static int ls_pcie_probe(struct udevice *dev) diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 1e635ef..0f9d2fe6 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -94,8 +94,10 @@ #define PCIE_LUT_ENTRY_COUNT 32 /* PF Controll registers */ +#define PCIE_PF_CONFIG 0x14 #define PCIE_PF_VF_CTRL 0x7F8 #define PCIE_PF_DBG 0x7FC +#define PCIE_CONFIG_READY (1 << 0) #define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx)) #define PCIE_SYS_BASE_ADDR 0x3400000 -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH v2 1/1] Secure Boot: Enable IE (Key extention) Feature
by Udit Agarwal 28 Mar '17

28 Mar '17

For validating images from uboot (Such as Kernel Image), either keys from SoC fuses can be used or keys from a verified table of public keys can be used. The latter feature is called IE Key Extension Feature. For Layerscape Chasis 3 based platforms, IE table is validated by Bootrom and address of this table is written in scratch registers 13 and 14 via PBI commands. Following are the steps describing usage of this feature: 1) Verify IE Table in ISBC phase using keys stored in fuses. 2) Install IE table. (To be used across verification of multiple images stored in a static global structure.) 3) Use keys from IE table, to verify further images. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)nxp.com> Signed-off-by: Saksham Jain <saksham.jain(a)nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal(a)nxp.com> --- Changes for V2 Adds more clarity in subject and description related to this feature. --- arch/arm/include/asm/fsl_secure_boot.h | 6 +-- board/freescale/common/fsl_validate.c | 88 +++++++++++++++++++++++++++------- include/fsl_validate.h | 24 +++++++++- 3 files changed, 97 insertions(+), 21 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 27cf096..a612b7d 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -51,11 +51,11 @@ * in boot ROM of the SoC. * The feature is only applicable in case of NOR boot and is * not applicable in case of RAMBOOT (NAND, SD, SPI). + * For LS, this feature is available for all device if IE Table + * is copied to XIP memory + * Also, for LS, ISBC doesn't verify this table. */ -#ifndef CONFIG_ESBC_HDR_LS -/* Current Key EXT feature not available in LS ESBC Header */ #define CONFIG_FSL_ISBC_KEY_EXT -#endif #endif diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 2b723a4..7396aa2 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -27,6 +27,10 @@ #define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ ((key_len) == 2 * KEY_SIZE_BYTES)) +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +/* Global data structure */ +static struct fsl_secboot_glb glb; +#endif /* This array contains DER value for SHA-256 */ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, @@ -60,7 +64,7 @@ self: #if defined(CONFIG_FSL_ISBC_KEY_EXT) static u32 check_ie(struct fsl_secboot_img_priv *img) { - if (img->hdr.ie_flag) + if (img->hdr.ie_flag & IE_FLAG_MASK) return 1; return 0; @@ -119,7 +123,21 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) } #endif -static int get_ie_info_addr(u32 *ie_addr) +#if defined(CONFIG_ESBC_HDR_LS) +static int get_ie_info_addr(uintptr_t *ie_addr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + /* For LS-CH3, the address of IE Table is + * stated in Scratch13 and scratch14 of DCFG. + * Bootrom validates this table while validating uboot. + * DCFG is LE*/ + *ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]); + *ie_addr = *ie_addr << 32; + *ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]); + return 0; +} +#else /* CONFIG_ESBC_HDR_LS */ +static int get_ie_info_addr(uintptr_t *ie_addr) { struct fsl_secboot_img_hdr *hdr; struct fsl_secboot_sg_table *sg_tbl; @@ -147,16 +165,17 @@ static int get_ie_info_addr(u32 *ie_addr) /* IE Key Table is the first entry in the SG Table */ #if defined(CONFIG_MPC85xx) - *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) + - flash_base_addr; + *ie_addr = (uintptr_t)((sg_tbl->src_addr & + ~(CONFIG_SYS_PBI_FLASH_BASE)) + + flash_base_addr); #else - *ie_addr = sg_tbl->src_addr; + *ie_addr = (uintptr_t)sg_tbl->src_addr; #endif - debug("IE Table address is %x\n", *ie_addr); + debug("IE Table address is %lx\n", *ie_addr); return 0; } - +#endif /* CONFIG_ESBC_HDR_LS */ #endif #ifdef CONFIG_KEY_REVOCATION @@ -164,7 +183,10 @@ static int get_ie_info_addr(u32 *ie_addr) static u32 check_srk(struct fsl_secboot_img_priv *img) { #ifdef CONFIG_ESBC_HDR_LS - /* In LS, No SRK Flag as SRK is always present*/ + /* In LS, No SRK Flag as SRK is always present if IE not present*/ +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + return !check_ie(img); +#endif return 1; #else if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) @@ -253,14 +275,29 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) #endif /* CONFIG_ESBC_HDR_LS */ #if defined(CONFIG_FSL_ISBC_KEY_EXT) + +static void install_ie_tbl(uintptr_t ie_tbl_addr, + struct fsl_secboot_img_priv *img) +{ + /* Copy IE tbl to Global Data */ + memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info)); + img->ie_addr = (uintptr_t)&glb.ie_tbl; + glb.ie_addr = img->ie_addr; +} + static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) { struct fsl_secboot_img_hdr *hdr = &img->hdr; u32 ie_key_len, ie_revoc_flag, ie_num; struct ie_key_info *ie_info; - if (get_ie_info_addr(&img->ie_addr)) - return ERROR_IE_TABLE_NOT_FOUND; + if (!img->ie_addr) { + if (get_ie_info_addr(&img->ie_addr)) + return ERROR_IE_TABLE_NOT_FOUND; + else + install_ie_tbl(img->ie_addr, img); + } + ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; if (ie_info->num_keys == 0 || ie_info->num_keys > 32) return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; @@ -786,6 +823,26 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) return 0; } +/* Function to initialize img priv and global data structure + */ +static int secboot_init(struct fsl_secboot_img_priv **img_ptr) +{ + *img_ptr = malloc(sizeof(struct fsl_secboot_img_priv)); + + struct fsl_secboot_img_priv *img = *img_ptr; + + if (!img) + return -ENOMEM; + memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + if (glb.ie_addr) + img->ie_addr = glb.ie_addr; +#endif + return 0; +} + + /* haddr - Address of the header of image to be validated. * arg_hash_str - Option hash string. If provided, this * overrides the key hash in the SFP fuses. @@ -839,12 +896,9 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, hash_cmd = 1; } - img = malloc(sizeof(struct fsl_secboot_img_priv)); - - if (!img) - return -1; - - memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + ret = secboot_init(&img); + if (ret) + goto exit; /* Update the information in Private Struct */ hdr = &img->hdr; @@ -899,5 +953,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, } exit: + /* Free Img as it was malloc'ed*/ + free(img); return ret; } diff --git a/include/fsl_validate.h b/include/fsl_validate.h index c350938..452c6df 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -40,8 +40,8 @@ struct fsl_secboot_img_hdr { u8 num_srk; u8 srk_sel; u8 reserve; - u8 ie_flag; } len_kr; + u8 ie_flag; u32 uid_flag; @@ -69,6 +69,11 @@ struct fsl_secboot_img_hdr { #define MAX_KEY_ENTRIES 8 #endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#define IE_FLAG_MASK 0x1 +#define SCRATCH_IE_LOW_ADR 13 +#define SCRATCH_IE_HIGH_ADR 14 +#endif #else /* CONFIG_ESBC_HDR_LS */ @@ -150,6 +155,10 @@ struct fsl_secboot_img_hdr { #define MAX_KEY_ENTRIES 4 #endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#define IE_FLAG_MASK 0xFFFFFFFF +#endif + #endif /* CONFIG_ESBC_HDR_LS */ @@ -202,6 +211,17 @@ struct fsl_secboot_sg_table { }; #endif +/* ESBC global structure. + * Data to be used across verification of different images. + * Stores follwoing Data: + * IE Table + */ +struct fsl_secboot_glb { +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + uintptr_t ie_addr; + struct ie_key_info ie_tbl; +#endif +}; /* * ESBC private structure. * Private structure used by ESBC to store following fields @@ -213,7 +233,7 @@ struct fsl_secboot_sg_table { */ struct fsl_secboot_img_priv { uint32_t hdr_location; - u32 ie_addr; + uintptr_t ie_addr; u32 key_len; struct fsl_secboot_img_hdr hdr; -- 1.9.1

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