February 2017 - U-Boot

[U-Boot] [PATCH v2 1/2] power: pmic: add the max8997 controller for DM
by Jaehoon Chung 09 Feb '17

09 Feb '17

Add the max8997 controller for Driver model. Exynos4210 is using max8997 pmic controller. (pmic_max8997.c should be deprecated.) Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changelog on V2: - Add the descirption in more detail - Change from DM_PMIC_MAX8997 to PMIC_MAX8997 - Fixes header file ordering drivers/power/pmic/Kconfig | 15 +++++++++++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/max8997.c | 61 ++++++++++++++++++++++++++++++++++++++++++++ drivers/power/pmic/max8998.c | 2 +- 4 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 drivers/power/pmic/max8997.c diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index e7cc405..03fea07 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -61,6 +61,21 @@ config DM_PMIC_MAX8998 This config enables implementation of driver-model pmic uclass features for PMIC MAX8998. The driver implements read/write operations. +config PMIC_MAX8997 + bool "Enable Driver Model for PMIC MAX8997" + depends on DM_PMIC + ---help--- + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8997. The driver implements read/write operations. + This is a Power Management IC with RTC, Fuel Gauge, MUIC control on Chip. + - 21x LDOs + - 12x GPIOs + - Haptic Motor driver + - RTC with two alarms + - Fueal Gauge and One backup battery charger + - MUIC + - Others + config PMIC_PM8916 bool "Enable Driver Model for Qualcomm PM8916 PMIC" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 8615939..40240c7 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_ACT8846) += act8846.o +obj-$(CONFIG_PMIC_MAX8997) += max8997.o obj-$(CONFIG_PMIC_PM8916) += pm8916.o obj-$(CONFIG_PMIC_RK808) += rk808.o obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o diff --git a/drivers/power/pmic/max8997.c b/drivers/power/pmic/max8997.c new file mode 100644 index 0000000..f749d7d --- /dev/null +++ b/drivers/power/pmic/max8997.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2016 Samsung Electronics + * Jaehoon Chung <jh80.chung(a)samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/max8997_pmic.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int max8997_reg_count(struct udevice *dev) +{ + return PMIC_NUM_OF_REGS; +} + +static int max8997_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) + error("write error to device: %p register: %#x!", dev, reg); + + return ret; +} + +static int max8997_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) + error("read error from device: %p register: %#x!", dev, reg); + + return ret; +} + +static struct dm_pmic_ops max8997_ops = { + .reg_count = max8997_reg_count, + .read = max8997_read, + .write = max8997_write, +}; + +static const struct udevice_id max8997_ids[] = { + { .compatible = "maxim,max8997" }, + { }, +}; + +U_BOOT_DRIVER(pmic_max8997) = { + .name = "max8997_pmic", + .id = UCLASS_PMIC, + .of_match = max8997_ids, + .ops = &max8997_ops, +}; diff --git a/drivers/power/pmic/max8998.c b/drivers/power/pmic/max8998.c index 3baa8da..7c4773c 100644 --- a/drivers/power/pmic/max8998.c +++ b/drivers/power/pmic/max8998.c @@ -7,10 +7,10 @@ #include <common.h> #include <dm.h> +#include <errno.h> #include <i2c.h> #include <power/pmic.h> #include <power/max8998_pmic.h> -#include <errno.h> DECLARE_GLOBAL_DATA_PTR; -- 2.10.2

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[U-Boot] [PATCH] mmc: ftsdc021_sdhci: remove the ftsdc021_sdhci.c
by Jaehoon Chung 09 Feb '17

09 Feb '17

ftsdc021_sdhci.c is dead file. There is no reason to maintain this host controller. Removes the entire ftsdc021_sdhci.c. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/Makefile | 1 - drivers/mmc/ftsdc021_sdhci.c | 34 ---------------------------------- 2 files changed, 35 deletions(-) delete mode 100644 drivers/mmc/ftsdc021_sdhci.c diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index e78bd0d..8e922db 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -24,7 +24,6 @@ obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o -obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o obj-$(CONFIG_GENERIC_MMC) += mmc.o ifdef CONFIG_SUPPORT_EMMC_BOOT obj-$(CONFIG_GENERIC_MMC) += mmc_boot.o diff --git a/drivers/mmc/ftsdc021_sdhci.c b/drivers/mmc/ftsdc021_sdhci.c deleted file mode 100644 index 4940ccb..0000000 --- a/drivers/mmc/ftsdc021_sdhci.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2013 Faraday Technology - * Kuo-Jung Su <dantesu(a)faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <malloc.h> -#include <sdhci.h> - -#ifndef CONFIG_FTSDC021_CLOCK -#define CONFIG_FTSDC021_CLOCK clk_get_rate("MMC") -#endif - -int ftsdc021_sdhci_init(u32 regbase) -{ - struct sdhci_host *host = NULL; - uint32_t freq = CONFIG_FTSDC021_CLOCK; - - host = calloc(1, sizeof(struct sdhci_host)); - if (!host) { - puts("sdh_host malloc fail!\n"); - return -ENOMEM; - } - - host->name = "FTSDC021"; - host->ioaddr = (void __iomem *)regbase; - host->quirks = 0; - host->max_clk = freq; - add_sdhci(host, 0, 0); - - return 0; -} -- 2.10.2

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[U-Boot] [PATCH] drivers: mmc: omap_hsmmc: Fix IO Buffer on OMAP36xx
by aford173＠gmail.com 09 Feb '17

09 Feb '17

From: Adam Ford <aford173(a)gmail.com> On the OMAP36xx/37xx the CONTROL_WKUP_CTRL register has a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which are related to GPIO_126, 127 and 129 are disabled. Some boards may need this for MMC. After the PBIAS is configured, this bit should be set high to enable these GPIO pins. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- V4: Fixed some spacing and remove a warning when compiling on board not using the new #define CONFIG_MMC_OMAP36XX_PINS V3: The OMAP36xx datasheet states to clear this bit before changing PBIAS, so this update clears the bit before changing it. This patch also makes the option dependant on MMC_OMAP_HS. V2: Make this feature a config option and add it to the MMC section of the Kconfig. This allows the precompiler to only include it in a small handfull of OMAP36XX and 37XX boards using MMC1. diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index f200e87..37ee267 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_MMC_OMAP_HS=y +CONFIG_MMC_OMAP36XX_PINS=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_MUSB_GADGET=y diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0c07781..01d1dbf 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -131,6 +131,18 @@ config MMC_OMAP_HS If unsure, say N. +config MMC_OMAP36XX_PINS + bool "Enable MMC1 on OMAP36xx/37xx" + depends on OMAP34XX && MMC_OMAP_HS + help + This enables extended-drain in the MMC/SD/SDIO1I/O and + GPIO-associated I/O cells (gpio_126, gpio_127, and gpio_129) + specific to the OMAP36xx/37xx using MMC1 + + If you have a controller with this interface, say Y here. + + If unsure, say N. + config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" depends on RMOBILE diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index b326846..07ab9d7 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -38,6 +38,7 @@ #include <asm/arch/sys_proto.h> #endif #include <dm.h> +#include <asm/arch-omap3/mux.h> DECLARE_GLOBAL_DATA_PTR; @@ -102,6 +103,9 @@ static unsigned char mmc_board_init(struct mmc *mmc) t2_t *t2_base = (t2_t *)T2_BASE; struct prcm *prcm_base = (struct prcm *)PRCM_BASE; u32 pbias_lite; +#ifdef CONFIG_MMC_OMAP36XX_PINS + u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL); +#endif pbias_lite = readl(&t2_base->pbias_lite); pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); @@ -109,12 +113,26 @@ static unsigned char mmc_board_init(struct mmc *mmc) /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ pbias_lite &= ~PBIASLITEVMODE0; #endif +#ifdef CONFIG_MMC_OMAP36XX_PINS + if (get_cpu_family() == CPU_OMAP36XX) { + /* Disable extended drain IO before changing PBIAS */ + wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ; + writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL); + } +#endif writel(pbias_lite, &t2_base->pbias_lite); writel(pbias_lite | PBIASLITEPWRDNZ1 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, &t2_base->pbias_lite); +#ifdef CONFIG_MMC_OMAP36XX_PINS + if (get_cpu_family() == CPU_OMAP36XX) + /* Enable extended drain IO after changing PBIAS */ + writel(wkup_ctrl | + OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, + OMAP34XX_CTRL_WKUP_CTRL); +#endif writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, &t2_base->devconf0); -- 2.7.4

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[U-Boot] [PATCH v2] mmc: mmc-uclass: use the fixed devnum with alias node
by Jaehoon Chung 09 Feb '17

09 Feb '17

If there are alias nodes as "mmc", use the devnum as alias index number. This patch is for fixing a problem of Exynos4 series. Problem is the below thing. Current legacy mode: EXYNOS DWMMC: 0, SAMSUNG SDHCI: 1 After using DM: SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1 Dev index is swapped. Then u-boot can't find the kernel image..because it is already set to 0 as mmcdev. If change from legacy to DM, also needs to touch all exynos4 config file. For using simply, just supporting the fixed devnum with alias node is better than it. Usage: alaise { .... mmc0 = &sdhci2; /* eMMC */ mmc1 = &sdhci1; /* SD */ ... } Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changelog on V2: - Add the #ifndef CONFIG_SPL_BUILD - Fixes the typo by Simon's comment drivers/mmc/mmc-uclass.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 2fe5d61..de7acb6 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -13,6 +13,8 @@ #include <dm/root.h> #include "mmc_private.h" +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_DM_MMC_OPS int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) @@ -192,10 +194,15 @@ int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg) { struct blk_desc *bdesc; struct udevice *bdev; - int ret; + int ret, devnum = -1; + +#ifndef CONFIG_SPL_BUILD + /* Use the fixed index with aliase node's index */ + fdtdec_get_alias_seq(gd->fdt_blob, "mmc", dev->of_offset, &devnum); +#endif - ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512, - 0, &bdev); + ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, + devnum, 512, 0, &bdev); if (ret) { debug("Cannot create block device\n"); return ret; -- 2.10.2

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[U-Boot] [PATCH] nand: atmel: add drvice tree support and dm gpio APIs
by Wenyou Yang 09 Feb '17

09 Feb '17

In order to use the driver model gpio APIs, add the device tree support. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- drivers/mtd/nand/atmel_nand.c | 143 ++++++++++++++++++++++++++++++++++-------- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 3 files changed, 119 insertions(+), 26 deletions(-) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 8669432deb..87ff5c2eb4 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -14,29 +14,34 @@ #include <common.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> +#ifdef CONFIG_DM_GPIO +#include <asm/gpio.h> +#endif +#include <fdtdec.h> #include <malloc.h> #include <nand.h> #include <watchdog.h> #include <linux/mtd/nand_ecc.h> -#ifdef CONFIG_ATMEL_NAND_HWECC - -/* Register access macros */ -#define ecc_readl(add, reg) \ - readl(add + ATMEL_ECC_##reg) -#define ecc_writel(add, reg, value) \ - writel((value), add + ATMEL_ECC_##reg) +DECLARE_GLOBAL_DATA_PTR; + +struct atmel_nand_data { + struct gpio_desc enable_pin; /* chip enable */ + struct gpio_desc det_pin; /* card detect */ + struct gpio_desc rdy_pin; /* ready/busy */ + u8 ale; /* address line number connected to ALE */ + u8 cle; /* address line number connected to CLE */ + u8 bus_width_16; /* buswidth is 16 bit */ + u8 ecc_mode; /* ecc mode */ + u8 on_flash_bbt; /* bbt on flash */ +}; -#include "atmel_nand_ecc.h" /* Hardware ECC registers */ +struct atmel_nand_host { + void __iomem *io_base; + struct atmel_nand_data board; #ifdef CONFIG_ATMEL_NAND_HW_PMECC - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -struct atmel_nand_host { struct pmecc_regs __iomem *pmecc; struct pmecc_errloc_regs __iomem *pmerrloc; void __iomem *pmecc_rom_base; @@ -63,9 +68,26 @@ struct atmel_nand_host { int *pmecc_mu; int *pmecc_dmu; int *pmecc_delta; +#endif }; -static struct atmel_nand_host pmecc_host; +static struct atmel_nand_host nand_host; +#ifdef CONFIG_ATMEL_NAND_HWECC + +/* Register access macros */ +#define ecc_readl(add, reg) \ + readl(add + ATMEL_ECC_##reg) +#define ecc_writel(add, reg, value) \ + writel((value), add + ATMEL_ECC_##reg) + +#include "atmel_nand_ecc.h" /* Hardware ECC registers */ + +#ifdef CONFIG_ATMEL_NAND_HW_PMECC + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_SYS_NAND_ONFI_DETECTION +#endif + static struct nand_ecclayout atmel_pmecc_oobinfo; /* @@ -805,12 +827,9 @@ static uint16_t *create_lookup_table(int sector_size) static int atmel_pmecc_nand_init_params(struct nand_chip *nand, struct mtd_info *mtd) { - struct atmel_nand_host *host; + struct atmel_nand_host *host = nand_get_controller_data(nand); int cap, sector_size; - host = &pmecc_host; - nand_set_controller_data(nand, host); - nand->ecc.mode = NAND_ECC_HW; nand->ecc.calculate = NULL; nand->ecc.correct = NULL; @@ -1207,12 +1226,24 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd) #endif /* CONFIG_ATMEL_NAND_HWECC */ static void at91_nand_hwcontrol(struct mtd_info *mtd, - int cmd, unsigned int ctrl) + int cmd, unsigned int ctrl) { struct nand_chip *this = mtd_to_nand(mtd); +#if CONFIG_IS_ENABLED(OF_CONTROL) + struct atmel_nand_host *host = nand_get_controller_data(this); +#endif if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + ulong IO_ADDR_W = (ulong)this->IO_ADDR_W; +#if CONFIG_IS_ENABLED(OF_CONTROL) + IO_ADDR_W &= ~((1 << host->board.ale) + | (1 << host->board.cle)); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= (1 << host->board.cle); + if (ctrl & NAND_ALE) + IO_ADDR_W |= (1 << host->board.ale); +#else IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE | CONFIG_SYS_NAND_MASK_CLE); @@ -1220,10 +1251,18 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE; if (ctrl & NAND_ALE) IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE; +#endif +#ifdef CONFIG_DM_GPIO + if (dm_gpio_is_valid(&host->board.enable_pin)) + dm_gpio_set_value(&host->board.enable_pin, + !(ctrl & NAND_NCE)); +#else #ifdef CONFIG_SYS_NAND_ENABLE_PIN gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE)); #endif +#endif + this->IO_ADDR_W = (void *) IO_ADDR_W; } @@ -1231,12 +1270,24 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, writeb(cmd, this->IO_ADDR_W); } -#ifdef CONFIG_SYS_NAND_READY_PIN static int at91_nand_ready(struct mtd_info *mtd) { +#ifdef CONFIG_DM_GPIO + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct atmel_nand_host *host = nand_get_controller_data(nand_chip); + + if (dm_gpio_is_valid(&host->board.rdy_pin)) + return dm_gpio_get_value(&host->board.rdy_pin); + + return 0; +#else +#ifdef CONFIG_SYS_NAND_READY_PIN return gpio_get_value(CONFIG_SYS_NAND_READY_PIN); -} +#else + return 0; #endif +#endif +} #ifdef CONFIG_SPL_BUILD /* The following code is for SPL */ @@ -1419,6 +1470,10 @@ int at91_nand_wait_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { int ret = 0; + struct atmel_nand_host *host; + + host = &nand_host; + nand_set_controller_data(nand, host); nand->ecc.mode = NAND_ECC_SOFT; #ifdef CONFIG_SYS_NAND_DBW_16 @@ -1486,9 +1541,45 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) int ret; struct nand_chip *nand = &nand_chip[devnum]; struct mtd_info *mtd = nand_to_mtd(nand); + struct atmel_nand_host *host; + + host = &nand_host; + nand_set_controller_data(nand, host); + +#if CONFIG_IS_ENABLED(OF_CONTROL) + struct atmel_nand_data *board; + int node; + + board = &host->board; + node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_ATMEL_NAND); + if (node < 0) + return -1; + + nand->IO_ADDR_R = (void __iomem *) + fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, + node, "reg", + 0, NULL, true); + nand->IO_ADDR_W = nand->IO_ADDR_R; - nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; + board->ale = fdtdec_get_uint(gd->fdt_blob, node, + "atmel,nand-addr-offset", 21); + board->cle = fdtdec_get_uint(gd->fdt_blob, node, + "atmel,nand-cmd-offset", 22); + + gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, + &board->rdy_pin, GPIOD_IS_IN); + + gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 1, + &board->enable_pin, GPIOD_IS_OUT); + + gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 2, + &board->det_pin, GPIOD_IS_IN); +#else + nand->IO_ADDR_R = (void __iomem *)base_addr; + nand->IO_ADDR_W = (void __iomem *)base_addr; +#endif #ifdef CONFIG_NAND_ECC_BCH nand->ecc.mode = NAND_ECC_SOFT_BCH; #else @@ -1498,9 +1589,9 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) nand->options = NAND_BUSWIDTH_16; #endif nand->cmd_ctrl = at91_nand_hwcontrol; -#ifdef CONFIG_SYS_NAND_READY_PIN + nand->dev_ready = at91_nand_ready; -#endif + nand->chip_delay = 75; #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT nand->bbt_options |= NAND_BBT_USE_FLASH; diff --git a/include/fdtdec.h b/include/fdtdec.h index d074478f14..eacf251d63 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -155,6 +155,7 @@ enum fdt_compat_id { COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ + COMPAT_ATMEL_NAND, /* Atmel NAND controller */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 81f47ef2c7..a89e8272e1 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -66,6 +66,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"), + COMPAT(COMPAT_ATMEL_NAND, "atmel,at91rm9200-nand"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- 2.11.0

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[U-Boot] [PATCH 0/6] ARM: DRA7: AM57xx: Enable SPL_DM
by Lokesh Vutla 09 Feb '17

09 Feb '17

- Enable SPL_DM on all DRA7 and AM57xx based platforms. - SPL uses a generic dts on all platforms with same defconfig. - After this series SPL size is increased by ~7KB. Verified MMC, eMMC boot on DRA74-evm, DRA72-evm. MMC boot on AM57xx-evm. Lokesh Vutla (6): tools: omapimage: Fix size in header ARM: OMAP2+: define _image_binary_end to fix SPL_OF_CONTROL ARM: dts: AM57xx: Add generic dts for spl ARM: dts: DRA7: Add generic dts for spl configs: am57xx_evm: Enable SPL_DM configs: dra7xx_evm: Enable SPL_DM arch/arm/dts/Makefile | 3 ++- arch/arm/dts/am57xx-generic-spl.dts | 24 ++++++++++++++++++ arch/arm/dts/dra7-generic-spl.dts | 50 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/u-boot-spl.lds | 2 ++ configs/am57xx_evm_defconfig | 7 ++++-- configs/am57xx_hs_evm_defconfig | 7 ++++-- configs/dra7xx_evm_defconfig | 7 ++++-- configs/dra7xx_hs_evm_defconfig | 7 ++++-- include/configs/am57xx_evm.h | 5 ---- include/configs/dra7xx_evm.h | 5 ---- include/configs/ti_omap5_common.h | 8 +----- tools/gpimage.c | 2 +- tools/omapimage.c | 2 +- 13 files changed, 101 insertions(+), 28 deletions(-) create mode 100644 arch/arm/dts/am57xx-generic-spl.dts create mode 100644 arch/arm/dts/dra7-generic-spl.dts -- 2.11.0

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[U-Boot] [PATCH] x86: baytrail: Configure SPI BIOS parameters
by Stefan Roese 09 Feb '17

09 Feb '17

Without configuring these registers in the SPI controller, the Linux MTD device driver is not able to correctly read/write to the SPI NOR chip at all. In fact, the chip is not detected at all. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/baytrail/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 0bb08524f8..4e12c8ce76 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -16,6 +16,7 @@ #include <asm/lapic.h> #include <asm/msr.h> #include <asm/turbo.h> +#include <asm/arch/iomap.h> #define BYT_PRV_CLK 0x800 #define BYT_PRV_CLK_EN (1 << 0) @@ -23,6 +24,44 @@ #define BYT_PRV_CLK_N_VAL_SHIFT 16 #define BYT_PRV_CLK_UPDATE (1 << 31) +/* SPI register offsets */ +#define OPTYPE 0x96 +#define OPMENU0 0x98 +#define OPMENU1 0x9c + +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) + static void hsuart_clock_set(void *base) { u32 m, n, reg; @@ -40,6 +79,17 @@ static void hsuart_clock_set(void *base) } /* + * Configure SPI controller so that the Linux MTD driver can fully + * access the SPI NOR chip + */ +static void spi_controller_config(void *base) +{ + writew(SPI_OPTYPE, base + OPTYPE); + writel(SPI_OPMENU_LOWER, base + OPMENU0); + writel(SPI_OPMENU_UPPER, base + OPMENU1); +} + +/* * Configure the internal clock of both SIO HS-UARTs, if they are enabled * via FSP */ @@ -60,6 +110,13 @@ int arch_cpu_init_dm(void) } } + /* + * Configure the SPI-NOR controller in a way that the Linux + * MTD SPI-NOR device driver has full read-write access to + * the SPI-NOR chips + */ + spi_controller_config((void *)SPI_BASE_ADDRESS); + return 0; } -- 2.11.0

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[U-Boot] Please pull u-boot-dm
by Simon Glass 09 Feb '17

09 Feb '17

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[U-Boot] [PATCH] GPIO: Correct doc typo "confguration" -> "configuration"
by Robert P. J. Day 09 Feb '17

09 Feb '17

Signed-off-by: Robert P. J. Day <rpjday(a)crashcourse.ca> --- Since it's just inline doc, should have no runtime effects. diff --git a/drivers/gpio/db8500_gpio.c b/drivers/gpio/db8500_gpio.c index db32db6..eefb56d 100644 --- a/drivers/gpio/db8500_gpio.c +++ b/drivers/gpio/db8500_gpio.c @@ -174,7 +174,7 @@ void db8500_gpio_set_output(unsigned gpio, int val) /** * config_pin - configure a pin's mux attributes - * @cfg: pin confguration + * @cfg: pin configuration * * Configures a pin's mode (alternate function or GPIO), its pull up status, * and its sleep mode based on the specified configuration. The @cfg is -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH] Remove unused symbol CONGIG_CMD_STORAGE from board configs
by Lars Poeschel 09 Feb '17

09 Feb '17

Albeit it's a typo, neither CONGIG_CMD_STORAGE nor CONFIG_CMD_STORAGE are used anywhere, so remove the define from the board configs. Signed-off-by: Lars Poeschel <poeschel(a)lemonage.de> --- include/configs/am3517_crane.h | 2 -- include/configs/am3517_evm.h | 2 -- include/configs/omap3_evm.h | 2 -- include/configs/tao3530.h | 1 - 4 files changed, 7 deletions(-) diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 5d568604a6..f1b82df456 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -88,8 +88,6 @@ #ifdef CONFIG_USB_MUSB_HCD -#define CONGIG_CMD_STORAGE - #ifdef CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL #define CONFIG_PREBOOT "usb start" diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 13de819245..1062e20f6d 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -88,8 +88,6 @@ #ifdef CONFIG_USB_MUSB_HOST -#define CONGIG_CMD_STORAGE - #ifdef CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL #define CONFIG_PREBOOT "usb start" diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 8846aa6607..8ed5602bc9 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -217,8 +217,6 @@ #ifdef CONFIG_USB_MUSB_HCD -#define CONGIG_CMD_STORAGE - #ifdef CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL #define CONFIG_PREBOOT "usb start" diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index dafb05fa07..32a4b27870 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -263,7 +263,6 @@ #define CONFIG_USB_ETHER #define CONFIG_USB_ETHER_RNDIS -#define CONGIG_CMD_STORAGE /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK -- 2.11.0

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