February 2017 - U-Boot

[U-Boot] [PATCH v3 0/3] net: phy: Add Marvell M88E1512
by Phil Edworthy 09 Feb '17

09 Feb '17

These patches add support for the Marvell M88E1512 PHY. It turns out that it behaves exactly the same as 88E1518, so it's just a matter of fixing up the uid/mask. Phil Edworthy (3): net: phy: Fix mask so that we can identify Marvell 88E1518 net: phy: Add support for Marvell M88E1512 net: phy: Marvell: Use phy_interface_is_rgmii helper function drivers/net/phy/marvell.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) -- 2.7.4

3 7

[U-Boot] [PATCH] net: phy: ti: Fix dp83867 RGMII_TXID interface path
by Phil Edworthy 09 Feb '17

09 Feb '17

There is code that is specifically for RGMII_TXID interface, but this will never get used because the code checks that the RGMII interface is RGMII_ID to RGMII_RXID; RGMII_TXID is after this. To fix this and avoid similar problems in the future, use the phy_interface_is_rgmii helper function. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- This has _not_ been tested in any way, shape or form! It was picked up when converting PHY code to use the phy_interface_is_rgmii helper function. --- drivers/net/phy/ti.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index c55dd97..5e2b2dd 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -246,8 +246,7 @@ static int dp83867_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0); } - if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && - (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { + if (phy_interface_is_rgmii(phydev)) { val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, DP83867_DEVADDR, phydev->addr); -- 2.7.4

3 2

[U-Boot] [PATCH v2 0/3] net: macb: Add option and clock support
by Wenyou Yang 09 Feb '17

09 Feb '17

The CONFIG_MACB option is added in KConfig to be used to select the Cadence MACB Ethernet driver, and the clock is supported. Changes in v2: - Use positive logic, #ifdef...#else...#endif. - Remove unnecessary splitting the signature of macb_mdc_clk_div() and others. - Add Acked-by tag. Wenyou Yang (3): net: Kconfig: Add CONFIG_MACB option net: macb: Add the clock support net: macb: Remove redundant #ifdef CONFIG_DM_ETH drivers/net/Kconfig | 10 ++++++++++ drivers/net/macb.c | 44 +++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 51 insertions(+), 3 deletions(-) -- 2.7.4

4 9

[U-Boot] [PATCH v4 0/2] SPL: Add support to boot a partition type
by Dalon Westergreen 09 Feb '17

09 Feb '17

From: Dalon Westergreen <dalon.westergreen(a)intel.com> This adds support for the spl to seach for and boot from an arbitrary partition type rather then a specific partition number. When USE_PARTITION_TYPE is enabled, splwill search for the partition type but fallback to the specified partition number. In addition to the above, move SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to Kconfig. Dalon Westergreen (2): SPL: add support to boot from a partition type SPL: Move SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to Kconfig common/spl/Kconfig | 33 +++++++++++++++++++++++++++++++++ common/spl/spl_mmc.c | 27 ++++++++++++++++++--------- configs/db-88f6820-gp_defconfig | 1 + configs/kc1_defconfig | 2 ++ configs/sniper_defconfig | 2 ++ disk/part_dos.c | 1 + include/configs/db-88f6820-gp.h | 1 - include/configs/kc1.h | 2 -- include/configs/sniper.h | 2 -- include/configs/socfpga_common.h | 2 -- include/part.h | 3 +++ 11 files changed, 60 insertions(+), 16 deletions(-) -- 2.7.4

2 8

[U-Boot] [PATCH] defconfig: am43xx_hs_evm: Sync HS defconfig with non-HS defconfig
by Andrew F. Davis 09 Feb '17

09 Feb '17

The non-HS defconfig has been modified without equivalent changes being applied to the HS defconfig. Sync these here. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- configs/am43xx_hs_evm_defconfig | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 8bb1b3535a..6bcbfd77ed 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -10,12 +10,19 @@ CONFIG_FIT=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1, NAND" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_ETH_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USBETH_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -41,6 +48,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y @@ -53,8 +61,8 @@ CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_DM_ETH=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y -- 2.11.0

3 2

[U-Boot] [PATCH v4 4/6] mvebu: usb: xhci: Add VBUS regulator supply to the host driver
by kostap＠marvell.com 09 Feb '17

09 Feb '17

From: Konstantin Porotchkin <kostap(a)marvell.com> The USB device should linked to VBUS regulator through "vbus-supply" DTS property. This patch adds handling for "vbus-supply" property inside the USB device entry for turning on the VBUS regulator upon the host adapter probe. Signed-off-by: Konstantin Porotchkin <kostap(a)marvell.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Nadav Haklai <nadavh(a)marvell.com> Cc: Neta Zur Hershkovits <neta(a)marvell.com> Cc: Igal Liberman <igall(a)marvell.com> Cc: Haim Boot <hayim(a)marvell.com> --- Changes for v4: - Move the VBUS supply handling to use regulator framework - Select DM_REGULATOR by Kconfig for mvebu XHCI driver doc/device-tree-bindings/usb/marvell.xhci-usb.txt | 29 +++++++++++++++++++++++ drivers/usb/host/Kconfig | 1 + drivers/usb/host/xhci-mvebu.c | 14 ++++++++++- 3 files changed, 43 insertions(+), 1 deletion(-) create mode 100644 doc/device-tree-bindings/usb/marvell.xhci-usb.txt diff --git a/doc/device-tree-bindings/usb/marvell.xhci-usb.txt b/doc/device-tree-bindings/usb/marvell.xhci-usb.txt new file mode 100644 index 0000000..cd21115 --- /dev/null +++ b/doc/device-tree-bindings/usb/marvell.xhci-usb.txt @@ -0,0 +1,29 @@ +Marvell SOC USB controllers + +This controller is integrated in Armada 3700/8K. +It uses the same properties as a generic XHCI host controller + +Required properties : + - compatible: should be one or more of: + - "marvell,armada3700-xhci", "generic-xhci" for Armada 37xx SoCs + - "marvell,armada-8k-xhci", "generic-xhci" for Armada A8K SoCs + - reg: should contain address and length of the standard XHCI + register set for the device. + - interrupts: one XHCI interrupt should be described here. + +Optional properties: + - clocks: reference to a clock + - vbus-supply : If present, specifies the fixed regulator to be turned on + for providing power to the USB VBUS rail. + +Example: + cpm_usb3_0: usb3@500000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; + reg = <0x500000 0x4000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpm_syscon0 1 22>; + vbus-supply = <&reg_usb3h0_vbus>; + status = "disabled"; + }; + diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 5129a57..0bf8274 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -25,6 +25,7 @@ config USB_XHCI_MVEBU bool "MVEBU USB 3.0 support" default y depends on ARCH_MVEBU + select DM_REGULATOR help Choose this option to add support for USB 3.0 driver on mvebu SoCs, which includes Armada8K, Armada3700 and other Armada diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c index 46eb937..35d89ab 100644 --- a/drivers/usb/host/xhci-mvebu.c +++ b/drivers/usb/host/xhci-mvebu.c @@ -10,6 +10,7 @@ #include <dm.h> #include <fdtdec.h> #include <usb.h> +#include <power/regulator.h> #include <asm/gpio.h> #include "xhci.h" @@ -44,12 +45,23 @@ static int xhci_usb_probe(struct udevice *dev) struct mvebu_xhci_platdata *plat = dev_get_platdata(dev); struct mvebu_xhci *ctx = dev_get_priv(dev); struct xhci_hcor *hcor; - int len; + int len, ret; + struct udevice *regulator; ctx->hcd = (struct xhci_hccr *)plat->hcd_base; len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)); hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len); + ret = device_get_supply_regulator(dev, "vbus-supply", &regulator); + if (!ret) { + ret = regulator_set_enable(regulator, true); + if (ret) { + printf("Failed to turn ON the VBUS regulator\n"); + return ret; + } + } else + printf("No VBUS regulator found\n"); + /* Enable USB xHCI (VBUS, reset etc) in board specific code */ board_xhci_enable(); -- 2.7.4

3 3

[U-Boot] [PATCH v4 6/6] arm64: mvebu: Add default configuraton for MACCHIATOBin board
by kostap＠marvell.com 09 Feb '17

09 Feb '17

From: Konstantin Porotchkin <kostap(a)marvell.com> Add default configuration for MACHHIATOBin community board based on Aramda-8040 SoC. Change-Id: Ic6b562065c0929ec338492452f765115c15a6188 Signed-off-by: Konstantin Porotchkin <kostap(a)marvell.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Nadav Haklai <nadavh(a)marvell.com> Cc: Neta Zur Hershkovits <neta(a)marvell.com> Cc: Igal Liberman <igall(a)marvell.com> Cc: Haim Boot <hayim(a)marvell.com> --- Changes for v4: - Remove CONFIG_DM_REGULATOR, it is handled by XHCI Kconfig configs/mvebu_mcbin-88f8040_defconfig | 74 +++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 configs/mvebu_mcbin-88f8040_defconfig diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig new file mode 100644 index 0000000..0de3d9e --- /dev/null +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_MVEBU_ARMADA_8K=y +CONFIG_DEFAULT_DEVICE_TREE="armada-8040-mcbin" +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_REGULATOR=y +CONFIG_BLOCK_CACHE=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_DM_GPIO=y +CONFIG_MVEBU_GPIO=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_SMBIOS_MANUFACTURER="" -- 2.7.4

1 0

[U-Boot] [PATCH v4 5/6] arm64: mvebu: dts: Add DTS file for MACCHIATOBin board
by kostap＠marvell.com 09 Feb '17

09 Feb '17

From: Rabeeh Khoury <rabeeh(a)solid-run.com> Added A8040 dts file for community board MACCHIATIBin. The patch includes the following features: AP - Serial console (connected to onboard FTDI usb to serial) CP0 - PCIe x4, SATA, I2C and 10G KR (connected to Marvell 3310 10G copper / SFP+ phy) CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR (connected to Marvell 3310 10G copper / SFP+ phy), SGMII connected to onboard 1512 1Gbps copper phy, and additional SGMII connected to SFP (default 1Gbps can be configured to 2.5Gbps). Network interface naming - egiga0 - CP0 KR egiga1 - CP1 KR egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot) egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps Signed-off-by: Konstantin Porotchkin <kostap(a)marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh(a)solid-run.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Nadav Haklai <nadavh(a)marvell.com> Cc: Neta Zur Hershkovits <neta(a)marvell.com> Cc: Igal Liberman <igall(a)marvell.com> Cc: Haim Boot <hayim(a)marvell.com> --- Changes dor v4: - Put USB VBUS regulator inside the "simple bus" block arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-8040-mcbin.dts | 293 +++++++++++++++++++++++++++++++++++++ 2 files changed, 294 insertions(+) create mode 100644 arch/arm/dts/armada-8040-mcbin.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 397a0ae..a3b139b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-385-amc.dtb \ armada-7040-db.dtb \ armada-8040-db.dtb \ + armada-8040-mcbin.dtb \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts new file mode 100644 index 0000000..e42b092 --- /dev/null +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -0,0 +1,293 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#include "armada-8040.dtsi" /* include SoC device tree */ + +/ { + model = "MACCHIATOBin-8040"; + compatible = "marvell,armada8040-mcbin", + "marvell,armada8040"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &cpm_i2c0; + i2c1 = &cpm_i2c1; + spi0 = &cps_spi1; + gpio0 = &ap_gpio0; + gpio1 = &cpm_gpio0; + gpio2 = &cpm_gpio1; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + simple-bus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb3h0_vbus: usb3-vbus0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_xhci_vbus_pins>; + regulator-name = "reg-usb3h0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <500000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ + }; + }; +}; + +/* Accessible over the mini-USB CON9 connector on the main board */ +&uart0 { + status = "okay"; +}; + +&ap_pinctl { + /* + * MPP Bus: + * eMMC [0-10] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 3 0 0 0 0 0 0 0 3 >; +}; + +/* on-board eMMC */ +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + bus-width= <8>; + status = "okay"; +}; + +&cpm_pinctl { + /* + * MPP Bus: + * [0-31] = 0xff: Keep default CP0_shared_pins: + * [11] CLKOUT_MPP_11 (out) + * [23] LINK_RD_IN_CP2CP (in) + * [25] CLKOUT_MPP_25 (out) + * [29] AVS_FB_IN_CP2CP (in) + * [32,34] SMI + * [33] MSS power down + * [35-38] CP0 I2C1 and I2C0 + * [39] MSS CKE Enable + * [40,41] CP0 UART1 TX/RX + * [42,43] XSMI (controls two 10G phys) + * [47] USB VBUS EN + * [48] FAN PWM + * [49] 10G port 1 interrupt + * [50] 10G port 0 interrupt + * [51] 2.5G SFP TX fault + * [52] PCIe reset out + * [53] 2.5G SFP mode + * [54] 2.5G SFP LOS + * [55] Micro SD card detect + * [56-61] Micro SD + * [62] CP1 KR SFP FAULT + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0 7 0xa 7 2 2 2 2 0xa + 7 7 8 8 0 0 0 0 0 0 + 0 0 0 0 0 0 0xe 0xe 0xe 0xe + 0xe 0xe 0 >; + + cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + marvell,pins = < 47 >; + marvell,function = <0>; + }; + + cpm_pcie_reset_pins: cpm-pcie-reset-pins { + marvell,pins = < 52 >; + marvell,function = <0>; + }; +}; + +/* uSD slot */ +&cpm_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_sdhci_pins>; + bus-width= <4>; + status = "okay"; +}; + +/* PCIe x4 */ +&cpm_pcie0 { + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_reset_pins>; + marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */ + status = "okay"; +}; + +&cpm_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpm_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_i2c1_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpm_sata0 { + status = "okay"; +}; + +&cpm_comphy { + /* + * CP0 Serdes Configuration: + * Lane 0: PCIe0 (x4) + * Lane 1: PCIe0 (x4) + * Lane 2: PCIe0 (x4) + * Lane 3: PCIe0 (x4) + * Lane 4: KR (10G) + * Lane 5: SATA1 + */ + phy0 { + phy-type = <PHY_TYPE_PEX0>; + }; + phy1 { + phy-type = <PHY_TYPE_PEX0>; + }; + phy2 { + phy-type = <PHY_TYPE_PEX0>; + }; + phy3 { + phy-type = <PHY_TYPE_PEX0>; + }; + phy4 { + phy-type = <PHY_TYPE_KR>; + }; + phy5 { + phy-type = <PHY_TYPE_SATA1>; + }; +}; + +&cps_sata0 { + status = "okay"; +}; + +&cps_usb3_0 { + vbus-supply = <&reg_usb3h0_vbus>; + status = "okay"; +}; + +&cps_utmi0 { + status = "okay"; +}; + +&cps_pinctl { + /* + * MPP Bus: + * [0-5] TDM + * [6,7] CP1_UART 0 + * [8] CP1 10G SFP LOS + * [9] CP1 10G PHY RESET + * [10] CP1 10G SFP TX Disable + * [11] CP1 10G SFP Mode + * [12] SPI1 CS1n + * [13] SPI1 MISO (TDM and SPI ROM shared) + * [14] SPI1 CS0n + * [15] SPI1 MOSI (TDM and SPI ROM shared) + * [16] SPI1 CLK (TDM and SPI ROM shared) + * [24] CP1 2.5G SFP TX Disable + * [26] CP0 10G SFP TX Fault + * [27] CP0 10G SFP Mode + * [28] CP0 10G SFP LOS + * [29] CP0 10G SFP TX Disable + * [30] USB Over current indication + * [31] 10G Port 0 phy reset + * [32-62] = 0xff: Keep default CP1_shared_pins: + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0 + 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff>; +}; + +&cps_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cps_spi1_pins>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xce0000>; + }; + }; + }; +}; + +&cps_comphy { + /* + * CP1 Serdes Configuration: + * Lane 0: SGMII2 + * Lane 1: SATA 0 + * Lane 2: USB HOST 0 + * Lane 3: SATA1 + * Lane 4: KR (10G) + * Lane 5: SGMII3 + */ + phy0 { + phy-type = <PHY_TYPE_SGMII2>; + phy-speed = <PHY_SPEED_1_25G>; + }; + phy1 { + phy-type = <PHY_TYPE_SATA0>; + }; + phy2 { + phy-type = <PHY_TYPE_USB3_HOST0>; + }; + phy3 { + phy-type = <PHY_TYPE_SATA1>; + }; + phy4 { + phy-type = <PHY_TYPE_KR>; + }; + phy5 { + phy-type = <PHY_TYPE_SGMII3>; + }; +}; -- 2.7.4

1 0

[U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register
by Dinh Nguyen 09 Feb '17

09 Feb '17

The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll. Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz. Signed-off-by: Dinh Nguyen <dinguyen(a)kernel.org> --- arch/arm/mach-socfpga/clock_manager.c | 3 +++ arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 +++ arch/arm/mach-socfpga/wrap_pll_config.c | 3 +++ 3 files changed, 9 insertions(+) diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index aa71636..29e18f8 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -167,6 +167,9 @@ void cm_basic_init(const struct cm_config * const cfg) /* main mpu */ writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); + /* altera group mpuclk */ + writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); + /* main main clock */ writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 2675951..803c926 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -55,6 +55,9 @@ struct cm_config { uint32_t ddr2xdqsclk; uint32_t ddrdqclk; uint32_t s2fuser2clk; + + /* altera group */ + uint32_t altera_grp_mpuclk; }; void cm_basic_init(const struct cm_config * const cfg); diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index 8a0a0e6..72b5f92 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -116,6 +116,9 @@ static const struct cm_config cm_default_cfg = { CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET), + + /* altera group */ + CONFIG_HPS_ALTERAGRP_MPUCLK, }; const struct cm_config * const cm_get_default_config(void) -- 2.7.4

3 9

[U-Boot] [PATCH] mmc: init mmc block devices on probe
by Fiach Antaw 09 Feb '17

09 Feb '17

MMC devices accessed exclusively via the driver model were not being initialized before being exposed as block devices, causing issues in scenarios where the MMC device is first accessed via the uclass block interface. Signed-off-by: Fiach Antaw <fiach.antaw(a)uqconnect.edu.au> --- drivers/mmc/mmc-uclass.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 2fe5d61..a1c31a5 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -247,6 +247,17 @@ static int mmc_select_hwpart(struct udevice *bdev, int hwpart) return mmc_switch_part(mmc, hwpart); } +static int mmc_blk_probe(struct udevice *dev) +{ + struct blk_desc *block_dev = dev_get_uclass_platdata(dev); + int dev_num = block_dev->devnum; + struct mmc *mmc = find_mmc_device(dev_num); + + if (!mmc) + return -ENODEV; + return mmc_init(mmc); +} + static const struct blk_ops mmc_blk_ops = { .read = mmc_bread, #ifndef CONFIG_SPL_BUILD @@ -260,6 +271,7 @@ U_BOOT_DRIVER(mmc_blk) = { .name = "mmc_blk", .id = UCLASS_BLK, .ops = &mmc_blk_ops, + .probe = mmc_blk_probe, }; #endif /* CONFIG_BLK */ -- 2.7.4

2 2