February 2017 - U-Boot

[U-Boot] [PATCH v1 0/2] sunxi: MUSB support for the sun50i (A64)
by Philipp Tomsich 21 Feb '17

21 Feb '17

The A64 has 3 USB controllers and 2 USB PHYs, but a somewhat odd (actually it's wasteful, as there's no way to use the 2 PHYs and the HSIC output concurrently) muxing scheme between those: * PHY 0 is multiplexed to either MUSB (dual-role) or HCI0 * PHY 1 is dedicated to HCI1 This changeset fixes the common use-case of MUSB controlling PHY0 and HCI1 controlling PHY1. To have HCI0 control PHY0, additional work will be needed to reconcile the fact that the [eo]hci_sunxi infrastructure assumes that EHCI/OHCI controllers start at USB1. Tested on the A64-uQ7 with MUSB (for PHY0) and HCI1 for PHY1. Philipp Tomsich (2): sunxi (sun50i): Set CONFIG_SUNXI_USB_PHYS to 2 (the A64 has 2 PHYs) sunxi (sun50i): improved USB support for sun50i (A64) arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 12 ++++++- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 +++- arch/arm/include/asm/arch-sunxi/usb_phy.h | 2 ++ arch/arm/mach-sunxi/usb_phy.c | 48 +++++++++++++++++---------- drivers/usb/host/ehci-sunxi.c | 14 ++++++++ drivers/usb/host/ohci-sunxi.c | 8 +++++ drivers/usb/musb-new/musb_regs.h | 2 +- drivers/usb/musb-new/sunxi.c | 34 ++++++++++++++----- include/configs/sun50i.h | 2 +- 9 files changed, 98 insertions(+), 30 deletions(-) -- 1.9.1

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[U-Boot] [PATCH v1 0/6] Introduce DCU support for Vybrid
by Sanchayan Maity 21 Feb '17

21 Feb '17

Hello, This patchset adds support for the Freescale/NXP Display Controller Unit (DCU4) found on the LS1021A and Vybrid SoC. Patch series is based on top of latest u-boot master. First patch in the series renames existing CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and then converts it to Kconfig. All board defconfigs affected by this patch have been compile tested. Patch 2-5 introduce incremental changes for supporting DCU on Vybrid. Patch 6 in the series adds DCU support to Vybrid and has been tested on Toradex Colibri VF61 module. Will appreciate it if the maintainers or users of LS1021 SoC can test this to check and report regressions if any. Thanks & Regards, Sanchayan. Sanchayan Maity (1): Convert CONFIG_FSL_DCU_FB to Kconfig Stefan Agner (5): video: fsl_dcu_fb: fix framebuffer to the end of memory video: fsl_dcu_fb: Enable pixel clock after initialization video: fsl_dcu_fb: Update DCU layers for Vybrid video: fsl_dcu_fb: add additional modes for DCU board: toradex: colibri_vf: Add DCU support for Colibri Vybrid arch/arm/cpu/armv7/ls102xa/soc.c | 2 +- arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 14 +++ arch/arm/include/asm/arch-vf610/imx-regs.h | 2 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 31 ++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 3 + board/freescale/ls1021aiot/Makefile | 2 +- board/freescale/ls1021aqds/Makefile | 2 +- board/freescale/ls1021atwr/Makefile | 2 +- board/toradex/colibri_vf/Makefile | 1 + board/toradex/colibri_vf/colibri_vf.c | 76 ++++++++++--- board/toradex/colibri_vf/dcu.c | 38 +++++++ configs/colibri_vf_defconfig | 4 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + drivers/video/Kconfig | 15 +++ drivers/video/Makefile | 2 +- drivers/video/fsl_dcu_fb.c | 124 ++++++++++++++++++--- include/configs/colibri_vf.h | 18 ++- include/configs/ls1021aqds.h | 4 +- include/configs/ls1021atwr.h | 4 +- include/fsl_dcu_fb.h | 1 + scripts/config_whitelist.txt | 1 - 37 files changed, 318 insertions(+), 45 deletions(-) create mode 100644 board/toradex/colibri_vf/dcu.c -- 2.11.1

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[U-Boot] [PATCH v5 0/9] Add STMicroelectronics STiH410-B2260 board
by patrice.chotard＠st.com 21 Feb '17

21 Feb '17

From: Patrice Chotard <patrice.chotard(a)st.com> v5: _ Add Simon Glass's reviewed-by _ move board Kconfig description from patch 1 to 9 v4: _ fix STi serial driver to be fully DT compliant _ remove arch/arm/include/asm/arch-stih410/sti.h and include/dm/platform_data/serial_sti_asc.h which became useless _ board file cleanup _ fix some nits in sti_sdhci.c _ rebased on top of v2017.03-rc2 v3: _ add reviewed-by _ add top level MAINTAINERS entry and in the board MAINTAINERS _ use the fallback table from include/config_fallbacks.h _ minor update in sti_sdhci.c _ reorder patches with functionnal board and defconfig in last _ remove arch/arm/mach-sti/cpu.c and replace it by a sysreset DM driver _ remove arch/arm/mach-sti/timer.c by a timer DM driver _ remove useless arch/arm/include/asm/arch-stih410/syscfg.h _ remove useless arch/arm/include/asm/arch-stih410/gpio.h and update arch/arm/include/asm/gpio.h for ARCH_STI in patch 5 v2: _ fix remarks from Jaechon Chung on SDHCI patch _ fix remarks from Antonio Borneo on board patch _ replace some macro by U-boot generic's one _ add missing maintainers in recipients Patrice Chotard (9): arm: Add support for STMicroelectronics STiH410 soc STiH410: Add STi timer driver STiH410: Add STi sysreset driver STiH410: Add STi serial driver gpio: do not include <asm/arch/gpio.h> for ARCH_STI STiH410: Add STi SDHCI driver STiH410: Add STi pinctrl driver STiH410-B2260: Add device tree board: Add STMicroelectronics STiH410-B2260 support Patrice Chotard (9): arm: Add support for STMicroelectronics STiH410 soc STiH410: Add STi timer driver STiH410: Add STi sysreset driver STiH410: Add STi serial driver gpio: do not include <asm/arch/gpio.h> for ARCH_STI STiH410: Add STi SDHCI driver STiH410: Add STi pinctrl driver STiH410-B2260: Add device tree board: Add STMicroelectronics STiH410-B2260 support MAINTAINERS | 6 + arch/arm/Kconfig | 13 + arch/arm/dts/Makefile | 2 + arch/arm/dts/st-pincfg.h | 71 ++ arch/arm/dts/stih407-clock.dtsi | 326 ++++++ arch/arm/dts/stih407-family.dtsi | 977 +++++++++++++++ arch/arm/dts/stih407-pinctrl.dtsi | 1303 +++++++++++++++++++++ arch/arm/dts/stih410-b2260.dts | 226 ++++ arch/arm/dts/stih410-clock.dtsi | 347 ++++++ arch/arm/dts/stih410-pinctrl.dtsi | 34 + arch/arm/dts/stih410.dtsi | 454 +++++++ arch/arm/include/asm/arch-stih410/sdhci.h | 68 ++ arch/arm/include/asm/gpio.h | 2 +- arch/arm/mach-sti/Kconfig | 31 + board/st/stih410-b2260/Kconfig | 19 + board/st/stih410-b2260/MAINTAINERS | 7 + board/st/stih410-b2260/Makefile | 8 + board/st/stih410-b2260/board.c | 28 + configs/stih410-b2260_defconfig | 26 + drivers/mmc/Kconfig | 7 + drivers/mmc/Makefile | 1 + drivers/mmc/sti_sdhci.c | 141 +++ drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-sti.c | 320 +++++ drivers/serial/Kconfig | 8 + drivers/serial/Makefile | 1 + drivers/serial/serial_sti_asc.c | 211 ++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_sti.c | 82 ++ drivers/timer/Kconfig | 7 + drivers/timer/Makefile | 1 + drivers/timer/sti-timer.c | 78 ++ include/configs/stih410-b2260.h | 60 + include/dt-bindings/clock/stih407-clks.h | 90 ++ include/dt-bindings/clock/stih410-clks.h | 25 + include/dt-bindings/interrupt-controller/irq-st.h | 30 + include/dt-bindings/mfd/st-lpc.h | 16 + include/dt-bindings/reset/stih407-resets.h | 65 + 39 files changed, 5102 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/st-pincfg.h create mode 100644 arch/arm/dts/stih407-clock.dtsi create mode 100644 arch/arm/dts/stih407-family.dtsi create mode 100644 arch/arm/dts/stih407-pinctrl.dtsi create mode 100644 arch/arm/dts/stih410-b2260.dts create mode 100644 arch/arm/dts/stih410-clock.dtsi create mode 100644 arch/arm/dts/stih410-pinctrl.dtsi create mode 100644 arch/arm/dts/stih410.dtsi create mode 100644 arch/arm/include/asm/arch-stih410/sdhci.h create mode 100644 arch/arm/mach-sti/Kconfig create mode 100644 board/st/stih410-b2260/Kconfig create mode 100644 board/st/stih410-b2260/MAINTAINERS create mode 100644 board/st/stih410-b2260/Makefile create mode 100644 board/st/stih410-b2260/board.c create mode 100644 configs/stih410-b2260_defconfig create mode 100644 drivers/mmc/sti_sdhci.c create mode 100644 drivers/pinctrl/pinctrl-sti.c create mode 100644 drivers/serial/serial_sti_asc.c create mode 100644 drivers/sysreset/sysreset_sti.c create mode 100644 drivers/timer/sti-timer.c create mode 100644 include/configs/stih410-b2260.h create mode 100644 include/dt-bindings/clock/stih407-clks.h create mode 100644 include/dt-bindings/clock/stih410-clks.h create mode 100644 include/dt-bindings/interrupt-controller/irq-st.h create mode 100644 include/dt-bindings/mfd/st-lpc.h create mode 100644 include/dt-bindings/reset/stih407-resets.h -- 1.9.1

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[U-Boot] [PATCH v6 0/9] Add STMicroelectronics STiH410-B2260 board
by patrice.chotard＠st.com 21 Feb '17

21 Feb '17

From: Patrice Chotard <patrice.chotard(a)st.com> v6: _ fix last minute bug in pinctrl driver v5: _ Add Simon Glass's reviewed-by _ move board Kconfig description from patch 1 to 9 v4: _ fix STi serial driver to be fully DT compliant _ remove arch/arm/include/asm/arch-stih410/sti.h and include/dm/platform_data/serial_sti_asc.h which became useless _ board file cleanup _ fix some nits in sti_sdhci.c _ rebased on top of v2017.03-rc2 v3: _ add reviewed-by _ add top level MAINTAINERS entry and in the board MAINTAINERS _ use the fallback table from include/config_fallbacks.h _ minor update in sti_sdhci.c _ reorder patches with functionnal board and defconfig in last _ remove arch/arm/mach-sti/cpu.c and replace it by a sysreset DM driver _ remove arch/arm/mach-sti/timer.c by a timer DM driver _ remove useless arch/arm/include/asm/arch-stih410/syscfg.h _ remove useless arch/arm/include/asm/arch-stih410/gpio.h and update arch/arm/include/asm/gpio.h for ARCH_STI in patch 5 v2: _ fix remarks from Jaechon Chung on SDHCI patch _ fix remarks from Antonio Borneo on board patch _ replace some macro by U-boot generic's one _ add missing maintainers in recipients Patrice Chotard (9): arm: Add support for STMicroelectronics STiH410 soc STiH410: Add STi timer driver STiH410: Add STi sysreset driver STiH410: Add STi serial driver gpio: do not include <asm/arch/gpio.h> for ARCH_STI STiH410: Add STi SDHCI driver STiH410: Add STi pinctrl driver STiH410-B2260: Add device tree board: Add STMicroelectronics STiH410-B2260 support MAINTAINERS | 6 + arch/arm/Kconfig | 13 + arch/arm/dts/Makefile | 2 + arch/arm/dts/st-pincfg.h | 71 ++ arch/arm/dts/stih407-clock.dtsi | 326 ++++++ arch/arm/dts/stih407-family.dtsi | 977 +++++++++++++++ arch/arm/dts/stih407-pinctrl.dtsi | 1303 +++++++++++++++++++++ arch/arm/dts/stih410-b2260.dts | 226 ++++ arch/arm/dts/stih410-clock.dtsi | 347 ++++++ arch/arm/dts/stih410-pinctrl.dtsi | 34 + arch/arm/dts/stih410.dtsi | 454 +++++++ arch/arm/include/asm/arch-stih410/sdhci.h | 68 ++ arch/arm/include/asm/gpio.h | 2 +- arch/arm/mach-sti/Kconfig | 31 + board/st/stih410-b2260/Kconfig | 19 + board/st/stih410-b2260/MAINTAINERS | 7 + board/st/stih410-b2260/Makefile | 8 + board/st/stih410-b2260/board.c | 28 + configs/stih410-b2260_defconfig | 26 + drivers/mmc/Kconfig | 7 + drivers/mmc/Makefile | 1 + drivers/mmc/sti_sdhci.c | 141 +++ drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-sti.c | 320 +++++ drivers/serial/Kconfig | 8 + drivers/serial/Makefile | 1 + drivers/serial/serial_sti_asc.c | 211 ++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_sti.c | 82 ++ drivers/timer/Kconfig | 7 + drivers/timer/Makefile | 1 + drivers/timer/sti-timer.c | 78 ++ include/configs/stih410-b2260.h | 60 + include/dt-bindings/clock/stih407-clks.h | 90 ++ include/dt-bindings/clock/stih410-clks.h | 25 + include/dt-bindings/interrupt-controller/irq-st.h | 30 + include/dt-bindings/mfd/st-lpc.h | 16 + include/dt-bindings/reset/stih407-resets.h | 65 + 39 files changed, 5102 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/st-pincfg.h create mode 100644 arch/arm/dts/stih407-clock.dtsi create mode 100644 arch/arm/dts/stih407-family.dtsi create mode 100644 arch/arm/dts/stih407-pinctrl.dtsi create mode 100644 arch/arm/dts/stih410-b2260.dts create mode 100644 arch/arm/dts/stih410-clock.dtsi create mode 100644 arch/arm/dts/stih410-pinctrl.dtsi create mode 100644 arch/arm/dts/stih410.dtsi create mode 100644 arch/arm/include/asm/arch-stih410/sdhci.h create mode 100644 arch/arm/mach-sti/Kconfig create mode 100644 board/st/stih410-b2260/Kconfig create mode 100644 board/st/stih410-b2260/MAINTAINERS create mode 100644 board/st/stih410-b2260/Makefile create mode 100644 board/st/stih410-b2260/board.c create mode 100644 configs/stih410-b2260_defconfig create mode 100644 drivers/mmc/sti_sdhci.c create mode 100644 drivers/pinctrl/pinctrl-sti.c create mode 100644 drivers/serial/serial_sti_asc.c create mode 100644 drivers/sysreset/sysreset_sti.c create mode 100644 drivers/timer/sti-timer.c create mode 100644 include/configs/stih410-b2260.h create mode 100644 include/dt-bindings/clock/stih407-clks.h create mode 100644 include/dt-bindings/clock/stih410-clks.h create mode 100644 include/dt-bindings/interrupt-controller/irq-st.h create mode 100644 include/dt-bindings/mfd/st-lpc.h create mode 100644 include/dt-bindings/reset/stih407-resets.h -- 1.9.1

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[U-Boot] [PATCH v2 1/3] x86: Introduce INTEL_MID quirk option
by Andy Shevchenko 21 Feb '17

21 Feb '17

Intel Mobile Internet Device (MID) platforms have special treatment in some cases, such as CPU enumeration or boot parameters configuration. Besides that several drivers are specifically developed for the IP blocks found on Intel MID platforms. Those drivers will be dependent to this option. Here we introduce specific quirk option for such cases. It is supposed to be selected by Intel MID platform boards, for example, Intel Edison. Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- arch/x86/Kconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5f9597b230..7abbfd8223 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -80,6 +80,20 @@ config VENDOR_INTEL endchoice +# subarchitectures-specific options below +config INTEL_MID + bool "Intel MID platform support" + ---help--- + Select to build a kernel capable of supporting Intel MID + (Mobile Internet Device) platform systems which do not have + the PCI legacy interfaces. + + If you are building for a PC class system say N here. + + Intel MID platforms are based on an Intel processor and + chipset which consume less power than most of the x86 + derivatives. + # board-specific options below source "board/advantech/Kconfig" source "board/congatec/Kconfig" -- 2.11.0

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[U-Boot] [PATCH] x86: Force 32-bit jumps in interrupt handlers
by J. Tang 21 Feb '17

21 Feb '17

Depending upon the compiler used, IRQ entries could vary in sizes. With GCC 5.x, the code generator will use short jumps for some IRQ entries but near jumps for others. For example, GCC 5.4.0 generates the following: $ objdump -d interrupt.o <snip> 00000207 <irq_18>: 207: 6a 12 push $0x12 209: eb 85 jmp 190 <irq_common_entry> 0000020b <irq_19>: 20b: 6a 13 push $0x13 20d: eb 81 jmp 190 <irq_common_entry> 0000020f <irq_20>: 20f: 6a 14 push $0x14 211: e9 7a ff ff ff jmp 190 <irq_common_entry> 00000216 <irq_21>: 216: 6a 15 push $0x15 218: e9 73 ff ff ff jmp 190 <irq_common_entry> This causes a problem in cpu_init_interrupts(), because the IDT setup assumed same sizes for all IRQ entries. GCC 4.x always generated 32-bit jumps, so this previously was not a problem. The fix is to force 32-bit near jumps for all entries within the inline assembly. This works for GCC 5.x, and 4.x was already using that form of jumping. Signed-off-by: Jason Tang <tang(a)jtang.org> --- arch/x86/cpu/i386/interrupt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index a058303..ba576fe 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; ".type irq_"#x", @function\n" \ "irq_"#x":\n" \ "pushl $"#x"\n" \ - "jmp irq_common_entry\n" + "jmp.d32 irq_common_entry\n" static char *exceptions[] = { "Divide Error", -- 2.1.4

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[U-Boot] [PATCH v1 0/2] sunxi: A64: support GPIO
by Philipp Tomsich 21 Feb '17

21 Feb '17

This changeset adds support for the PIO and the R_PIO block on the sun50iw1p1 (A64). Philipp Tomsich (2): sunxi: sun50i/a64: enabled GPIO via sunxi_gpio.c sunxi: sun50i/a64: add r_pio (bank 'L') gpio support arch/arm/dts/sun50i-a64.dtsi | 11 +++++++++++ drivers/gpio/sunxi_gpio.c | 7 +++++++ 2 files changed, 18 insertions(+) -- 1.9.1

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[U-Boot] [PATCHv2 1/2] pci: layerscape: add LS2088A series SoC pcie support
by Zhiqiang Hou 21 Feb '17

21 Feb '17

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- V2: - Moved the fix of PF control registers address to probe func. arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 46 +++++++++++++++++++++++++++++++++ drivers/pci/pcie_layerscape.c | 36 ++++++++++++++++++++++++++ drivers/pci/pcie_layerscape.h | 8 ++++++ 3 files changed, 90 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 335f225..6afb40f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -89,6 +89,49 @@ static inline void early_mmu_setup(void) set_sctlr(get_sctlr() | CR_M); } +static void fix_final_mmu_map(void) +{ +#ifdef CONFIG_LS2080A + unsigned int i; + u32 svr, ver; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + svr = gur_in32(&gur->svr); + ver = SVR_SOC_VER(svr); + + /* Fix PCIE base and size for LS2088A */ + if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) || + (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) { + for (i = 0; i < ARRAY_SIZE(final_map); i++) { + switch (final_map[i].phys) { + case CONFIG_SYS_PCIE1_PHYS_ADDR: + final_map[i].phys = 0x2000000000ULL; + final_map[i].virt = 0x2000000000ULL; + final_map[i].size = 0x800000000ULL; + break; + case CONFIG_SYS_PCIE2_PHYS_ADDR: + final_map[i].phys = 0x2800000000ULL; + final_map[i].virt = 0x2800000000ULL; + final_map[i].size = 0x800000000ULL; + break; + case CONFIG_SYS_PCIE3_PHYS_ADDR: + final_map[i].phys = 0x3000000000ULL; + final_map[i].virt = 0x3000000000ULL; + final_map[i].size = 0x800000000ULL; + break; + case CONFIG_SYS_PCIE4_PHYS_ADDR: + final_map[i].phys = 0x3800000000ULL; + final_map[i].virt = 0x3800000000ULL; + final_map[i].size = 0x800000000ULL; + break; + default: + break; + } + } + } +#endif +} + /* * The final tables look similar to early tables, but different in detail. * These tables are in DRAM. Sub tables are added to enable cache for @@ -105,6 +148,9 @@ static inline void final_mmu_setup(void) int index; #endif + /* fix the final_map before filling in the block entries */ + fix_final_mmu_map(); + mem_map = final_map; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 90b9fe2..f468437 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -50,6 +50,7 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie) { u32 state; uint svr; + u32 off = 0; svr = get_svr(); if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) { @@ -167,6 +168,27 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie) pci_get_regions(pcie->bus, &io, &mem, &pref); idx = PCIE_ATU_REGION_INDEX1 + 1; + /* Fix the pcie memory map for LS2088A series SoCs */ + svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; + if (svr == SVR_LS2088A || svr == SVR_LS2084A || + svr == SVR_LS2048A || svr == SVR_LS2044A) { + if (io) + io->phys_start = (io->phys_start & + (PCIE_PHYS_SIZE - 1)) + + LS2088A_PCIE1_PHYS_ADDR + + LS2088A_PCIE_PHYS_SIZE * pcie->idx; + if (mem) + mem->phys_start = (mem->phys_start & + (PCIE_PHYS_SIZE - 1)) + + LS2088A_PCIE1_PHYS_ADDR + + LS2088A_PCIE_PHYS_SIZE * pcie->idx; + if (pref) + pref->phys_start = (pref->phys_start & + (PCIE_PHYS_SIZE - 1)) + + LS2088A_PCIE1_PHYS_ADDR + + LS2088A_PCIE_PHYS_SIZE * pcie->idx; + } + if (io) /* ATU : OUTBOUND : IO */ ls_pcie_atu_outbound_set(pcie, idx++, @@ -442,6 +464,7 @@ static int ls_pcie_probe(struct udevice *dev) u8 header_type; u16 link_sta; bool ep_mode; + uint svr; int ret; pcie->bus = dev; @@ -495,6 +518,19 @@ static int ls_pcie_probe(struct udevice *dev) return ret; } + /* + * Fix the pcie memory map address and PF control registers address + * for LS2088A series SoCs + */ + svr = get_svr(); + svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; + if (svr == SVR_LS2088A || svr == SVR_LS2084A || + svr == SVR_LS2048A || svr == SVR_LS2044A) { + pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + + LS2088A_PCIE_PHYS_SIZE * pcie->idx; + pcie->ctrl = pcie->lut + 0x40000; + } + pcie->cfg0 = map_physmem(pcie->cfg_res.start, fdt_resource_size(&pcie->cfg_res), MAP_NOCACHE); diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 1e635ef..029695d 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -26,6 +26,10 @@ #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR #endif +#define PCIE_PHYS_SIZE 0x200000000 +#define LS2088A_PCIE_PHYS_SIZE 0x800000000 +#define LS2088A_PCIE1_PHYS_ADDR 0x2000000000 + /* iATU registers */ #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) @@ -107,6 +111,10 @@ #define SVR_LS102XA 0 #define SVR_VAR_PER_SHIFT 8 #define SVR_LS102XA_MASK 0x700 +#define SVR_LS2088A 0x870900 +#define SVR_LS2084A 0x870910 +#define SVR_LS2048A 0x870920 +#define SVR_LS2044A 0x870930 /* LS1021a PCIE space */ #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/2] common: fitimage support for arbitrary fpga type
by Dalon Westergreen 20 Feb '17

20 Feb '17

The intent of these patches is to modify existing fitimage support for fpga configuration to allow configuration of any fpga type supported by the fpga_load command. Note though, that fitimage support for fpga configuration only allows for configuration of the fpga of devnum 0. Dalon Westergreen (2): common: image: update boot_get_fpga to support arbitrary fpga image common: bootm: add support for arbitrary fgpa configuration common/bootm.c | 2 +- common/image.c | 37 ++++++++++++++++++++++--------------- 2 files changed, 23 insertions(+), 16 deletions(-) -- 2.7.4

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[U-Boot] [PATCH 0/3] SECURE Boot targets for NAND and SD on LS1043, LS1046
by Ruchika Gupta 20 Feb '17

20 Feb '17

Ruchika Gupta (3): arm: ls1043ardb: Add SD secure boot target arm: ls1043ardb: Add NAND secure boot target arm: ls1046ardb: Add SD secure boot target arch/arm/include/asm/fsl_secure_boot.h | 16 +++++-- board/freescale/common/fsl_validate.c | 4 ++ board/freescale/ls1043ardb/ls1043ardb.c | 20 +++++++++ board/freescale/ls1046ardb/ls1046ardb.c | 19 +++++++++ configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 57 +++++++++++++++++++++++++ configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 57 +++++++++++++++++++++++++ configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 45 +++++++++++++++++++ include/config_fsl_chain_trust.h | 9 ++-- include/configs/ls1043a_common.h | 34 +++++++++++++-- include/configs/ls1043ardb.h | 2 +- include/configs/ls1046a_common.h | 17 ++++++-- include/configs/ls1046ardb.h | 1 - 12 files changed, 266 insertions(+), 15 deletions(-) create mode 100644 configs/ls1043ardb_nand_SECURE_BOOT_defconfig create mode 100644 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig create mode 100644 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig -- The patchset is dependent on the following patches: https://patchwork.ozlabs.org/patch/717614/ http://patchwork.ozlabs.org/patch/724332/ http://patchwork.ozlabs.org/patch/729932/ http://patchwork.ozlabs.org/patch/729980/ 1.9.1

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