February 2017 - U-Boot

[U-Boot] [PATCH v1] armv8: spl: Call spl_relocate_stack_gd for ARMv8
by Philipp Tomsich 22 Feb '17

22 Feb '17

As part of the startup process for boards using the SPL, we need to call spl_relocate_stack_gd. This is needed to set up malloc with its DRAM buffer. Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- arch/arm/lib/crt0_64.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 19c6a98..05a80ee 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -105,15 +105,21 @@ ENTRY(_main) relocation_return: /* * Set up final (full) environment */ bl c_runtime_cpu_setup /* still call old routine */ #endif /* !CONFIG_SPL_BUILD */ - +#if defined(CONFIG_SPL_BUILD) + bl spl_relocate_stack_gd + mov x1, sp + adds x0, x0, xzr + csel x0, x0, x1, ne + mov sp, x0 +#endif /* TODO: For SPL, call spl_relocate_stack_gd() to alloc stack relocation */ /* * Clear BSS section */ ldr x0, =__bss_start /* this is auto-relocated! */ ldr x1, =__bss_end /* this is auto-relocated! */ -- 1.9.1

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[U-Boot] [PATCH v1] dtoc: make ScanTree recurse into subnodes
by Philipp Tomsich 22 Feb '17

22 Feb '17

Previously, dtoc could only process the top-level nodes which led to device nodes in hierarchical trees to be ignored. E.g. the mmc0 node in the following example would be ignored, as only the soc node was processed: / { soc { mmc0 { /* ... */ }; }; }; This introduces a recursive helper method ScanNode, which is used by ScanTree to recursively parse the entire tree hierarchy. Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- tools/dtoc/dtoc.py | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py index 6df7b0d..fe8b0c2 100755 --- a/tools/dtoc/dtoc.py +++ b/tools/dtoc/dtoc.py @@ -66,290 +66,307 @@ def TabTo(num_tabs, str): class DtbPlatdata: """Provide a means to convert device tree binary data to platform data The output of this process is C structures which can be used in space- constrained encvironments where the ~3KB code overhead of device tree code is not affordable. Properties: fdt: Fdt object, referencing the device tree _dtb_fname: Filename of the input device tree binary file _valid_nodes: A list of Node object with compatible strings _options: Command-line options _phandle_node: A dict of nodes indexed by phandle number (1, 2...) _outfile: The current output file (sys.stdout or a real file) _lines: Stashed list of output lines for outputting in the future _phandle_node: A dict of Nodes indexed by phandle (an integer) """ def __init__(self, dtb_fname, options): self._dtb_fname = dtb_fname self._valid_nodes = None self._options = options self._phandle_node = {} self._outfile = None self._lines = [] def SetupOutput(self, fname): """Set up the output destination Once this is done, future calls to self.Out() will output to this file. Args: fname: Filename to send output to, or '-' for stdout """ if fname == '-': self._outfile = sys.stdout else: self._outfile = open(fname, 'w') def Out(self, str): """Output a string to the output file Args: str: String to output """ self._outfile.write(str) def Buf(self, str): """Buffer up a string to send later Args: str: String to add to our 'buffer' list """ self._lines.append(str) def GetBuf(self): """Get the contents of the output buffer, and clear it Returns: The output buffer, which is then cleared for future use """ lines = self._lines self._lines = [] return lines def GetValue(self, type, value): """Get a value as a C expression For integers this returns a byte-swapped (little-endian) hex string For bytes this returns a hex string, e.g. 0x12 For strings this returns a literal string enclosed in quotes For booleans this return 'true' Args: type: Data type (fdt_util) value: Data value, as a string of bytes """ if type == fdt.TYPE_INT: return '%#x' % fdt_util.fdt32_to_cpu(value) elif type == fdt.TYPE_BYTE: return '%#x' % ord(value[0]) elif type == fdt.TYPE_STRING: return '"%s"' % value elif type == fdt.TYPE_BOOL: return 'true' def GetCompatName(self, node): """Get a node's first compatible string as a C identifier Args: node: Node object to check Return: C identifier for the first compatible string """ compat = node.props['compatible'].value if type(compat) == list: compat = compat[0] return Conv_name_to_c(compat) def ScanDtb(self): """Scan the device tree to obtain a tree of notes and properties Once this is done, self.fdt.GetRoot() can be called to obtain the device tree root node, and progress from there. """ self.fdt = fdt_select.FdtScan(self._dtb_fname) + def ScanNode(self, root): + for node in root.subnodes: + if 'compatible' in node.props: + status = node.props.get('status') + if (not options.include_disabled and not status or + status.value != 'disabled'): + self._valid_nodes.append(node) + phandle_prop = node.props.get('phandle') + if phandle_prop: + phandle = phandle_prop.GetPhandle() + self._phandle_node[phandle] = node + + # recurse to handle any subnodes + self.ScanNode(node); + def ScanTree(self): """Scan the device tree for useful information This fills in the following properties: _phandle_node: A dict of Nodes indexed by phandle (an integer) _valid_nodes: A list of nodes we wish to consider include in the platform data """ - node_list = [] self._phandle_node = {} + self._valid_nodes = [] + return self.ScanNode(self.fdt.GetRoot()); + for node in self.fdt.GetRoot().subnodes: if 'compatible' in node.props: status = node.props.get('status') if (not options.include_disabled and not status or status.value != 'disabled'): node_list.append(node) phandle_prop = node.props.get('phandle') if phandle_prop: phandle = phandle_prop.GetPhandle() self._phandle_node[phandle] = node self._valid_nodes = node_list def IsPhandle(self, prop): """Check if a node contains phandles We have no reliable way of detecting whether a node uses a phandle or not. As an interim measure, use a list of known property names. Args: prop: Prop object to check Return: True if the object value contains phandles, else False """ if prop.name in ['clocks']: return True return False def ScanStructs(self): """Scan the device tree building up the C structures we will use. Build a dict keyed by C struct name containing a dict of Prop object for each struct field (keyed by property name). Where the same struct appears multiple times, try to use the 'widest' property, i.e. the one with a type which can express all others. Once the widest property is determined, all other properties are updated to match that width. """ structs = {} for node in self._valid_nodes: node_name = self.GetCompatName(node) fields = {} # Get a list of all the valid properties in this node. for name, prop in node.props.items(): if name not in PROP_IGNORE_LIST and name[0] != '#': fields[name] = copy.deepcopy(prop) # If we've seen this node_name before, update the existing struct. if node_name in structs: struct = structs[node_name] for name, prop in fields.items(): oldprop = struct.get(name) if oldprop: oldprop.Widen(prop) else: struct[name] = prop # Otherwise store this as a new struct. else: structs[node_name] = fields upto = 0 for node in self._valid_nodes: node_name = self.GetCompatName(node) struct = structs[node_name] for name, prop in node.props.items(): if name not in PROP_IGNORE_LIST and name[0] != '#': prop.Widen(struct[name]) upto += 1 return structs def GenerateStructs(self, structs): """Generate struct defintions for the platform data This writes out the body of a header file consisting of structure definitions for node in self._valid_nodes. See the documentation in README.of-plat for more information. """ self.Out('#include <stdbool.h>\n') self.Out('#include <libfdt.h>\n') # Output the struct definition for name in sorted(structs): self.Out('struct %s%s {\n' % (STRUCT_PREFIX, name)); for pname in sorted(structs[name]): prop = structs[name][pname] if self.IsPhandle(prop): # For phandles, include a reference to the target self.Out('\t%s%s[%d]' % (TabTo(2, 'struct phandle_2_cell'), Conv_name_to_c(prop.name), len(prop.value) / 2)) else: ptype = TYPE_NAMES[prop.type] self.Out('\t%s%s' % (TabTo(2, ptype), Conv_name_to_c(prop.name))) if type(prop.value) == list: self.Out('[%d]' % len(prop.value)) self.Out(';\n') self.Out('};\n') def GenerateTables(self): """Generate device defintions for the platform data This writes out C platform data initialisation data and U_BOOT_DEVICE() declarations for each valid node. See the documentation in README.of-plat for more information. """ self.Out('#include <common.h>\n') self.Out('#include <dm.h>\n') self.Out('#include <dt-structs.h>\n') self.Out('\n') node_txt_list = [] for node in self._valid_nodes: struct_name = self.GetCompatName(node) var_name = Conv_name_to_c(node.name) self.Buf('static struct %s%s %s%s = {\n' % (STRUCT_PREFIX, struct_name, VAL_PREFIX, var_name)) for pname, prop in node.props.items(): if pname in PROP_IGNORE_LIST or pname[0] == '#': continue ptype = TYPE_NAMES[prop.type] member_name = Conv_name_to_c(prop.name) self.Buf('\t%s= ' % TabTo(3, '.' + member_name)) # Special handling for lists if type(prop.value) == list: self.Buf('{') vals = [] # For phandles, output a reference to the platform data # of the target node. if self.IsPhandle(prop): # Process the list as pairs of (phandle, id) it = iter(prop.value) for phandle_cell, id_cell in zip(it, it): phandle = fdt_util.fdt32_to_cpu(phandle_cell) id = fdt_util.fdt32_to_cpu(id_cell) target_node = self._phandle_node[phandle] name = Conv_name_to_c(target_node.name) vals.append('{&%s%s, %d}' % (VAL_PREFIX, name, id)) else: for val in prop.value: vals.append(self.GetValue(prop.type, val)) self.Buf(', '.join(vals)) self.Buf('}') else: self.Buf(self.GetValue(prop.type, prop.value)) self.Buf(',\n') self.Buf('};\n') # Add a device declaration self.Buf('U_BOOT_DEVICE(%s) = {\n' % var_name) self.Buf('\t.name\t\t= "%s",\n' % struct_name) self.Buf('\t.platdata\t= &%s%s,\n' % (VAL_PREFIX, var_name)) self.Buf('\t.platdata_size\t= sizeof(%s%s),\n' % (VAL_PREFIX, var_name)) self.Buf('};\n') self.Buf('\n') # Output phandle target nodes first, since they may be referenced # by others if 'phandle' in node.props: self.Out(''.join(self.GetBuf())) else: node_txt_list.append(self.GetBuf()) # Output all the nodes which are not phandle targets themselves, but # may reference them. This avoids the need for forward declarations. for node_txt in node_txt_list: self.Out(''.join(node_txt)) -- 1.9.1

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[U-Boot] Veyron-speedy u-boot
by Riley Baird 22 Feb '17

22 Feb '17

Hi Simon, I've tried porting u-boot to the veyron-speedy Chromebook, based upon the veyron-minnie patch. I've attached a patch with my changes to this email. However, when I boot, all I get is a black screen. So, I have some questions: 1. Does u-boot show output to the laptop's screen, or do I have to make a serial console? 2. If I have to make a serial console, where do I do this/what is the pin layout? 3. Do I just have to sign u-boot-dtb.img with vbutil_kernel before dd-ing it onto a USB, or do I have to do something else to make the right image? Yours thankfully, Riley Baird

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[U-Boot] [PATCH 1/2] rsa: Fix build with OpenSSL 1.1.x
by Jelle van der Waa 22 Feb '17

22 Feb '17

The rsa_st struct has been made opaque in 1.1.x, add forward compatible code to access the n, e, d members of rsa_struct. EVP_MD_CTX_cleanup has been removed in 1.1.x and EVP_MD_CTX_reset should be called to reinitialise an already created structure. --- lib/rsa/rsa-sign.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 8c6637e328..965fb00f95 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -20,6 +20,19 @@ #define HAVE_ERR_REMOVE_THREAD_STATE #endif +#if OPENSSL_VERSION_NUMBER < 0x10100000L +void RSA_get0_key(const RSA *r, + const BIGNUM **n, const BIGNUM **e, const BIGNUM **d) +{ + if (n != NULL) + *n = r->n; + if (e != NULL) + *e = r->e; + if (d != NULL) + *d = r->d; +} +#endif + static int rsa_err(const char *msg) { unsigned long sslErr = ERR_get_error(); @@ -409,7 +422,11 @@ static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, ret = rsa_err("Could not obtain signature"); goto err_sign; } - EVP_MD_CTX_cleanup(context); + #if OPENSSL_VERSION_NUMBER < 0x10100000L + EVP_MD_CTX_cleanup(context); + #else + EVP_MD_CTX_reset(context); + #endif EVP_MD_CTX_destroy(context); EVP_PKEY_free(key); @@ -479,6 +496,7 @@ static int rsa_get_exponent(RSA *key, uint64_t *e) { int ret; BIGNUM *bn_te; + const BIGNUM *key_e; uint64_t te; ret = -EINVAL; @@ -487,17 +505,18 @@ static int rsa_get_exponent(RSA *key, uint64_t *e) if (!e) goto cleanup; - if (BN_num_bits(key->e) > 64) + RSA_get0_key(key, NULL, &key_e, NULL); + if (BN_num_bits(key_e) > 64) goto cleanup; - *e = BN_get_word(key->e); + *e = BN_get_word(key_e); - if (BN_num_bits(key->e) < 33) { + if (BN_num_bits(key_e) < 33) { ret = 0; goto cleanup; } - bn_te = BN_dup(key->e); + bn_te = BN_dup(key_e); if (!bn_te) goto cleanup; @@ -527,6 +546,7 @@ int rsa_get_params(RSA *key, uint64_t *exponent, uint32_t *n0_invp, { BIGNUM *big1, *big2, *big32, *big2_32; BIGNUM *n, *r, *r_squared, *tmp; + const BIGNUM *key_n; BN_CTX *bn_ctx = BN_CTX_new(); int ret = 0; @@ -548,7 +568,8 @@ int rsa_get_params(RSA *key, uint64_t *exponent, uint32_t *n0_invp, if (0 != rsa_get_exponent(key, exponent)) ret = -1; - if (!BN_copy(n, key->n) || !BN_set_word(big1, 1L) || + RSA_get0_key(key, NULL, &key_n, NULL); + if (!BN_copy(n, key_n) || !BN_set_word(big1, 1L) || !BN_set_word(big2, 2L) || !BN_set_word(big32, 32L)) ret = -1; -- 2.11.1

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[U-Boot] [PATCH v3 00/16] rk3188 uboot support
by Heiko Stuebner 22 Feb '17

22 Feb '17

Hi, this is meant as a status update and possible discussion for the core parts if needed. After talking with Simon and Tom the order is now also correct with tpl -> spl -> uboot. Status right now is: - the full uboot still works - the tpl/spl does start and is able to configure the ddr into a working state - The jump spl -> bootrom -> uboot doesn't work though On the other hand, Kever was able to make this work, booting from nand when building the image with a very ancient tool. All newer tools (including boot_merger.c from Rockchip's uboot) do not produce working images. But it is possible to produce a working sd-boot image using the proprietary 1st-stage loader. See the temporary mkuboot script in the last patch, which can create both types of images now (especially wrt. the needed rc4 encryption of everything). Combining this (it does work using some special tool), it looks like there is still some minor glitch in the way we build the spl image somewhere. Heiko Stuebner (16): dm: allow limiting pre-reloc markings to spl or tpl rockchip: move bootrom helper compilation to a hidden option rockchip: mkimage: Allow encoding of loader code in spl images rockchip: mkimage: Add support rk3188 serial rockchip: serial: Adapt rockchip of-platdata driver for rk3188 rockchip: rk3188: Add header files for PMU and GRF rockchip: rk3188: Add pinctrl driver rockchip: rk3188: Add sysreset driver rockchip: rk3188: Add rk3066/rk3188 clock bindings rockchip: rk3188: Add clock driver rockchip: rk3188: Add core devicetree files rockchip: rk3188: Add core support rockchip: rk3188: Add sdram driver rockchip: rk3188: Add main, spl and tpl boards rockchip: rk3188: Add Radxa Rock board Add a temporary script that can create a bootimage for rk3188 arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3188-radxarock.dts | 382 +++++++++ arch/arm/dts/rk3188.dtsi | 601 +++++++++++++++ arch/arm/dts/rk3xxx.dtsi | 417 ++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 191 +++++ arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 22 + arch/arm/include/asm/arch-rockchip/grf_rk3188.h | 589 ++++++++++++++ arch/arm/include/asm/arch-rockchip/pmu_rk3188.h | 36 + arch/arm/mach-rockchip/Kconfig | 20 + arch/arm/mach-rockchip/Makefile | 14 +- arch/arm/mach-rockchip/rk3188-board-spl.c | 220 ++++++ arch/arm/mach-rockchip/rk3188-board-tpl.c | 87 +++ arch/arm/mach-rockchip/rk3188-board.c | 71 ++ arch/arm/mach-rockchip/rk3188/Kconfig | 35 + arch/arm/mach-rockchip/rk3188/Makefile | 11 + arch/arm/mach-rockchip/rk3188/clk_rk3188.c | 33 + arch/arm/mach-rockchip/rk3188/sdram_rk3188.c | 985 ++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3188/syscon_rk3188.c | 55 ++ board/radxa/rock/Kconfig | 15 + board/radxa/rock/MAINTAINERS | 6 + board/radxa/rock/Makefile | 7 + board/radxa/rock/rock.c | 7 + configs/rock_defconfig | 56 ++ doc/driver-model/README.txt | 4 + drivers/clk/at91/pmc.c | 3 +- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk3188.c | 523 +++++++++++++ drivers/core/root.c | 2 +- drivers/core/util.c | 29 + drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/pinctrl-uclass.c | 3 +- drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3188.c | 611 +++++++++++++++ drivers/serial/serial_rockchip.c | 19 +- drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_rk3188.c | 47 ++ include/configs/rk3188_common.h | 125 +++ include/configs/rock.h | 30 + include/dm/util.h | 2 + include/dt-bindings/clock/rk3066a-cru.h | 32 + include/dt-bindings/clock/rk3188-cru-common.h | 256 ++++++ include/dt-bindings/clock/rk3188-cru.h | 48 ++ mkuboot | 35 + scripts/Makefile.spl | 7 +- tools/dtoc/dtoc.py | 2 + tools/rkcommon.c | 34 +- tools/rkcommon.h | 22 + tools/rkimage.c | 3 + tools/rksd.c | 4 + tools/rkspi.c | 4 + 50 files changed, 5707 insertions(+), 11 deletions(-) create mode 100644 arch/arm/dts/rk3188-radxarock.dts create mode 100644 arch/arm/dts/rk3188.dtsi create mode 100644 arch/arm/dts/rk3xxx.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3188.h create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3188.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3188.h create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3188.h create mode 100644 arch/arm/mach-rockchip/rk3188-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3188-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk3188-board.c create mode 100644 arch/arm/mach-rockchip/rk3188/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3188/Makefile create mode 100644 arch/arm/mach-rockchip/rk3188/clk_rk3188.c create mode 100644 arch/arm/mach-rockchip/rk3188/sdram_rk3188.c create mode 100644 arch/arm/mach-rockchip/rk3188/syscon_rk3188.c create mode 100644 board/radxa/rock/Kconfig create mode 100644 board/radxa/rock/MAINTAINERS create mode 100644 board/radxa/rock/Makefile create mode 100644 board/radxa/rock/rock.c create mode 100644 configs/rock_defconfig create mode 100644 drivers/clk/rockchip/clk_rk3188.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c create mode 100644 drivers/sysreset/sysreset_rk3188.c create mode 100644 include/configs/rk3188_common.h create mode 100644 include/configs/rock.h create mode 100644 include/dt-bindings/clock/rk3066a-cru.h create mode 100644 include/dt-bindings/clock/rk3188-cru-common.h create mode 100644 include/dt-bindings/clock/rk3188-cru.h create mode 100755 mkuboot -- 2.11.0

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[U-Boot] [PATCH 0/2] Series to clean handle_XXX() in f_dfu.c
by Patrick Delaunay 21 Feb '17

21 Feb '17

1/ DFU_GETSTATE response error when the DFU device state is requested using libusb with DFU_GETSTATUS a error is generated : LIBUSB_ERROR_IO I see the issue with my programmer tools based on dfu with libusb and I don't understood the actual code in U-Boot (req->actual is updated but not req->lenght ?) With the proposed patch, I aligned the code on the GETSTATUS behavior: the correct lenght is provided in req->lenght as the other answer and the issue is solved. PS: the issue not see with dfu-util as the existing function dfu_get_state() is never called in main (with dfu-util 0.9) But I can reproduce the same issue with patched version of dfu-util to add call to this function, on the dfu-util master branch diff --git a/src/main.c b/src/main.c index 7f31d4c..d99ace9 100644 --- a/src/main.c +++ b/src/main.c @@ -535,6 +535,13 @@ dfustate: } status_again: + printf("Determining device state: "); + ret = dfu_get_state(dfu_root->dev_handle, dfu_root->interface); + if (ret < 0) { + errx(EX_IOERR, "error get_state: %s", libusb_error_name(ret)); + } + printf("state = %s\n", dfu_state_to_string(ret)); + printf("Determining device status: "); ret = dfu_get_status(dfu_root, &status ); if (ret < 0) { 2/ harmonize handle_getstatus() with other function => add return value with size of the buffer as - handle_getstate() add in part 1 or existing functions - handle_dnload() - handle_upload() Patrick Delaunay (2): usb: gadget: dfu: correct size for USB_REQ_DFU_GETSTATE result usb: gadget: dfu: add result for handle_getstatus() drivers/usb/gadget/f_dfu.c | 56 ++++++++++++++++++++-------------------------- drivers/usb/gadget/f_dfu.h | 1 - 2 files changed, 24 insertions(+), 33 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] MCCMON6: defconfig: Move 'quiet' console parameter to 'console' env variable
by Lukasz Majewski 21 Feb '17

21 Feb '17

Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- include/configs/mccmon6.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index b16b837..8c72455 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -118,7 +118,7 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200\0" \ + "console=ttymxc0,115200 quiet\0" \ "fdtfile=imx6q-mccmon6.dtb\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -148,7 +148,7 @@ "boot_nor=" \ "setenv kernelnor 0x08180000;" \ "setenv dtbnor 0x09980000;" \ - "setenv bootargs console=${console} quiet " \ + "setenv bootargs console=${console} " \ ""MTDPARTS_DEFAULT" " \ "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \ "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \ -- 2.1.4

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[U-Boot] socfpga qspi issues on SoCKit devkit
by Rush, Jason A. 21 Feb '17

21 Feb '17

The QSPI NOR interface on the Altera Cyclone V SoCKit devkit (Rev B) appears to be broken in the current release. I've tracked it down to working in the v2016.07 release, but broken in the the v2016.09 release. With the help of git bisect, I tracked down the commit that breaks the QSPI to the following: commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1 Author: Vignesh R <vigneshr(a)ti.com> Date: Wed Jul 6 10:20:55 2016 +0530 spi: cadence_qspi_apb: Support 32 bit AHB address AHB address can be as long as 32 bit, hence remove the CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT and read as u32 value, it anyway does not make sense to mask upper bits. Signed-off-by: Vignesh R <vigneshr(a)ti.com> Tested-by: Marek Vasut <marex(a)denx.de> Acked-by: Marek Vasut <marex(a)denx.de> Reviewed-by: Jagan Teki <jteki(a)openedev.com> When I try and read anything from the QSPI on the dac3bf20fb2c9b03476be0d73db620f62ab3cee1 commit I get a "data abort" and the CPU resets. Example output below is from a clean build of U-Boot configured with socfpga_sockit_defconfig: => sf probe SF: Detected N25Q1024 with page size 256 Bytes, erase size 64 KiB, total 128 MiB => sf read 0x2000000 0x50000 0x5000 device 0 offset 0x50000, size 0x5000 data abort pc : [<3ff7a9bc>] lr : [<3ff98359>] reloc pc : [<010249fc>] lr : [<01042399>] sp : 3bf4fde8 ip : 3ff7a371 fp : 00000002 r10: 00000000 r9 : 3bf54ee8 r8 : 3bf55530 r7 : 0000270d r6 : 02000000 r5 : 00005000 r4 : 3bf55530 r3 : 00000004 r2 : 00000000 r1 : 02000000 r0 : ffa00000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... When I run the same commands with the previous commit in the git log (fdf02a36c52cb96717b64113775c4251ecd49596) I get the following output: => sf probe SF: Detected N25Q1024 with page size 256 Bytes, erase size 64 KiB, total 128 MiB => sf read 0x2000000 0x50000 0x5000 device 0 offset 0x50000, size 0x5000 SF: 20480 bytes @ 0x50000 Read: OK => I've done some investigation, and previously the ahbbase was masked so the value 0xFFA0_0000 results in 0x0 when writing the CQSPI_REG_INDIRECTTRIGGER register. I assume the above commit works on some boards, but it appears to break the socfpga arch. Is there someone that could help investigate or confirm this? Thanks, Jason

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[U-Boot] [PATCH v1] sun8i_emac: configure PHY reset GPIO via DM
by Philipp Tomsich 21 Feb '17

21 Feb '17

This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. For easier migration for the Designware driver, the prefix of DTB entries has simply been changed from 'snps,' to 'allwinner,': i.e. 'snps,reset-gpio' became 'allwinner,reset-gpio'. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- drivers/net/sun8i_emac.c | 85 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 79 insertions(+), 6 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 5094dd8..664d585 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -1,98 +1,101 @@ /* * (C) Copyright 2016 * Author: Amit Singh Tomar, amittomer25(a)gmail.com * * SPDX-License-Identifier: GPL-2.0+ * * Ethernet driver for H3/A64/A83T based SoC's * * It is derived from the work done by * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS! * */ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> #include <common.h> #include <dm.h> #include <fdt_support.h> #include <linux/err.h> #include <malloc.h> #include <miiphy.h> #include <net.h> +#ifdef CONFIG_DM_GPIO +#include <asm-generic/gpio.h> +#endif #define MDIO_CMD_MII_BUSY BIT(0) #define MDIO_CMD_MII_WRITE BIT(1) #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12 #define MDIO_CMD_MDC_DIV_RATIO_M_SHIFT 20 #define MDIO_CMD_MDC_DIV_16 (0 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT) #define MDIO_CMD_MDC_DIV_32 (1 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT) #define MDIO_CMD_MDC_DIV_64 (2 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT) #define MDIO_CMD_MDC_DIV_128 (3 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT) #define CONFIG_TX_DESCR_NUM 32 #define CONFIG_RX_DESCR_NUM 32 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */ /* * The datasheet says that each descriptor can transfers up to 4096 bytes * But later, the register documentation reduces that value to 2048, * using 2048 cause strange behaviours and even BSP driver use 2047 */ #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */ #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) #define H3_EPHY_DEFAULT_VALUE 0x58000 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15) #define H3_EPHY_ADDR_SHIFT 20 #define REG_PHY_ADDR_MASK GENMASK(4, 0) #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ #define SC_RMII_EN BIT(13) #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */ #define SC_ETCS_MASK GENMASK(1, 0) #define SC_ETCS_EXT_GMII 0x1 #define SC_ETCS_INT_GMII 0x2 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) #define AHB_GATE_OFFSET_EPHY 0 #if defined(CONFIG_MACH_SUN8I_H3) #define SUN8I_GPD8_GMAC 2 #else #define SUN8I_GPD8_GMAC 4 #endif /* H3/A64 EMAC Register's offset */ #define EMAC_CTL0 0x00 #define EMAC_CTL1 0x04 #define EMAC_INT_STA 0x08 #define EMAC_INT_EN 0x0c #define EMAC_TX_CTL0 0x10 #define EMAC_TX_CTL1 0x14 #define EMAC_TX_FLOW_CTL 0x1c #define EMAC_TX_DMA_DESC 0x20 #define EMAC_RX_CTL0 0x24 #define EMAC_RX_CTL1 0x28 #define EMAC_RX_DMA_DESC 0x34 #define EMAC_MII_CMD 0x48 #define EMAC_MII_DATA 0x4c #define EMAC_ADDR0_HIGH 0x50 #define EMAC_ADDR0_LOW 0x54 #define EMAC_TX_DMA_STA 0xb0 #define EMAC_TX_CUR_DESC 0xb4 #define EMAC_TX_CUR_BUF 0xb8 #define EMAC_RX_DMA_STA 0xc0 #define EMAC_RX_CUR_DESC 0xc4 @@ -114,91 +117,103 @@ struct emac_dma_desc { struct emac_eth_dev { struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM]; struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM]; char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); u32 interface; u32 phyaddr; u32 link; u32 speed; u32 duplex; u32 phy_configured; u32 tx_currdescnum; u32 rx_currdescnum; u32 addr; u32 tx_slot; bool use_internal_phy; enum emac_variant variant; void *mac_reg; phys_addr_t sysctl_reg; struct phy_device *phydev; struct mii_dev *bus; +#ifdef CONFIG_DM_GPIO + struct gpio_desc reset_gpio; +#endif +}; + + +struct sun8i_eth_pdata { + struct eth_pdata eth_pdata; + u32 reset_delays[3]; }; + static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { - struct emac_eth_dev *priv = bus->priv; + struct udevice *dev = bus->priv; + struct emac_eth_dev *priv = dev_get_priv(dev); ulong start; u32 miiaddr = 0; int timeout = CONFIG_MDIO_TIMEOUT; miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & MDIO_CMD_MII_PHY_REG_ADDR_MASK; miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & MDIO_CMD_MII_PHY_ADDR_MASK; /* The MAC block is fed by a 300MHz clock, so we need to divide by 128 to bring the MDC into the range permissible by the IEEE standard. */ miiaddr |= MDIO_CMD_MDC_DIV_128; miiaddr |= MDIO_CMD_MII_BUSY; writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); start = get_timer(0); while (get_timer(start) < timeout) { if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY)) return readl(priv->mac_reg + EMAC_MII_DATA); udelay(10); }; return -1; } static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val) { - struct emac_eth_dev *priv = bus->priv; + struct udevice *dev = bus->priv; + struct emac_eth_dev *priv = dev_get_priv(dev); ulong start; u32 miiaddr = 0; int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & MDIO_CMD_MII_PHY_REG_ADDR_MASK; miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & MDIO_CMD_MII_PHY_ADDR_MASK; miiaddr |= MDIO_CMD_MII_WRITE; miiaddr |= MDIO_CMD_MII_BUSY; /* The MAC block is fed by a 300MHz clock, so we need to divide by 128 to bring the MDC into the range permissible by the IEEE standard. */ miiaddr |= MDIO_CMD_MDC_DIV_128; writel(val, priv->mac_reg + EMAC_MII_DATA); writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); start = get_timer(0); while (get_timer(start) < timeout) { if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY)) { ret = 0; break; } udelay(10); }; return ret; } @@ -610,20 +625,57 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); } -static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv) +#if defined(CONFIG_DM_GPIO) +static int sun8i_mdio_reset(struct mii_dev *bus) +{ + struct udevice *dev = bus->priv; + struct emac_eth_dev *priv = dev_get_priv(dev); + struct sun8i_eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + if (!dm_gpio_is_valid(&priv->reset_gpio)) + return 0; + + /* reset the phy */ + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) + return ret; + + udelay(pdata->reset_delays[0]); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) + return ret; + + udelay(pdata->reset_delays[1]); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) + return ret; + + udelay(pdata->reset_delays[2]); + + return 0; +} +#endif + +static int sun8i_mdio_init(const char *name, struct udevice *priv) { struct mii_dev *bus = mdio_alloc(); if (!bus) { debug("Failed to allocate MDIO bus\n"); return -ENOMEM; } bus->read = sun8i_mdio_read; bus->write = sun8i_mdio_write; snprintf(bus->name, sizeof(bus->name), name); bus->priv = (void *)priv; +#if defined(CONFIG_DM_GPIO) + bus->reset = sun8i_mdio_reset; +#endif return mdio_register(bus); } @@ -695,16 +747,16 @@ static void sun8i_emac_eth_stop(struct udevice *dev) static int sun8i_emac_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct emac_eth_dev *priv = dev_get_priv(dev); priv->mac_reg = (void *)pdata->iobase; sun8i_emac_board_setup(priv); sun8i_emac_set_syscon(priv); - sun8i_mdio_init(dev->name, priv); + sun8i_mdio_init(dev->name, dev); priv->bus = miiphy_get_dev_by_name(dev->name); return sun8i_phy_init(priv, dev); } @@ -719,55 +771,76 @@ static const struct eth_ops sun8i_emac_eth_ops = { static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_platdata(dev); + struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); + struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; struct emac_eth_dev *priv = dev_get_priv(dev); const char *phy_mode; int node = dev_of_offset(dev); int offset = 0; +#ifdef CONFIG_DM_GPIO + int reset_flags = GPIOD_IS_OUT; + int ret = 0; +#endif pdata->iobase = dev_get_addr_name(dev, "emac"); priv->sysctl_reg = dev_get_addr_name(dev, "syscon"); pdata->phy_interface = -1; priv->phyaddr = -1; priv->use_internal_phy = false; offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy"); if (offset > 0) priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); printf("phy interface%d\n", pdata->phy_interface); if (pdata->phy_interface == -1) { debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } priv->variant = dev_get_driver_data(dev); if (!priv->variant) { printf("%s: Missing variant '%s'\n", __func__, (char *)priv->variant); return -EINVAL; } if (priv->variant == H3_EMAC) { if (fdt_getprop(gd->fdt_blob, node, "allwinner,use-internal-phy", NULL)) priv->use_internal_phy = true; } priv->interface = pdata->phy_interface; if (!priv->use_internal_phy) parse_phy_pins(dev); +#ifdef CONFIG_DM_GPIO + if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, + "allwinner,reset-active-low")) + reset_flags |= GPIOD_ACTIVE_LOW; + + ret = gpio_request_by_name(dev, "allwinner,reset-gpio", 0, + &priv->reset_gpio, reset_flags); + + if (ret == 0) { + ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "allwinner,reset-delays-us", sun8i_pdata->reset_delays, 3); + } else if (ret == -ENOENT) { + ret = 0; + } +#endif + return 0; } @@ -783,11 +856,11 @@ static const struct udevice_id sun8i_emac_eth_ids[] = { U_BOOT_DRIVER(eth_sun8i_emac) = { .name = "eth_sun8i_emac", .id = UCLASS_ETH, .of_match = sun8i_emac_eth_ids, .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata, .probe = sun8i_emac_eth_probe, .ops = &sun8i_emac_eth_ops, .priv_auto_alloc_size = sizeof(struct emac_eth_dev), - .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -- 1.9.1

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[U-Boot] [PATCH v1 0/2] sun8i_emac: set MDC divider for MDIO read/write
by Philipp Tomsich 21 Feb '17

21 Feb '17

To ensure compatibility with all PHYs, we need to keep the MDIO clock (MDC) below 2.5MHz (the guaranteed operating limit from IEEE 802.3), even if some PHYs will tolerate higher speeds. This changeset also cleans up the MDIO read/write functions by removing pointless bit-masking in a variable initialised to 0. Philipp Tomsich (2): sun8i_emac: Set MDC divider for MDIO read/write sun8i_emac: remove unnecessary bit-masking for mdio_read/write drivers/net/sun8i_emac.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) -- 1.9.1

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