January 2017 - U-Boot

[U-Boot] [PATCH 1/2] spi: Zap ep93xx_spi driver and related code
by Jagan Teki 04 Jan '17

04 Jan '17

Dropped becuase - driver and related configs not used any board. - no dm conversion. Cc: Heiko Schocher <hs(a)denx.de> Cc: Sergey Kostanbaev <sergey.kostanbaev(a)gmail.com> Signed-off-by: Jagan Teki <jagan(a)openedev.com> --- board/cirrus/edb93xx/edb93xx.c | 98 --------------- drivers/spi/Makefile | 1 - drivers/spi/ep93xx_spi.c | 272 ----------------------------------------- include/configs/edb93xx.h | 10 -- scripts/config_whitelist.txt | 4 - 5 files changed, 385 deletions(-) delete mode 100644 drivers/spi/ep93xx_spi.c diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c index 8963d3a..51ff162 100644 --- a/board/cirrus/edb93xx/edb93xx.c +++ b/board/cirrus/edb93xx/edb93xx.c @@ -282,101 +282,3 @@ int dram_init(void) gd->ram_size = dram_init_banksize_int(1); return 0; } - - -#ifdef CONFIG_EP93XX_SPI -#include <spi.h> - -/* - * EGIO0-EGIPO7 -> port A - * EGIO8-EGIP15 -> port B - */ - -static void ep93xx_set_epgio(unsigned num) -{ - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; - if (num < 8) - writel(readl(&regs->padr) | (1<<num), &regs->padr); - else - writel(readl(&regs->pbdr) | (1<<(num-8)), &regs->pbdr); -} - -static void ep93xx_clear_epgio(unsigned num) -{ - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; - if (num < 8) - writel(readl(&regs->padr) & (~(1<<num)), &regs->padr); - else - writel(readl(&regs->pbdr) & (~(1<<(num-8))), &regs->pbdr); -} - -static void ep93xx_dir_epgio_out(unsigned num) -{ - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; - if (num < 8) - writel(readl(&regs->paddr) | (1<<num), &regs->paddr); - else - writel(readl(&regs->pbddr) | (1<<(num-8)), &regs->pbddr); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - if (bus == 0 && cs < 16) - return 1; - - return 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - ep93xx_clear_epgio(slave->cs); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - ep93xx_set_epgio(slave->cs); -} - -#ifdef CONFIG_MMC_SPI -#include <mmc.h> - -#ifndef CONFIG_MMC_SPI_CS_EPGIO -# define CONFIG_MMC_SPI_CS_EPGIO 4 -#endif - -#ifndef CONFIG_MMC_SPI_SPEED -# define CONFIG_MMC_SPI_SPEED 25000000 -#endif - -#ifndef CONFIG_MMC_SPI_MODE -# define CONFIG_MMC_SPI_MODE SPI_MODE_0 -#endif - -int board_mmc_init(bd_t *bis) -{ - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; - - ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO); - ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO); - -#ifdef CONFIG_MMC_SPI_POWER_EGPIO - ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO); - ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO); -#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO) - ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO); - ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO); -#endif - struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO, - CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE); - - if (!mmc) { - printf("Failed to create MMC Device\n"); - return 1; - } - mmc_init(mmc); - return 0; -} - - -#endif /* CONFIG_MMC_SPI */ -#endif /* CONFIG_EP93XX_SPI */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c1ce158..521911b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_CF_QSPI) += cf_qspi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o -obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o diff --git a/drivers/spi/ep93xx_spi.c b/drivers/spi/ep93xx_spi.c deleted file mode 100644 index cb682dd..0000000 --- a/drivers/spi/ep93xx_spi.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * SPI Driver for EP93xx - * - * Copyright (C) 2013 Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru> - * - * Inspired form linux kernel driver and atmel uboot driver - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <spi.h> -#include <malloc.h> - -#include <asm/io.h> - -#include <asm/arch/ep93xx.h> - -#define SSPBASE SPI_BASE - -#define SSPCR0 0x0000 -#define SSPCR0_MODE_SHIFT 6 -#define SSPCR0_SCR_SHIFT 8 -#define SSPCR0_SPH BIT(7) -#define SSPCR0_SPO BIT(6) -#define SSPCR0_FRF_SPI 0 -#define SSPCR0_DSS_8BIT 7 - -#define SSPCR1 0x0004 -#define SSPCR1_RIE BIT(0) -#define SSPCR1_TIE BIT(1) -#define SSPCR1_RORIE BIT(2) -#define SSPCR1_LBM BIT(3) -#define SSPCR1_SSE BIT(4) -#define SSPCR1_MS BIT(5) -#define SSPCR1_SOD BIT(6) - -#define SSPDR 0x0008 - -#define SSPSR 0x000c -#define SSPSR_TFE BIT(0) -#define SSPSR_TNF BIT(1) -#define SSPSR_RNE BIT(2) -#define SSPSR_RFF BIT(3) -#define SSPSR_BSY BIT(4) -#define SSPCPSR 0x0010 - -#define SSPIIR 0x0014 -#define SSPIIR_RIS BIT(0) -#define SSPIIR_TIS BIT(1) -#define SSPIIR_RORIS BIT(2) -#define SSPICR SSPIIR - -#define SSPCLOCK 14745600 -#define SSP_MAX_RATE (SSPCLOCK / 2) -#define SSP_MIN_RATE (SSPCLOCK / (254 * 256)) - -/* timeout in milliseconds */ -#define SPI_TIMEOUT 5 -/* maximum depth of RX/TX FIFO */ -#define SPI_FIFO_SIZE 8 - -struct ep93xx_spi_slave { - struct spi_slave slave; - - unsigned sspcr0; - unsigned sspcpsr; -}; - -static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave) -{ - return container_of(slave, struct ep93xx_spi_slave, slave); -} - -void spi_init() -{ -} - -static inline void ep93xx_spi_write_u8(u16 reg, u8 value) -{ - writel(value, (unsigned int *)(SSPBASE + reg)); -} - -static inline u8 ep93xx_spi_read_u8(u16 reg) -{ - return readl((unsigned int *)(SSPBASE + reg)); -} - -static inline void ep93xx_spi_write_u16(u16 reg, u16 value) -{ - writel(value, (unsigned int *)(SSPBASE + reg)); -} - -static inline u16 ep93xx_spi_read_u16(u16 reg) -{ - return (u16)readl((unsigned int *)(SSPBASE + reg)); -} - -static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode, - struct ep93xx_spi_slave *slave) -{ - unsigned cpsr, scr; - - if (rate > SSP_MAX_RATE) - rate = SSP_MAX_RATE; - - if (rate < SSP_MIN_RATE) - return -1; - - /* Calculate divisors so that we can get speed according the - * following formula: - * rate = spi_clock_rate / (cpsr * (1 + scr)) - * - * cpsr must be even number and starts from 2, scr can be any number - * between 0 and 255. - */ - for (cpsr = 2; cpsr <= 254; cpsr += 2) { - for (scr = 0; scr <= 255; scr++) { - if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) { - /* Set CHPA and CPOL, SPI format and 8bit */ - unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) | - SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT; - if (mode & SPI_CPHA) - sspcr0 |= SSPCR0_SPH; - if (mode & SPI_CPOL) - sspcr0 |= SSPCR0_SPO; - - slave->sspcr0 = sspcr0; - slave->sspcpsr = cpsr; - return 0; - } - } - } - - return -1; -} - -void spi_set_speed(struct spi_slave *slave, unsigned int hz) -{ - struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); - - unsigned int mode = 0; - if (as->sspcr0 & SSPCR0_SPH) - mode |= SPI_CPHA; - if (as->sspcr0 & SSPCR0_SPO) - mode |= SPI_CPOL; - - ep93xx_spi_init_hw(hz, mode, as); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct ep93xx_spi_slave *as; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs); - if (!as) - return NULL; - - if (ep93xx_spi_init_hw(max_hz, mode, as)) { - free(as); - return NULL; - } - - return &as->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); - - free(as); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); - - /* Enable the SPI hardware */ - ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE); - - - ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr); - ep93xx_spi_write_u16(SSPCR0, as->sspcr0); - - debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n", - slave->cs, as->sspcpsr, as->sspcr0); - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - /* Disable the SPI hardware */ - ep93xx_spi_write_u8(SSPCR1, 0); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - unsigned int len_tx; - unsigned int len_rx; - unsigned int len; - u32 status; - const u8 *txp = dout; - u8 *rxp = din; - u8 value; - - debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n", - slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen); - - - if (bitlen == 0) - /* Finish any previously submitted transfers */ - goto out; - - if (bitlen % 8) { - /* Errors always terminate an ongoing transfer */ - flags |= SPI_XFER_END; - goto out; - } - - len = bitlen / 8; - - - if (flags & SPI_XFER_BEGIN) { - /* Empty RX FIFO */ - while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE)) - ep93xx_spi_read_u8(SSPDR); - - spi_cs_activate(slave); - } - - for (len_tx = 0, len_rx = 0; len_rx < len; ) { - status = ep93xx_spi_read_u8(SSPSR); - - if ((len_tx < len) && (status & SSPSR_TNF)) { - if (txp) - value = *txp++; - else - value = 0xff; - - ep93xx_spi_write_u8(SSPDR, value); - len_tx++; - } - - if (status & SSPSR_RNE) { - value = ep93xx_spi_read_u8(SSPDR); - - if (rxp) - *rxp++ = value; - len_rx++; - } - } - -out: - if (flags & SPI_XFER_END) { - /* - * Wait until the transfer is completely done before - * we deactivate CS. - */ - do { - status = ep93xx_spi_read_u8(SSPSR); - } while (status & SSPSR_BSY); - - spi_cs_deactivate(slave); - } - - return 0; -} diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index a83c617..9080b9a 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -229,16 +229,6 @@ #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -/* Define to enable MMC on SPI support */ -/* #define CONFIG_EP93XX_SPI_MMC */ - -#ifdef CONFIG_EP93XX_SPI_MMC -#define CONFIG_EP93XX_SPI -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC_SPI -#define CONFIG_MMC_SPI_NPOWER_EGPIO 9 -#endif - #define CONFIG_USB_OHCI_NEW #define CONFIG_USB_OHCI_EP93XX #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 6d614c6..2533e26 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1098,8 +1098,6 @@ CONFIG_EP9312 CONFIG_EP9315 CONFIG_EP93XX CONFIG_EP93XX_NO_FLASH_CFG -CONFIG_EP93XX_SPI -CONFIG_EP93XX_SPI_MMC CONFIG_EPH_POWER_EN CONFIG_EPOLL CONFIG_ESBC_ADDR_64BIT @@ -3078,8 +3076,6 @@ CONFIG_MMC_SPI_CRC_ON CONFIG_MMC_SPI_CS CONFIG_MMC_SPI_CS_EPGIO CONFIG_MMC_SPI_MODE -CONFIG_MMC_SPI_NPOWER_EGPIO -CONFIG_MMC_SPI_POWER_EGPIO CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI CONFIG_MMC_SUNXI_SLOT -- 1.9.1

2 2

[U-Boot] [PATCH] ARM: omap3_logic: Add scripts to program NAND
by Adam Ford 04 Jan '17

04 Jan '17

This patch adds scripts to burn the kernel, U-Boot, and MLO to NAND. The RootFS needs to be added and programmed from the kernel for now. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 90faaf4..632885a 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -227,7 +227,33 @@ "nandbootz=run nandbootcommon; "\ "bootz ${loadaddr} - ${fdtaddr}\0"\ "nandboot=run nandbootcommon; "\ - "bootm ${loadaddr} - ${fdtaddr}\0"\ + "bootm ${loadaddr} - ${fdtaddr}\0" \ + "nandburnkernel=echo 'Burn Image to NAND...'; "\ + "nand unlock;" \ + "echo 'Erasing Kernel partition...';" \ + "nand erase.part kernel; "\ + "run loadimage; " \ + "echo 'Flashing Kernel partition...';" \ + "nand write ${loadaddr} kernel ${filesize}; \0" \ + "nandburnzimage=setenv bootfile zImage; run nandburnkernel\0"\ + "nandburnuimage=setenv bootfile uImage; run nandburnkernel\0"\ + "nandburnuboot=echo 'Burn U-Boot to NAND...'; " \ + "nand unlock;" \ + "echo 'Erasing U-Boot partition...';" \ + "nand erase.part u-boot; "\ + "mmc rescan; " \ + "load mmc ${mmcdev} ${loadaddr} u-boot.img; " \ + "echo 'Flashing U-Boot partition...';" \ + "nand write ${loadaddr} u-boot ${filesize};\0" \ + "nandburnmlo=echo 'Burn MLO to NAND...'; " \ + "nand unlock;" \ + "echo 'Erasing MLO partition...';" \ + "nand erase.part MLO; "\ + "mmc rescan; " \ + "load mmc ${mmcdev} ${loadaddr} MLO; " \ + "nandecc hw;" \ + "echo 'Flashing MLO partition...';" \ + "nand write ${loadaddr} MLO ${filesize};\0" #define CONFIG_BOOTCOMMAND \ "run autoboot" -- 2.7.4

2 2

[U-Boot] [PATCH 1/2][RESEND] armv8:ls2080a: Reorganise NAND_BOOT code in config flag
by Priyanka Jain 04 Jan '17

04 Jan '17

Add CONFIG_NAND_BOOT config flag to organise NAND_BOOT specific code in config flag like -nand-boot specfic errata errata_rcw_src() -CONFIG_SYS_NAND_U_BOOT_DST,etc Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080ardb_nand_defconfig | 2 +- include/configs/ls2080a_common.h | 4 ++++ include/configs/ls2080aqds.h | 4 +++- 5 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d43361f..73a751d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -134,7 +134,7 @@ void erratum_a009635(void) static void erratum_rcw_src(void) { -#if defined(CONFIG_SPL) +#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT) u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; u32 val; diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 2161815..5e7bea5 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, NAND_BOOT, LS2080A" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index e40152e..d6633c3 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, NAND_BOOT, LS2080A" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 2cae966..3828058 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -250,6 +250,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_PANIC_HANG /* do not reset board on panic */ +#ifdef CONFIG_SPL #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 #define CONFIG_SPL_FRAMEWORK @@ -259,11 +260,14 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_TEXT_BASE 0x1800a000 +#ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#endif #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 #define CONFIG_SYS_MONITOR_LEN (640 * 1024) +#endif #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 838568f..a87d13a 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -202,7 +202,8 @@ unsigned long get_board_ddr_clk(void); FTIM2_GPCM_TWP(0x3E)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_SPL) && defined(CONFIG_NAND) +#if defined(CONFIG_SPL) +#if defined(CONFIG_NAND_BOOT) #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR @@ -238,6 +239,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) +#endif #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -- 1.7.4.1

2 2

[U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node
by Wenbin song 04 Jan '17

04 Jan '17

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. The rev1.0 silicon only supports the CIG offset with 4K alignment. GIC offset is decided by SVR and GIC_ADDR_BIT bit. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. Signed-off-by: Wenbin Song <wenbin.song(a)nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu(a)nxp.com> --- Changes in v6: Add comments around checking the revision. Changes in v5: Replace fix_gic_off with get_gic_off. Add #if condition to check CONFIG_GICV2 and CONFIG_GICV3 on smp_kick_all_cpus. Fixup gic node with 64K alignment when running on rev1.1 with GIC_ADDR_BIT cleared. --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 71 ++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 57 +++++++++++++++-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 26 +++++++- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +- 5 files changed, 154 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 94ec8d5..f415868 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -135,4 +135,8 @@ config SYS_FSL_DDR4 help Enable Freescale DDR4 controller. +config HAS_FEATURE_GIC4K_ALIGN + bool + default y if ARCH_LS1043A + endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 1a8321b..9936be1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -126,6 +126,74 @@ void fsl_fdt_disable_usb(void *blob) } } +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN +static void fdt_fixup_gic(void *blob) +{ + int offset, err; + u64 reg[8]; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int rev; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + int align_4k = 1; + + rev = gur_in32(&gur->svr) & 0xff; + /* + * For ls1043a rev1.0, the GIC offset aligns with 4K. + * For ls1043a rev1.1 or more higher, the GIC offset + * is decided by gic_align register. + */ + + if (rev > REV1_0) { + /* + * The GIC_ADDR_BIT on gic_align was set by + * PBI to select GIC offset. + */ + rev = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT); + if (!rev) + align_4k = 0; + } + + offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000"); + if (offset < 0) { + printf("WARNING: fdt_subnode_offset can't find node %s: %s\n", + "interrupt-controller@1400000", fdt_strerror(offset)); + return; + } + + /* Fixup gic node align with 4K */ + if (align_4k) { + reg[0] = cpu_to_fdt64(GICD_BASE_4K); + reg[1] = cpu_to_fdt64(GICD_SIZE_4K); + reg[2] = cpu_to_fdt64(GICC_BASE_4K); + reg[3] = cpu_to_fdt64(GICC_SIZE_4K); + reg[4] = cpu_to_fdt64(GICH_BASE_4K); + reg[5] = cpu_to_fdt64(GICH_SIZE_4K); + reg[6] = cpu_to_fdt64(GICV_BASE_4K); + reg[7] = cpu_to_fdt64(GICV_SIZE_4K); + } else { + /* Fixup gic node align with 64K */ + reg[0] = cpu_to_fdt64(GICD_BASE); + reg[1] = cpu_to_fdt64(GICD_SIZE); + reg[2] = cpu_to_fdt64(GICC_BASE); + reg[3] = cpu_to_fdt64(GICC_SIZE); + reg[4] = cpu_to_fdt64(GICH_BASE); + reg[5] = cpu_to_fdt64(GICH_SIZE); + reg[6] = cpu_to_fdt64(GICV_BASE); + reg[7] = cpu_to_fdt64(GICV_SIZE); + } + + err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg)); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s\n", + "reg", "interrupt-controller@1400000", + fdt_strerror(err)); + return; + } + + return; +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FSL_LSCH2 @@ -170,4 +238,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif fsl_fdt_disable_usb(blob); +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN + fdt_fixup_gic(blob); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5d0b7a4..d50096c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -14,6 +14,55 @@ #include <asm/arch/mp.h> #endif + +/* Get GIC offset +* For LS1043a rev1.0, GIC base address align with 4k. +* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT] +* is set, GIC base address align with 4K, or else align +* with 64k. +* output: +* for GICv2: +* x0-> the base address of GICD +* x1-> the base address of GICC +* for GICv3: +* x0-> the base address of GICD +*/ +ENTRY(get_gic_offset) + ldr x0, =GICD_BASE +#ifdef CONFIG_GICV2 + ldr x1, =GICC_BASE +#endif +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN + ldr x3, =DCFG_CCSR_SVR + ldr w3, [x3] + rev w3, w3 + ands w3, w3, #0xff + cmp w3, #REV1_0 + b.eq 1f + ldr x3, =SCFG_GIC400_ALIGN + ldr w3, [x3] + rev w3, w3 + tbnz w3, #GIC_ADDR_BIT, 1f + ret +1: + ldr x0, =GICD_BASE_4K + ldr x1, =GICC_BASE_4K +#endif + ret +ENDPROC(get_gic_offset) + +ENTRY(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + mov x29, lr /* Save LR */ + bl get_gic_offset + bl gic_kick_secondary_cpus + mov lr, x29 /* Restore LR */ +#endif + ret +ENDPROC(smp_kick_all_cpus) + + ENTRY(lowlevel_init) mov x29, lr /* Save LR */ @@ -105,15 +154,14 @@ ENTRY(lowlevel_init) /* Initialize GIC Secure Bank Status */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f - ldr x0, =GICD_BASE + bl get_gic_offset bl gic_init_secure 1: #ifdef CONFIG_GICV3 ldr x0, =GICR_BASE bl gic_init_secure_percpu #elif defined(CONFIG_GICV2) - ldr x0, =GICD_BASE - ldr x1, =GICC_BASE + bl get_gic_offset bl gic_init_secure_percpu #endif #endif @@ -335,7 +383,8 @@ ENTRY(secondary_boot_func) #if defined(CONFIG_GICV3) gic_wait_for_interrupt_m x0 #elif defined(CONFIG_GICV2) - ldr x0, =GICC_BASE + bl get_gic_offset + mov x0, x1 gic_wait_for_interrupt_m x0, w1 #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 4201e0f..35f67dd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -172,8 +172,30 @@ #define SMMU_BASE 0x09000000 /* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x01401000 -#define GICC_BASE 0x01402000 +#define GICD_BASE 0x01410000 +#define GICC_BASE 0x01420000 +#define GICH_BASE 0x01440000 +#define GICV_BASE 0x01460000 +#define GICD_SIZE 0x10000 +#define GICC_SIZE 0x20000 +#define GICH_SIZE 0x20000 +#define GICV_SIZE 0x20000 +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN +#define GICD_BASE_4K 0x01401000 +#define GICC_BASE_4K 0x01402000 +#define GICH_BASE_4K 0x01404000 +#define GICV_BASE_4K 0x01406000 +#define GICD_SIZE_4K 0x1000 +#define GICC_SIZE_4K 0x2000 +#define GICH_SIZE_4K 0x2000 +#define GICV_SIZE_4K 0x2000 +#endif + +#define DCFG_CCSR_SVR 0x1ee00a4 +#define REV1_0 0x10 +#define REV1_1 0x11 +#define GIC_ADDR_BIT 31 +#define SCFG_GIC400_ALIGN 0x1570188 #define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d88543d..1dfef53 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -359,7 +359,8 @@ struct ccsr_scfg { u32 qspi_cfg; u8 res_160[0x180-0x160]; u32 dmamcr; - u8 res_184[0x18c-0x184]; + u8 res_184[0x188-0x184]; + u32 gic_align; u32 debug_icid; u8 res_190[0x1a4-0x190]; u32 snpcnfgcr; -- 2.1.0.27.g96db324

3 11

[U-Boot] final u-boot cleanup -- Makefiles testing non-existent CONFIG vars
by Robert P. J. Day 04 Jan '17

04 Jan '17

last example of cleanup script for today, i promise. one more cleanup script i wrote a while back identified something very specific; Makefiles that were testing CONFIG_ variables when those variables did not seem to be set anywhere. as in, if a Makefile contained the line: obj-$(CONFIG_RDAY) += rday.o it would only make sense that the variable "CONFIG_RDAY" would need to be set *somewhere* (or at the very least defined in a Kconfig file), otherwise, that file would never be compiled. i dumped the output of that script to the same wiki page: http://www.crashcourse.ca/wiki/index.php/U-Boot_Kconfig_cleanup it's the last section, and it might contain a few false positives since the Makefile itself might hardcode that variable, or might add a compilation option of "-DCONFIG_RDAY", and so on. for the most part, though, the list looks pretty good. as an example, there's this: >>>>> ALI152X ./drivers/misc/Makefile:obj-$(CONFIG_ALI152X) += ali512x.o that means that that Makefile is testing that variable, when it does not seem to be set by anything in the entire code base: $ grep -r ALI152X * drivers/misc/Makefile:obj-$(CONFIG_ALI152X) += ali512x.o $ here's another example: >>>>> CMD_FITUPD ./cmd/Makefile:obj-$(CONFIG_CMD_FITUPD) += fitupd.o absolutely nothing sets that variable, so that command will never be compiled into the image. one suspects that an entry for that command should be added to cmd/Kconfig, no? finally, here's an interesting example: >>>>> YAFFS2 ./fs/Makefile:obj-$(CONFIG_YAFFS2) += yaffs2/ ./cmd/Makefile:obj-$(CONFIG_YAFFS2) += yaffs2.o and if you search for the string "YAFFS2", you get: cmd/yaffs2.c:#ifdef YAFFS2_DEBUG cmd/Makefile:obj-$(CONFIG_YAFFS2) += yaffs2.o fs/yaffs2/yaffs_packedtags1.h:/* This is used to pack YAFFS1 tags, not YAFFS2 tags. */ fs/yaffs2/yaffs_guts.h:#define YAFFS_MIN_YAFFS2_CHUNK_SIZE 1024 fs/yaffs2/yaffs_guts.h:#define YAFFS_MIN_YAFFS2_SPARE_SIZE 32 fs/yaffs2/yaffs_guts.h:/* Sequence numbers are used in YAFFS2 to determine block allocation order. fs/yaffs2/yaffs_guts.h:/* Stuff used for extended tags in YAFFS2 */ fs/yaffs2/yaffs_guts.h: /* YAFFS2 stuff */ fs/yaffs2/yaffs_guts.h: /* Extra info if this is an object header (YAFFS2 only) */ fs/yaffs2/yaffs_guts.h: * However, if this state is returned on a YAFFS2 device, fs/yaffs2/yaffs_packedtags2.h:/* This is used to pack YAFFS2 tags, not YAFFS1tags. */ fs/yaffs2/Makefile: -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE \ fs/yaffs2/yaffs_yaffs2.h:#ifndef __YAFFS_YAFFS2_H__ fs/yaffs2/yaffs_yaffs2.h:#define __YAFFS_YAFFS2_H__ fs/yaffs2/yaffs_guts.c: * Correction for YAFFS2: This could happen quite a lot and we fs/yaffs2/yaffs_guts.c: * Backwards scanning YAFFS2: The old one is what fs/yaffs2/yaffs_guts.c: /* Handle YAFFS2 case (backward scanning) fs/yaffs2/yaffs_mtdif2.c:/* mtd interface for YAFFS2 */ fs/Makefile:obj-$(CONFIG_YAFFS2) += yaffs2/ scripts/config_whitelist.txt:CONFIG_YAFFS2 uh, this line looks interesting: fs/yaffs2/Makefile: -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE \ is that a typo? should it read: fs/yaffs2/Makefile: -DCONFIG_YAFFS2 -DNO_Y_INLINE \ anyway, that's it for today ... feel free to peruse that new list to see what parts of Makefiles seem to not be compiled. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ======================================================================== \

1 0

[U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942
by Hamish Martin 04 Jan '17

04 Jan '17

This erratum is already implemented for other ARM based QorIQ platforms with the Gen4 DDR controller. Port the fix to the Gen3 controller and enable it for T2080 and T2081. Reviewed-by: Chris Packham <chris.packham(a)alliedtelesis.co.nz> Signed-off-by: Hamish Martin <hamish.martin(a)alliedtelesis.co.nz> Cc: York Sun <york.sun(a)nxp.com> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 17 +++++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3b06ae42e4bc..94b6dcca96b6 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -329,6 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 puts("Work-around for Erratum A009663 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + puts("Work-around for Erratum A009942 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6d845e859f4a..9e1cd80e16e0 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -910,6 +910,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A009942 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define CONFIG_SYS_FSL_SFP_VER_3_0 diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 653b7f0c770c..a88884377f80 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -39,6 +39,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 u32 save1, save2; #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ulong ddr_freq; + u32 tmp; +#endif switch (ctrl_num) { case 0: @@ -183,6 +187,19 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->debug[21], 0x24000000); #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + tmp = in_be32(&ddr->debug[28]); + if (ddr_freq <= 1333) + out_be32(&ddr->debug[28], tmp | 0x0080006a); + else if (ddr_freq <= 1600) + out_be32(&ddr->debug[28], tmp | 0x0070006f); + else if (ddr_freq <= 1867) + out_be32(&ddr->debug[28], tmp | 0x00700076); + else if (ddr_freq <= 2133) + out_be32(&ddr->debug[28], tmp | 0x0060007b); +#endif + /* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is * deasserted. Clocks start when any chip select is enabled and clock -- 2.10.1

4 6

[U-Boot] [PATCH 1/2] SECURE_BOOT: Update bootscript and its address for LS Chasis 3
by Udit Agarwal 04 Jan '17

04 Jan '17

Update bootscript and its addresses for Layerscape Chasis 3 based platforms instead of individual SoCs. Signed-off-by: Sumit Garg <sumit.garg(a)nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal(a)nxp.com> --- arch/arm/include/asm/fsl_secure_boot.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 933e09c..f34ffc7 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -84,7 +84,7 @@ * Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD) */ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ defined(CONFIG_SD_BOOT) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif @@ -92,11 +92,11 @@ * The address needs to be modified according to NOR, NAND, SD and * DDR memory map */ -#ifdef CONFIG_LS2080A -#define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000 -#define CONFIG_BS_ADDR_DEVICE 0x583900000 -#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 -#define CONFIG_BS_ADDR_RAM 0xa3900000 +#ifdef CONFIG_FSL_LSCH3 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000 +#define CONFIG_BS_ADDR_DEVICE 0x580e00000 +#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000 +#define CONFIG_BS_ADDR_RAM 0xa0e00000 #define CONFIG_BS_HDR_SIZE 0x00002000 #define CONFIG_BS_SIZE 0x00001000 #else -- 1.9.1

2 3

[U-Boot] Kconfig cleanup -- identifying CONFIG variables not defined in any Kconfig file
by Robert P. J. Day 04 Jan '17

04 Jan '17

as a followup to my earlier post, one of my other linux kernel cleanup scripts was to identify "CONFIG_*" variables that *were* being tested in the source somewhere, but for which there was no definition for that variable in any Kconfig file. for example, if there exists a line: #if defined(CONFIG_RDAY) then one should expect some Kconfig file to contain the definition: config RDAY ... blah blah ... sadly, that doesn't work so well with u-boot given the plethora of CONFIG_* variables that are simply hard-coded in header files, rather than being defined in any Kconfig file. still, there seems to be a ton of that stuff; for example: $ grep -r CONFIG_I2CFAST * common/board_r.c:#if defined(CONFIG_I2CFAST) common/board_r.c:#endif /* CONFIG_I2CFAST */ README: CONFIG_I2CFAST (PPC405GP|PPC405EP only) scripts/config_whitelist.txt:CONFIG_I2CFAST $ so there we have a CONFIG variable that is clearly being tested, but does not seem to be defined *anywhere*, even hard-coded in a header file. however, since it exists, it ends up in the whitelist file. another short example: $ grep -r MTD_UBI_BLOCK * drivers/mtd/ubi/ubi.h:#ifdef CONFIG_MTD_UBI_BLOCK include/ubi_uboot.h:#undef CONFIG_MTD_UBI_BLOCK scripts/config_whitelist.txt:CONFIG_MTD_UBI_BLOCK $ anyway, there's plenty of that sort of thing scattered through the code base. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

1 0

[U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
by Vignesh R 04 Jan '17

04 Jan '17

According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts. So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr(a)ti.com> Reviewed-by: Marek Vasut <marex(a)denx.de> --- Resend v2: Rebased on latest rc. Link to v2:https://patchwork.ozlabs.org/patch/698614/ drivers/spi/cadence_qspi_apb.c | 26 ++++++++++++++++++++------ include/configs/k2g_evm.h | 1 + include/configs/socfpga_common.h | 1 + include/configs/stv0991.h | 1 + 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index df6a91fc9f7b..5d5b6f0d350b 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -30,6 +30,7 @@ #include <linux/errno.h> #include <wait_bit.h> #include <spi.h> +#include <bouncebuf.h> #include "cadence_qspi.h" #define CQSPI_REG_POLL_US 1 /* 1us */ @@ -724,6 +725,17 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, unsigned int remaining = n_tx; unsigned int write_bytes; int ret; + struct bounce_buffer bb; + u8 *bb_txbuf; + + /* + * Handle non-4-byte aligned accesses via bounce buffer to + * avoid data abort. + */ + ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ); + if (ret) + return ret; + bb_txbuf = bb.bounce_buffer; /* Configure the indirect read transfer bytes */ writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); @@ -734,11 +746,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; - /* Handle non-4-byte aligned access to avoid data abort. */ - if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) - writesb(plat->ahbbase, txbuf, write_bytes); - else - writesl(plat->ahbbase, txbuf, write_bytes >> 2); + writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2); + if (write_bytes % 4) + writesb(plat->ahbbase, + bb_txbuf + rounddown(write_bytes, 4), + write_bytes % 4); ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, CQSPI_REG_SDRAMLEVEL_WR_MASK << @@ -748,7 +760,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, goto failwr; } - txbuf += write_bytes; + bb_txbuf += write_bytes; remaining -= write_bytes; } @@ -759,6 +771,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, printf("Indirect write completion error (%i)\n", ret); goto failwr; } + bounce_buffer_stop(&bb); /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE, @@ -769,6 +782,7 @@ failwr: /* Cancel the indirect write */ writel(CQSPI_REG_INDIRECTWR_CANCEL, plat->regbase + CQSPI_REG_INDIRECTWR); + bounce_buffer_stop(&bb); return ret; } diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 2da0d8dd7f00..4f9c42abac7e 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -78,6 +78,7 @@ #define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_REF_CLK 384000000 #define CONFIG_CQSPI_DECODER 0x0 +#define CONFIG_BOUNCE_BUFFER #endif #endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 58a655084491..e50c2fac8d99 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -208,6 +208,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif #define CONFIG_CQSPI_DECODER 0 +#define CONFIG_BOUNCE_BUFFER /* * Designware SPI support diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index bfd1bd719285..09a3064bd6d6 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -74,6 +74,7 @@ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 +#define CONFIG_BOUNCE_BUFFER #endif -- 2.11.0

4 10

[U-Boot] [PATCH v2] mtd: nand: mxs_nand_spl: Fix to remove twise 'NAND' print
by Jagan Teki 04 Jan '17

04 Jan '17

SPL from nand will print 'NAND' in boot_from_devices based on the image_loader name, remove the extra 'NAND ' in mxs_nand_spl driver. Original behaviour: ------------------- U-Boot SPL 2017.01-rc2-gf84dd8b (Jan 02 2017 - 22:24:19) Trying to boot from NANDNAND : 512 MiB After the fix: ------------- U-Boot SPL 2017.01-rc2-gf84dd8b-dirty (Jan 02 2017 - 23:17:00) Trying to boot from NAND: 512 MiB Cc: Tom Rini <trini(a)konsulko.com> Signed-off-by: Jagan Teki <jagan(a)openedev.com> --- Changes for v2: - Fix commit message about fix logs drivers/mtd/nand/mxs_nand_spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c index ff28df4..b6c9208 100644 --- a/drivers/mtd/nand/mxs_nand_spl.c +++ b/drivers/mtd/nand/mxs_nand_spl.c @@ -153,7 +153,7 @@ static int mxs_nand_init(void) nand_chip.numchips = 1; /* identify flash device */ - puts("NAND : "); + puts(": "); if (mxs_flash_ident(mtd)) { printf("Failed to identify\n"); return -1; -- 1.9.1

1 1