January 2017 - U-Boot

[U-Boot] question about boot timing -- should it all depend on BOOTSTAGE?
by Robert P. J. Day 02 Jan '17

02 Jan '17

looking at another Kconfig file -- common/Kconfig -- and i find it curious that there are a couple BOOTSTAGE config options that don't depend on BOOTSTAGE: config BOOTSTAGE_USER_COUNT hex "Number of boot ID numbers available for user use" default 20 help This is the number of available user bootstage records. Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...) a new ID will be allocated from this stash. If you exceed the limit, recording will stop. ... snip ... config BOOTSTAGE_STASH_ADDR hex "Address to stash boot timing information" default 0 help Provide an address which will not be overwritten by the OS when it starts, so that it can read this information when ready. config BOOTSTAGE_STASH_SIZE hex "Size of boot timing stash region" default 4096 help This should be large enough to hold the bootstage stash. A value of 4096 (4KiB) is normally plenty. endmenu do those Kbuild options really not need BOOTSTAGE to be selected first? rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] why two "config FIT_VERBOSE" lines in top-level Kconfig?
by Robert P. J. Day 02 Jan '17

02 Jan '17

weird ... config FIT_VERBOSE bool "Display verbose messages on FIT boot" depends on FIT ... jump to a bit lower down ... config FIT_VERBOSE bool "Show verbose messages when FIT images fails" depends on FIT help Generally a system will have valid FIT images so debug messages are a waste of code space. If you are debugging your images then you can enable this option to get more verbose information about failures. this is really a lead-in to a larger question -- any objection to refactoring some of the Kconfig files that have numerous identical dependency lines which could be replaced by a simpler "if" test? that top-level Kconfig file is a candidate, given the number of "depends on FIT" lines that could be removed and surrounded by: if FIT ... endif and some Kconfig files have entries in a weird order such that, if you select a feature, dependent features suddenly pop up somewhere else in the display, a bit disconcerting. anyway, i'll post a refactored top-level Kconfig, so people can see what i'm talking about. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0
by Moritz Fischer 02 Jan '17

02 Jan '17

Revision 1.0 of this IP has a couple of issues, such as not supporting repeated start conditions for read transfers. So scan through the list of i2c messages for these conditions and report an error if they are attempted. This has been fixed for revision 1.4 of the IP, so only report the error when the IP can really not do it. Signed-off-by: Moritz Fischer <moritz.fischer(a)ettus.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: u-boot(a)lists.denx.de --- drivers/i2c/i2c-cdns.c | 69 ++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 55 insertions(+), 14 deletions(-) diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index f49f60b..c69e7e8 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -67,6 +67,7 @@ struct cdns_i2c_regs { #define CDNS_I2C_FIFO_DEPTH 16 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */ +#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) #ifdef DEBUG static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) @@ -114,6 +115,13 @@ struct i2c_cdns_bus { int id; unsigned int input_freq; struct cdns_i2c_regs __iomem *regs; /* register base */ + + int hold_flag; + u32 quirks; +}; + +struct cdns_i2c_platform_data { + u32 quirks; }; /* Wait for an interrupt */ @@ -236,18 +244,14 @@ static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr, } static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, - u32 len, bool next_is_read) + u32 len) { u8 *cur_data = data; struct cdns_i2c_regs *regs = i2c_bus->regs; - setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO | - CDNS_I2C_CONTROL_HOLD); + setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO); - /* if next is a read, we need to clear HOLD, doesn't work */ - if (next_is_read) - clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW); @@ -267,7 +271,9 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, } /* All done... release the bus */ - clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); + if (!i2c_bus->hold_flag) + clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); + /* Wait for the address and data to be sent */ if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) return -ETIMEDOUT; @@ -285,7 +291,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, struct cdns_i2c_regs *regs = i2c_bus->regs; /* Check the hardware can handle the requested bytes */ - if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX)) + if ((len < 0)) return -EINVAL; setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO | @@ -310,7 +316,8 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, *(cur_data++) = readl(&regs->data); } while (readl(&regs->transfer_size) != 0); /* All done... release the bus */ - clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); + if (!i2c_bus->hold_flag) + clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); #ifdef DEBUG cdns_i2c_debug_status(regs); @@ -322,19 +329,43 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) { struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); - int ret; + int ret, count; + bool hold_quirk; + + + printf("i2c_xfer: %d messages\n", nmsgs); + hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT); + + if (nmsgs > 1) { + /* + * This controller does not give completion interrupt after a + * master receive message if HOLD bit is set (repeated start), + * resulting in SW timeout. Hence, if a receive message is + * followed by any other message, an error is returned + * indicating that this sequence is not supported. + */ + for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) { + if (msg[count].flags & I2C_M_RD) { + printf("Can't do repeated start after a receive message\n"); + return -EOPNOTSUPP; + } + } + + i2c_bus->hold_flag = 1; + setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD); + } else { + i2c_bus->hold_flag = 0; + } debug("i2c_xfer: %d messages\n", nmsgs); for (; nmsgs > 0; nmsgs--, msg++) { - bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); - debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); if (msg->flags & I2C_M_RD) { ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf, msg->len); } else { ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, - msg->len, next_is_read); + msg->len); } if (ret) { debug("i2c_write: error sending\n"); @@ -348,11 +379,16 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, static int cdns_i2c_ofdata_to_platdata(struct udevice *dev) { struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); + struct cdns_i2c_platform_data *pdata = + (struct cdns_i2c_platform_data *)dev_get_driver_data(dev); i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev); if (!i2c_bus->regs) return -ENOMEM; + if (pdata) + i2c_bus->quirks = pdata->quirks; + i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */ return 0; @@ -364,8 +400,13 @@ static const struct dm_i2c_ops cdns_i2c_ops = { .set_bus_speed = cdns_i2c_set_bus_speed, }; +static const struct cdns_i2c_platform_data r1p10_i2c_def = { + .quirks = CDNS_I2C_BROKEN_HOLD_BIT, +}; + static const struct udevice_id cdns_i2c_of_match[] = { - { .compatible = "cdns,i2c-r1p10" }, + { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def }, + { .compatible = "cdns,i2c-r1p14" }, { /* end of table */ } }; -- 2.7.4

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[U-Boot] [PATCH] ML: SPL: NOR: Add CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE define to enable whole image copy from NOR
by Lukasz Majewski 02 Jan '17

02 Jan '17

This define gives the possibility to copy entire image (including header) from NOR parallel memory to e.g. SDRAM. The legacy behavior is preserved, since other board don't enabled this option. Signed-off-by: Lukasz Majewski <l.majewski(a)majess.pl> --- Kconfig | 10 ++++++++++ README | 4 ++++ common/spl/spl_nor.c | 12 +++++++++--- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/Kconfig b/Kconfig index e443490..473a099 100644 --- a/Kconfig +++ b/Kconfig @@ -159,6 +159,16 @@ config SPL_NOR_SUPPORT help This option enables SPL NOR driver. +config SPL_NOR_COPY_ENTIRE_IMAGE + bool + depends on SPL_NOR_SUPPORT + prompt "Copy entire image from NOR memory" + default n + help + By default the SPL NOR driver supports copying only payload to + destination address. Say Y if you want to copy entire image (including + its image header). + config SPL_SYS_MALLOC_SIMPLE bool depends on SPL diff --git a/README b/README index f41a6af..e9a3c5b 100644 --- a/README +++ b/README @@ -3661,6 +3661,10 @@ FIT uImage format: It conflicts with SPL env from storage medium specified by CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE + CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE + Allow NOR stored u-boot image to be copied by SPL with header to + SDRAM memory and executed from it + CONFIG_SPL_PAD_TO Image offset to which the SPL should be padded before appending the SPL payload. By default, this is defined as diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 8ea874c..1e0f739 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -9,13 +9,15 @@ int spl_nor_load_image(void) { + void *img_src; int ret; +#ifndef CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE /* * Loading of the payload to SDRAM is done with skipping of * the mkimage header in this SPL NOR driver */ spl_image.flags |= SPL_COPY_PAYLOAD_ONLY; - +#endif #ifdef CONFIG_SPL_OS_BOOT if (!spl_start_uboot()) { const struct image_header *header; @@ -64,9 +66,13 @@ int spl_nor_load_image(void) if (ret) return ret; + img_src = (void *)CONFIG_SYS_UBOOT_BASE; +#ifndef CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE + img_src += sizeof(struct image_header)); +#endif + memcpy((void *)(unsigned long)spl_image.load_addr, - (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)), - spl_image.size); + img_src, spl_image.size); return 0; } -- 2.1.4

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[U-Boot] [PATCH 00/10] i.MX6: engicam: Add nandboot env and FIT support
by Jagan Teki 02 Jan '17

02 Jan '17

From: Jagan Teki <jagan(a)amarulasolutions.com> This patchset, add support for - legacy image boot, with bootm - NAND boot env support, with UBIFS as rootfs - FIT image boot support on i.MX6 based Engicam Quad/DualLite/Dual/Solo module kits. Jagan Teki (10): configs: engicam: Increase nand kernel partition size imx6: engicam: Use bootm instead of bootz configs: engicam: Rename nand with gpmi-name in mtdparts defconfigs: engicam: Enable MMC commands in nand defconfigs: engicam: Enable UBI commands imx6: engicam: Add nandboot env support defconfigs: imx6: engicam: Enable FIT configs: engicam: Enable CONFIG_IMAGE_FORMAT_LEGACY configs: engicam: Cleanup on mmcboot env configs: engicam: Add fitboot env support configs/imx6dl_icore_mmc_defconfig | 4 +- configs/imx6dl_icore_nand_defconfig | 10 ++++- configs/imx6dl_icore_rqs_mmc_defconfig | 4 +- configs/imx6q_icore_mmc_defconfig | 4 +- configs/imx6q_icore_nand_defconfig | 10 ++++- configs/imx6q_icore_rqs_mmc_defconfig | 4 +- configs/imx6ul_geam_mmc_defconfig | 4 +- configs/imx6ul_geam_nand_defconfig | 10 ++++- include/configs/imx6qdl_icore.h | 77 +++++++++++++++++++++++++--------- include/configs/imx6qdl_icore_rqs.h | 43 +++++++++++++------ include/configs/imx6ul_geam.h | 76 ++++++++++++++++++++++++--------- 11 files changed, 187 insertions(+), 59 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] udoo_neo: Remove USDHC3 entry
by Fabio Estevam 02 Jan '17

02 Jan '17

Commit c94981efa20cc58 ("udoo_neo: Remove USDHC3 support") removed the SDHC3 support, but missed to remove the entry from the usdhc_cfg structure, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- board/udoo/neo/neo.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index 688b522..c5058b4 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -389,9 +389,8 @@ int board_early_init_f(void) return 0; } -static struct fsl_esdhc_cfg usdhc_cfg[2] = { +static struct fsl_esdhc_cfg usdhc_cfg[1] = { {USDHC2_BASE_ADDR, 0, 4}, - {USDHC3_BASE_ADDR, 0, 4}, }; #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1) -- 2.7.4

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[U-Boot] [PATCH] udoo: neo: Fix indentation
by Fabio Estevam 02 Jan '17

02 Jan '17

From: Fabio Estevam <fabio.estevam(a)nxp.com> The standard way is to put ifdef/endif in the very first column. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- board/udoo/neo/neo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index 688b522..288674a 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -349,9 +349,9 @@ int board_init(void) /* Active high for ncp692 */ gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); - #ifdef CONFIG_SYS_I2C_MXC +#ifdef CONFIG_SYS_I2C_MXC setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - #endif +#endif return 0; } -- 2.7.4

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[U-Boot] [PATCH] imx6ul: geam6ul: Enable I2C support
by Jagan Teki 02 Jan '17

02 Jan '17

From: Jagan Teki <jagan(a)amarulasolutions.com> Enable I2C support for Engicam GEAM6UL NAND module. Cc: Stefano Babic <sbabic(a)denx.de> Cc: Matteo Lisi <matteo.lisi(a)engicam.com> Cc: Michael Trimarchi <michael(a)amarulasolutions.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- configs/imx6ul_geam_nand_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index 71ef06a..66274e5 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_NAND=y CONFIG_CMD_UBI=y CONFIG_CMD_CACHE=y +CONFIG_CMD_I2C=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y @@ -37,6 +38,7 @@ CONFIG_NAND_MXS=y CONFIG_IMX_THERMAL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -- 1.9.1

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[U-Boot] [PATCH] imx6ul: geam6ul: Add MAINTAINERS for nand_defconfig
by Jagan Teki 02 Jan '17

02 Jan '17

From: Jagan Teki <jagan(a)amarulasolutions.com> Add Jagan as MAINTAINERS of configs/imx6ul_geam_nand_defconfig Cc: Stefano Babic <sbabic(a)denx.de> Cc: Matteo Lisi <matteo.lisi(a)engicam.com> Cc: Michael Trimarchi <michael(a)amarulasolutions.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- board/engicam/geam6ul/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/engicam/geam6ul/MAINTAINERS b/board/engicam/geam6ul/MAINTAINERS index 6691450..079370c 100644 --- a/board/engicam/geam6ul/MAINTAINERS +++ b/board/engicam/geam6ul/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/engicam/geam6ul F: include/configs/imx6ul_geam.h F: configs/imx6ul_geam_mmc_defconfig +F: configs/imx6ul_geam_nand_defconfig -- 1.9.1

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[U-Boot] [PATCH] mx6qsabreauto: Fix the EIM clock for the mx6qp variant
by Fabio Estevam 02 Jan '17

02 Jan '17

From: Fabio Estevam <fabio.estevam(a)nxp.com> On the MX6Q the aclk_eim_slow_podf field is '1' after POR, while on the MX6DQP it is '3'. This makes the EIM clock to be only 66MHz on the mx6qp variant, instead of 132 MHz. Instead of relying on the POR values for the CSMR1 register, make sure to manually configure the clk_eim_slow_sel field as '00' so that EIM clock is derived from AXI clock and the aclk_eim_slow_podf field as '1' so that EIM clock can be AXI clock divided by 2. This way a consistent EIM clock frequency is configured for all the mx6 variants. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 5fca4d1..51bbbc4 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -231,6 +231,33 @@ static void eimnor_cs_setup(void) set_chipselect_size(CS0_128); } +static void eim_clk_setup(void) +{ + struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int cscmr1, ccgr6; + + + /* Turn off EIM clock */ + ccgr6 = readl(&imx_ccm->CCGR6); + ccgr6 &= ~(0x3 << 10); + writel(ccgr6, &imx_ccm->CCGR6); + + /* + * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root + * and aclk_eim_slow_podf = 01 --> divide by 2 + * so that we can have EIM at the maximum clock of 132MHz + */ + cscmr1 = readl(&imx_ccm->cscmr1); + cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK | + MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK); + cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET); + writel(cscmr1, &imx_ccm->cscmr1); + + /* Turn on EIM clock */ + ccgr6 |= (0x3 << 10); + writel(ccgr6, &imx_ccm->CCGR6); +} + static void setup_iomux_eimnor(void) { imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads)); @@ -519,6 +546,7 @@ int board_early_init_f(void) #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif + eim_clk_setup(); return 0; } -- 2.7.4

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