January 2017 - U-Boot

[U-Boot] linux "coherent_pool" kernel parameter and u-boot
by t-erdmann 17 Jan '17

17 Jan '17

Hello u-boot list members, i have a problem with my arm64 odroid c2 board running some dvb-s2 usb cards. I had to increase the dma buffers for usb with kernel parameter "coherent_size=4M" to get them running. The default was 256kB. My question is, has this buffer to be defined or reserved in u-boot too ? From earlyer work with at91 i know that some adresses for kernel image and pool were be defined in u-boot config space. Can please someone explain how this works today on arm64 ? Thanks Thomas

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[U-Boot] [PATCH] drivers: usb: gadget: ether: Fix compiler warning
by Lokesh Vutla 17 Jan '17

17 Jan '17

Latest gcc 6.2 compiler is throwing the below warning for am335x_baltos_defconfig drivers/usb/gadget/ether.c:501:17: warning: 'mdlm_detail_desc' defined but not used [-Wunused-const-variable=] static const u8 mdlm_detail_desc[] = { Guard mdlm_detail_desc with CONFIG_USB_ETH_SUBSET to avoid the warning Reported-by: Dan Murphy <dmurphy(a)ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- drivers/usb/gadget/ether.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index f1b0709821..4137d76c42 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -507,6 +507,7 @@ static const struct usb_cdc_mdlm_desc mdlm_desc = { * can't really use its struct. All we do here is say that we're using * the submode of "SAFE" which directly matches the CDC Subset. */ +#ifdef CONFIG_USB_ETH_SUBSET static const u8 mdlm_detail_desc[] = { 6, USB_DT_CS_INTERFACE, @@ -516,6 +517,7 @@ static const u8 mdlm_detail_desc[] = { 0, /* network control capabilities (none) */ 0, /* network data capabilities ("raw" encapsulation) */ }; +#endif #endif -- 2.11.0

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[U-Boot] [PATCHv7 1/2] armv8/ls1043a: fixup GIC offset for ls1043a rev1
by Zhiqiang Hou 17 Jan '17

17 Jan '17

From: Wenbin Song <wenbin.song(a)nxp.com> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song(a)nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu(a)nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- V7: - Use the full SVR to check if a Soc needs the fix. - Use 4K alignment as the default alignment. arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 64 ++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 55 +++++++++++++++++-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 24 ++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + 6 files changed, 146 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index cc0dc88..cb24ce7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -168,4 +168,8 @@ config SYS_FSL_DDR4 help Enable Freescale DDR4 controller. +config HAS_FEATURE_GIC64K_ALIGN + bool + default y if ARCH_LS1043A + endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index c10ccf9..f289172 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -133,6 +133,67 @@ void fsl_fdt_disable_usb(void *blob) } } +#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN +static void fdt_fixup_gic(void *blob) +{ + int offset, err; + u64 reg[8]; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int val; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + int align_64k = 0; + + val = gur_in32(&gur->svr); + + if (SVR_SOC_VER(val) != SVR_LS1043A) { + align_64k = 1; + } else if (SVR_REV(val) != REV1_0) { + val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT); + if (!val) + align_64k = 1; + } + + offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000"); + if (offset < 0) { + printf("WARNING: fdt_subnode_offset can't find node %s: %s\n", + "interrupt-controller@1400000", fdt_strerror(offset)); + return; + } + + /* Fixup gic node align with 64K */ + if (align_64k) { + reg[0] = cpu_to_fdt64(GICD_BASE_64K); + reg[1] = cpu_to_fdt64(GICD_SIZE_64K); + reg[2] = cpu_to_fdt64(GICC_BASE_64K); + reg[3] = cpu_to_fdt64(GICC_SIZE_64K); + reg[4] = cpu_to_fdt64(GICH_BASE_64K); + reg[5] = cpu_to_fdt64(GICH_SIZE_64K); + reg[6] = cpu_to_fdt64(GICV_BASE_64K); + reg[7] = cpu_to_fdt64(GICV_SIZE_64K); + } else { + /* Fixup gic node align with default */ + reg[0] = cpu_to_fdt64(GICD_BASE); + reg[1] = cpu_to_fdt64(GICD_SIZE); + reg[2] = cpu_to_fdt64(GICC_BASE); + reg[3] = cpu_to_fdt64(GICC_SIZE); + reg[4] = cpu_to_fdt64(GICH_BASE); + reg[5] = cpu_to_fdt64(GICH_SIZE); + reg[6] = cpu_to_fdt64(GICV_BASE); + reg[7] = cpu_to_fdt64(GICV_SIZE); + } + + err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg)); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s\n", + "reg", "interrupt-controller@1400000", + fdt_strerror(err)); + return; + } + + return; +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FSL_LSCH2 @@ -177,4 +238,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif fsl_fdt_disable_usb(blob); +#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN + fdt_fixup_gic(blob); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 72f2c11..67c9636 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -19,6 +19,53 @@ #endif #include <asm/u-boot.h> +/* Get GIC offset +* For LS1043a rev1.0, GIC base address align with 4k. +* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT] +* is set, GIC base address align with 4K, or else align +* with 64k. +* output: +* x0: the base address of GICD +* x1: the base address of GICC +*/ +ENTRY(get_gic_offset) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE +#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN + ldr x2, =DCFG_CCSR_SVR + ldr w2, [x2] + rev w2, w2 + mov w3, w2 + ands w3, w3, #SVR_E_MASK + mov w4, #LS1043A_SVR + cmp w3, w4 + b.ne 1f + ands w2, w2, #0xff + cmp w2, #REV1_0 + b.eq 1f + ldr x2, =SCFG_GIC400_ALIGN + ldr w2, [x2] + rev w2, w2 + tbnz w2, #GIC_ADDR_BIT, 1f + ldr x0, =GICD_BASE_64K + ldr x1, =GICC_BASE_64K +1: +#endif + ret +ENDPROC(get_gic_offset) + +ENTRY(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + mov x29, lr /* Save LR */ + bl get_gic_offset + bl gic_kick_secondary_cpus + mov lr, x29 /* Restore LR */ +#endif + ret +ENDPROC(smp_kick_all_cpus) + + ENTRY(lowlevel_init) mov x29, lr /* Save LR */ @@ -110,15 +157,14 @@ ENTRY(lowlevel_init) /* Initialize GIC Secure Bank Status */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f - ldr x0, =GICD_BASE + bl get_gic_offset bl gic_init_secure 1: #ifdef CONFIG_GICV3 ldr x0, =GICR_BASE bl gic_init_secure_percpu #elif defined(CONFIG_GICV2) - ldr x0, =GICD_BASE - ldr x1, =GICC_BASE + bl get_gic_offset bl gic_init_secure_percpu #endif #endif @@ -356,7 +402,8 @@ ENTRY(secondary_boot_func) #if defined(CONFIG_GICV3) gic_wait_for_interrupt_m x0 #elif defined(CONFIG_GICV2) - ldr x0, =GICC_BASE + bl get_gic_offset + mov x0, x1 gic_wait_for_interrupt_m x0, w1 #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index c50894a..577f00c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -174,6 +174,30 @@ /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define GICH_BASE 0x01404000 +#define GICV_BASE 0x01406000 +#define GICD_SIZE 0x1000 +#define GICC_SIZE 0x2000 +#define GICH_SIZE 0x2000 +#define GICV_SIZE 0x2000 +#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN +#define GICD_BASE_64K 0x01410000 +#define GICC_BASE_64K 0x01420000 +#define GICH_BASE_64K 0x01440000 +#define GICV_BASE_64K 0x01460000 +#define GICD_SIZE_64K 0x10000 +#define GICC_SIZE_64K 0x20000 +#define GICH_SIZE_64K 0x20000 +#define GICV_SIZE_64K 0x20000 +#endif + +#define DCFG_CCSR_SVR 0x1ee00a4 +#define REV1_0 0x10 +#define REV1_1 0x11 +#define GIC_ADDR_BIT 31 +#define SCFG_GIC400_ALIGN 0x1570188 +#define LS1043A_SVR 0x87920000 +#define SVR_E_MASK 0xFFFFFE00 #define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index b3cfd89..81bc5bc 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -360,7 +360,8 @@ struct ccsr_scfg { u32 qspi_cfg; u8 res_160[0x180-0x160]; u32 dmamcr; - u8 res_184[0x18c-0x184]; + u8 res_184[0x188-0x184]; + u32 gic_align; u32 debug_icid; u8 res_190[0x1a4-0x190]; u32 snpcnfgcr; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 78363b6..1deb330 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -59,6 +59,7 @@ struct cpu_type { #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) +#define SVR_REV(svr) (((svr) >> 0) & 0xff) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) #define IS_SVR_REV(svr, maj, min) \ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] powerpc: mpc83xx: Enable pre-relocation malloc
by Mario Six 17 Jan '17

17 Jan '17

To enable DM on MPC83xx, we need pre-relocation malloc, which is implemented in this patch. Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- arch/powerpc/cpu/mpc83xx/cpu_init.c | 3 +-- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 4 +--- arch/powerpc/cpu/mpc83xx/start.S | 23 +++++++++++++++++++++++ 3 files changed, 25 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index f911275..3a0916b 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -205,8 +205,7 @@ void cpu_init_f (volatile immap_t * im) /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); + /* global data region was cleared in start.S */ /* system performance tweaking */ clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 845861e..026da12 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -23,9 +23,7 @@ void cpu_init_f (volatile immap_t * im) /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* Clear initial global data */ - for (i = 0; i < sizeof(gd_t); i++) - ((char *)gd)[i] = 0; + /* global data region was cleared in start.S */ /* system performance tweaking */ diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 9bd86d8..f8044ac 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -265,6 +265,29 @@ in_flash: lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l + /* r3 = end of GD area */ + addi r3,r1,GENERATED_GBL_DATA_SIZE + + /* Zero GD area */ + li r0, 0 +1: + subi r3, r3, 1 + stb r0, 0(r3) + cmplw r1, r3 + bne 1b + +#ifdef CONFIG_SYS_MALLOC_F_LEN + +#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM." +#endif + + /* r1 = stack pointer / pre-reloc malloc area */ + subi r1, r1, CONFIG_SYS_MALLOC_F_LEN + + /* Set pointer to pre-reloc malloc area in GD */ + stw r1, GD_MALLOC_BASE(r3) +#endif li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ -- 2.9.0

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[U-Boot] [PATCH v1 1/1] x86: Synchronize list of x86 subarchitectures (update bootparam.h)
by Andy Shevchenko 17 Jan '17

17 Jan '17

Basically rename X86_SUBARCH_MRST to X86_SUBARCH_INTEL_MID to be more specific. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- arch/x86/include/asm/bootparam.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h index a373a79886..48b138c6b0 100644 --- a/arch/x86/include/asm/bootparam.h +++ b/arch/x86/include/asm/bootparam.h @@ -117,7 +117,8 @@ enum { X86_SUBARCH_PC = 0, X86_SUBARCH_LGUEST, X86_SUBARCH_XEN, - X86_SUBARCH_MRST, + X86_SUBARCH_INTEL_MID, + X86_SUBARCH_CE4100, X86_NR_SUBARCHS, }; #endif /* _ASM_X86_BOOTPARAM_H */ -- 2.11.0

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[U-Boot] [PATCH v2] armv8: aarch64: Fix the warning about x1-x3 nonzero issue
by Alison Wang 17 Jan '17

17 Jan '17

For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang(a)nxp.com> --- Changes in v2: - Add another input argument 4 for armv8_switch_to_el2 and armv8_switch_to_el1. - Give up the previous way to adjust the parameters to transfer and make sure x3 is zero. arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 28 ++++++++++++++-------------- arch/arm/cpu/armv8/sec_firmware_asm.S | 5 +++-- arch/arm/cpu/armv8/start.S | 8 ++++---- arch/arm/cpu/armv8/transition.S | 22 +++++++++++----------- arch/arm/include/asm/system.h | 8 +++++--- arch/arm/lib/bootm.c | 10 +++++----- arch/arm/mach-rmobile/lowlevel_init_gen3.S | 8 ++++---- cmd/bootefi.c | 2 +- 8 files changed, 47 insertions(+), 44 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 72f2c11..63215f0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -378,29 +378,29 @@ cpu_is_le: b.eq 1f #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x3, secondary_switch_to_el1 - ldr x4, =ES_TO_AARCH64 + adr x4, secondary_switch_to_el1 + ldr x5, =ES_TO_AARCH64 #else - ldr x3, [x11] - ldr x4, =ES_TO_AARCH32 + ldr x4, [x11] + ldr x5, =ES_TO_AARCH32 #endif bl secondary_switch_to_el2 1: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x3, secondary_switch_to_el1 + adr x4, secondary_switch_to_el1 #else - ldr x3, [x11] + ldr x4, [x11] #endif - ldr x4, =ES_TO_AARCH64 + ldr x5, =ES_TO_AARCH64 bl secondary_switch_to_el2 ENDPROC(secondary_boot_func) ENTRY(secondary_switch_to_el2) - switch_el x5, 1f, 0f, 0f + switch_el x6, 1f, 0f, 0f 0: ret -1: armv8_switch_to_el2_m x3, x4, x5 +1: armv8_switch_to_el2_m x4, x5, x6 ENDPROC(secondary_switch_to_el2) ENTRY(secondary_switch_to_el1) @@ -414,22 +414,22 @@ ENTRY(secondary_switch_to_el1) /* physical address of this cpus spin table element */ add x11, x1, x0 - ldr x3, [x11] + ldr x4, [x11] ldr x5, [x11, #24] ldr x6, =IH_ARCH_DEFAULT cmp x6, x5 b.eq 2f - ldr x4, =ES_TO_AARCH32 + ldr x5, =ES_TO_AARCH32 bl switch_to_el1 -2: ldr x4, =ES_TO_AARCH64 +2: ldr x5, =ES_TO_AARCH64 switch_to_el1: - switch_el x5, 0f, 1f, 0f + switch_el x6, 0f, 1f, 0f 0: ret -1: armv8_switch_to_el1_m x3, x4, x5 +1: armv8_switch_to_el1_m x4, x5, x6 ENDPROC(secondary_switch_to_el1) /* Ensure that the literals used by the secondary boot code are diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 903195d..747b53f 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -57,7 +57,8 @@ ENDPROC(_sec_firmware_support_psci_version) * x0: argument, zero * x1: machine nr * x2: fdt address - * x3: kernel entry point + * x3: input argument + * x4: kernel entry point * @param outputs for secure firmware: * x0: function id * x1: kernel entry point @@ -65,7 +66,7 @@ ENDPROC(_sec_firmware_support_psci_version) * x3: fdt address */ ENTRY(armv8_el2_to_aarch32) - mov x0, x3 + mov x0, x4 mov x3, x2 mov x2, x1 mov x1, x0 diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 9535057..eb1b8a6 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -250,14 +250,14 @@ WEAK(lowlevel_init) /* * All slaves will enter EL2 and optionally EL1. */ - adr x3, lowlevel_in_el2 - ldr x4, =ES_TO_AARCH64 + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el2 lowlevel_in_el2: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x3, lowlevel_in_el1 - ldr x4, =ES_TO_AARCH64 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el1 lowlevel_in_el1: diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index adb9f35..ca07465 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -11,9 +11,9 @@ #include <asm/macro.h> ENTRY(armv8_switch_to_el2) - switch_el x5, 1f, 0f, 0f + switch_el x6, 1f, 0f, 0f 0: - cmp x4, #ES_TO_AARCH64 + cmp x5, #ES_TO_AARCH64 b.eq 2f /* * When loading 32-bit kernel, it will jump @@ -22,23 +22,23 @@ ENTRY(armv8_switch_to_el2) bl armv8_el2_to_aarch32 2: /* - * x3 is kernel entry point or switch_to_el1 + * x4 is kernel entry point or switch_to_el1 * if CONFIG_ARMV8_SWITCH_TO_EL1 is defined. * When running in EL2 now, jump to the - * address saved in x3. + * address saved in x4. */ - br x3 -1: armv8_switch_to_el2_m x3, x4, x5 + br x4 +1: armv8_switch_to_el2_m x4, x5, x6 ENDPROC(armv8_switch_to_el2) ENTRY(armv8_switch_to_el1) - switch_el x5, 0f, 1f, 0f + switch_el x6, 0f, 1f, 0f 0: - /* x3 is kernel entry point. When running in EL1 - * now, jump to the address saved in x3. + /* x4 is kernel entry point. When running in EL1 + * now, jump to the address saved in x4. */ - br x3 -1: armv8_switch_to_el1_m x3, x4, x5 + br x4 +1: armv8_switch_to_el1_m x4, x5, x6 ENDPROC(armv8_switch_to_el1) WEAK(armv8_el2_to_aarch32) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index dc4c991..766e929 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -196,11 +196,12 @@ void __asm_switch_ttbr(u64 new_ttbr); * For loading 32-bit OS, machine nr * @fdt_addr: For loading 64-bit OS, zero. * For loading 32-bit OS, fdt address. + * @arg4: Input argument. * @entry_point: kernel entry point * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 */ void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, - u64 entry_point, u64 es_flag); + u64 arg4, u64 entry_point, u64 es_flag); /* * Switch from EL2 to EL1 for ARMv8 * @@ -210,13 +211,14 @@ void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, * For loading 32-bit OS, machine nr * @fdt_addr: For loading 64-bit OS, zero. * For loading 32-bit OS, fdt address. + * @arg4: Input argument. * @entry_point: kernel entry point * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 */ void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr, - u64 entry_point, u64 es_flag); + u64 arg4, u64 entry_point, u64 es_flag); void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr, - u64 entry_point); + u64 arg4, u64 entry_point); void gic_init(void); void gic_send_sgi(unsigned long sgino); void wait_for_wakeup(void); diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 43cc83e..8125cf0 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -287,11 +287,11 @@ static void switch_to_el1(void) if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) && (images.os.arch == IH_ARCH_ARM)) armv8_switch_to_el1(0, (u64)gd->bd->bi_arch_number, - (u64)images.ft_addr, + (u64)images.ft_addr, 0, (u64)images.ep, ES_TO_AARCH32); else - armv8_switch_to_el1((u64)images.ft_addr, 0, 0, + armv8_switch_to_el1((u64)images.ft_addr, 0, 0, 0, images.ep, ES_TO_AARCH64); } @@ -324,17 +324,17 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) update_os_arch_secondary_cores(images->os.arch); #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - armv8_switch_to_el2((u64)images->ft_addr, 0, 0, + armv8_switch_to_el2((u64)images->ft_addr, 0, 0, 0, (u64)switch_to_el1, ES_TO_AARCH64); #else if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) && (images->os.arch == IH_ARCH_ARM)) armv8_switch_to_el2(0, (u64)gd->bd->bi_arch_number, - (u64)images->ft_addr, + (u64)images->ft_addr, 0, (u64)images->ep, ES_TO_AARCH32); else - armv8_switch_to_el2((u64)images->ft_addr, 0, 0, + armv8_switch_to_el2((u64)images->ft_addr, 0, 0, 0, images->ep, ES_TO_AARCH64); #endif diff --git a/arch/arm/mach-rmobile/lowlevel_init_gen3.S b/arch/arm/mach-rmobile/lowlevel_init_gen3.S index 11acce0..ce3d4f5 100644 --- a/arch/arm/mach-rmobile/lowlevel_init_gen3.S +++ b/arch/arm/mach-rmobile/lowlevel_init_gen3.S @@ -61,14 +61,14 @@ ENTRY(lowlevel_init) /* * All slaves will enter EL2 and optionally EL1. */ - adr x3, lowlevel_in_el2 - ldr x4, =ES_TO_AARCH64 + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el2 lowlevel_in_el2: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x3, lowlevel_in_el1 - ldr x4, =ES_TO_AARCH64 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el1 lowlevel_in_el1: diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 97a0fc9..06943a9 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -246,7 +246,7 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt) /* Move into EL2 and keep running there */ armv8_switch_to_el2((ulong)entry, (ulong)&loaded_image_info, - (ulong)&systab, (ulong)efi_run_in_el2, + (ulong)&systab, 0, (ulong)efi_run_in_el2, ES_TO_AARCH64); /* Should never reach here, efi exits with longjmp */ -- 2.1.0.27.g96db324

4 4

[U-Boot] [PATCH] armv8: fix #if around spin-table code in start.S
by Oded Gabbay 17 Jan '17

17 Jan '17

Using CONFIG_IS_ENABLED() doesn't work in SPL. This patch replaces the only occurrence of CONFIG_IS_ENABLED() in start.S to a regular #if defined(). It also adds "&& !defined(CONFIG_SPL_BUILD)" to that #if statement because the spin-table code can't currently work in SPL, and the spin-table file isn't even compiled in SPL. Signed-off-by: Oded Gabbay <oded.gabbay(a)gmail.com> --- arch/arm/cpu/armv8/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 4f5f6d8..2f975a0 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -99,7 +99,7 @@ save_boot_params_ret: /* Processor specific initialization */ bl lowlevel_init -#if CONFIG_IS_ENABLED(ARMV8_SPIN_TABLE) +#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD) branch_if_master x0, x1, master_cpu b spin_table_secondary_jump /* never return */ -- 2.7.4

3 5

[U-Boot] [PATCH][v2] driver: net: fsl-mc: Use aligned address for MC FW load
by Priyanka Jain 16 Jan '17

16 Jan '17

Firmware of Management Complex (MC) should be loaded at 512MB aligned address. So, -mc_ram_addr address calculation in mc_get_dram_addr() is updated to fetch aligned address -calculate_mc_private_ram_params() is removed as it is no longer required -num_256mb_blocks calculation is moved to mc_init() Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v2: Update mc_get_dram_addr() logic for adress calculation instead of updating variable mc_ram_addr drivers/net/fsl-mc/mc.c | 87 ++++++++++++++++++----------------------------- 1 files changed, 33 insertions(+), 54 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 46b8a6b..06d373d 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -41,6 +41,7 @@ struct fsl_dpbp_obj *dflt_dpbp = NULL; struct fsl_dpio_obj *dflt_dpio = NULL; struct fsl_dpni_obj *dflt_dpni = NULL; static u64 mc_lazy_dpl_addr; +u64 mc_ram_addr = 0; #ifdef DEBUG void dump_ram_words(const char *title, void *addr) @@ -153,48 +154,6 @@ int parse_mc_firmware_fit_image(u64 mc_fw_addr, } #endif -/* - * Calculates the values to be used to specify the address range - * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers. - * It returns the highest 512MB-aligned address within the given - * address range, in '*aligned_base_addr', and the number of 256 MiB - * blocks in it, in 'num_256mb_blocks'. - */ -static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr, - size_t mc_ram_size, - u64 *aligned_base_addr, - u8 *num_256mb_blocks) -{ - u64 addr; - u16 num_blocks; - - if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) { - printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", - mc_ram_size); - return -EINVAL; - } - - num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; - if (num_blocks < 1 || num_blocks > 0xff) { - printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", - mc_ram_size); - return -EINVAL; - } - - addr = (mc_private_ram_start_addr + mc_ram_size - 1) & - MC_RAM_BASE_ADDR_ALIGNMENT_MASK; - - if (addr < mc_private_ram_start_addr) { - printf("fsl-mc: ERROR: bad start address %#llx\n", - mc_private_ram_start_addr); - return -EFAULT; - } - - *aligned_base_addr = addr; - *num_256mb_blocks = num_blocks; - return 0; -} - static int mc_fixup_dpc(u64 dpc_addr) { void *blob = (void *)dpc_addr; @@ -443,7 +402,6 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) int error = 0; int portal_id = 0; struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; - u64 mc_ram_addr = mc_get_dram_addr(); u32 reg_gsr; u32 reg_mcfbalr; #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR @@ -451,17 +409,18 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) size_t raw_image_size = 0; #endif struct mc_version mc_ver_info; - u64 mc_ram_aligned_base_addr; u8 mc_ram_num_256mb_blocks; size_t mc_ram_size = mc_get_dram_block_size(); - error = calculate_mc_private_ram_params(mc_ram_addr, - mc_ram_size, - &mc_ram_aligned_base_addr, - &mc_ram_num_256mb_blocks); - if (error != 0) + mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; + if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) { + printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", + mc_ram_size); goto out; + } + + mc_ram_addr = mc_get_dram_addr(); /* * Management Complex cores should be held at reset out of POR. @@ -503,11 +462,11 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) /* * Tell MC what is the address range of the DRAM block assigned to it: */ - reg_mcfbalr = (u32)mc_ram_aligned_base_addr | + reg_mcfbalr = (u32)mc_ram_addr | (mc_ram_num_256mb_blocks - 1); out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr); out_le32(&mc_ccsr_regs->reg_mcfbahr, - (u32)(mc_ram_aligned_base_addr >> 32)); + (u32)(mc_ram_addr >> 32)); out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ); /* @@ -615,20 +574,40 @@ int get_dpl_apply_status(void) */ u64 mc_get_dram_addr(void) { - u64 mc_ram_addr; + u64 mc_private_ram_start_addr; + size_t mc_ram_size = mc_get_dram_block_size(); /* * The MC private DRAM block was already carved at the end of DRAM * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: */ if (gd->bd->bi_dram[1].start) { - mc_ram_addr = + mc_private_ram_start_addr = gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; } else { - mc_ram_addr = + mc_private_ram_start_addr = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; } + if (mc_ram_size == 0) { + printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", + mc_ram_size); + return -EINVAL; + } + + /* + * Calculate the highest 512MB aligned address within the + * given address range + */ + mc_ram_addr = (mc_private_ram_start_addr - 1 + + MC_RAM_BASE_ADDR_ALIGNMENT) & + MC_RAM_BASE_ADDR_ALIGNMENT_MASK; + + if (mc_ram_addr < mc_private_ram_start_addr) { + printf("fsl-mc: ERROR: bad start address %#llx\n", + mc_private_ram_start_addr); + return -EFAULT; + } return mc_ram_addr; } -- 1.7.4.1

2 1

[U-Boot] [PATCH v2] board/t1024rdb: enable board-level reset when issuing reset command
by Shengzhou Liu 16 Jan '17

16 Jan '17

As board-specific reset logic, it needs to issue reset signal via CPLD when issuing 'reset' command in u-boot, this patch solves the issue of reset command not working on T1024RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- v2: add build condition. board/freescale/t102xrdb/t102xrdb.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 01dbf38..0f453a7 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -167,6 +167,13 @@ unsigned long get_board_ddr_clk(void) return CONFIG_DDR_CLK_FREQ; } +#ifdef CONFIG_T1024RDB +void board_reset(void) +{ + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} +#endif + int misc_init_r(void) { return 0; -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH RESEND v2 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0
by Moritz Fischer 16 Jan '17

16 Jan '17

Revision 1.0 of this IP has a couple of issues, such as not supporting repeated start conditions for read transfers. So scan through the list of i2c messages for these conditions and report an error if they are attempted. This has been fixed for revision 1.4 of the IP, so only report the error when the IP can really not do it. Signed-off-by: Moritz Fischer <moritz.fischer(a)ettus.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: u-boot(a)lists.denx.de --- Changes from v1: - Removed additional blank lines - No longer modify printout paths - Rebased on top of prior patches for r1p14 support --- drivers/i2c/i2c-cdns.c | 66 +++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 52 insertions(+), 14 deletions(-) diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index ef85a70..c1d6427 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -67,6 +67,7 @@ struct cdns_i2c_regs { #define CDNS_I2C_FIFO_DEPTH 16 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */ +#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) #ifdef DEBUG static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) @@ -114,6 +115,13 @@ struct i2c_cdns_bus { int id; unsigned int input_freq; struct cdns_i2c_regs __iomem *regs; /* register base */ + + int hold_flag; + u32 quirks; +}; + +struct cdns_i2c_platform_data { + u32 quirks; }; /* Wait for an interrupt */ @@ -236,18 +244,14 @@ static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr, } static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, - u32 len, bool next_is_read) + u32 len) { u8 *cur_data = data; struct cdns_i2c_regs *regs = i2c_bus->regs; - setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO | - CDNS_I2C_CONTROL_HOLD); + setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO); - /* if next is a read, we need to clear HOLD, doesn't work */ - if (next_is_read) - clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW); @@ -267,7 +271,9 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, } /* All done... release the bus */ - clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); + if (!i2c_bus->hold_flag) + clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); + /* Wait for the address and data to be sent */ if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) return -ETIMEDOUT; @@ -285,7 +291,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, struct cdns_i2c_regs *regs = i2c_bus->regs; /* Check the hardware can handle the requested bytes */ - if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX)) + if ((len < 0)) return -EINVAL; setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO | @@ -310,7 +316,8 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, *(cur_data++) = readl(&regs->data); } while (readl(&regs->transfer_size) != 0); /* All done... release the bus */ - clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); + if (!i2c_bus->hold_flag) + clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); #ifdef DEBUG cdns_i2c_debug_status(regs); @@ -322,19 +329,41 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) { struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); - int ret; + int ret, count; + bool hold_quirk; + + hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT); + + if (nmsgs > 1) { + /* + * This controller does not give completion interrupt after a + * master receive message if HOLD bit is set (repeated start), + * resulting in SW timeout. Hence, if a receive message is + * followed by any other message, an error is returned + * indicating that this sequence is not supported. + */ + for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) { + if (msg[count].flags & I2C_M_RD) { + printf("Can't do repeated start after a receive message\n"); + return -EOPNOTSUPP; + } + } + + i2c_bus->hold_flag = 1; + setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD); + } else { + i2c_bus->hold_flag = 0; + } debug("i2c_xfer: %d messages\n", nmsgs); for (; nmsgs > 0; nmsgs--, msg++) { - bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); - debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); if (msg->flags & I2C_M_RD) { ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf, msg->len); } else { ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, - msg->len, next_is_read); + msg->len); } if (ret) { debug("i2c_write: error sending\n"); @@ -348,11 +377,16 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, static int cdns_i2c_ofdata_to_platdata(struct udevice *dev) { struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); + struct cdns_i2c_platform_data *pdata = + (struct cdns_i2c_platform_data *)dev_get_driver_data(dev); i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev); if (!i2c_bus->regs) return -ENOMEM; + if (pdata) + i2c_bus->quirks = pdata->quirks; + i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */ return 0; @@ -364,8 +398,12 @@ static const struct dm_i2c_ops cdns_i2c_ops = { .set_bus_speed = cdns_i2c_set_bus_speed, }; +static const struct cdns_i2c_platform_data r1p10_i2c_def = { + .quirks = CDNS_I2C_BROKEN_HOLD_BIT, +}; + static const struct udevice_id cdns_i2c_of_match[] = { - { .compatible = "cdns,i2c-r1p10" }, + { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def }, { .compatible = "cdns,i2c-r1p14" }, { /* end of table */ } }; -- 2.7.4

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