January 2017 - U-Boot

[U-Boot] [PATCH RESEND v2] at91: video: Support driver-model for the HLCD driver
by Songjun Wu 16 Jan '17

16 Jan '17

Add driver-model support to this driver. Signed-off-by: Songjun Wu <songjun.wu(a)microchip.com> --- Changes in v2: - Due to the peripheral clock driver improvement, remove the unneccessary clock calling. drivers/video/Kconfig | 7 + drivers/video/Makefile | 2 +- drivers/video/atmel_hlcdfb.c | 314 ++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 319 insertions(+), 4 deletions(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 8361a717e7..c40b2cffb0 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -362,6 +362,13 @@ config DISPLAY The devices provide a simple interface to start up the display, read display information and enable it. +config VIDEO_ATMEL_HLCD + bool "Enable ATMEL video support using HLCDC" + depends on DM_VIDEO + help + Only the LCD is supported in U-Boot. This option enables this support + which can be used on devices which have an LCD display connected. + config VIDEO_BROADWELL_IGD bool "Enable Intel Broadwell integrated graphics device" depends on X86 diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 3f045fe578..3d54cf91d1 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -22,7 +22,6 @@ endif obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o -obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o @@ -35,6 +34,7 @@ obj-$(CONFIG_S6E8AX0) += s6e8ax0.o obj-$(CONFIG_S6E63D6) += s6e63d6.o obj-$(CONFIG_LD9040) += ld9040.o obj-$(CONFIG_SED156X) += sed156x.o +obj-$(CONFIG_VIDEO_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index 960b474b76..0bcb92b2cf 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -10,13 +10,24 @@ #include <asm/io.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> +#include <clk.h> +#include <dm.h> +#include <fdtdec.h> #include <lcd.h> +#include <video.h> #include <atmel_hlcdc.h> #if defined(CONFIG_LCD_LOGO) #include <bmp_logo.h> #endif +DECLARE_GLOBAL_DATA_PTR; + +#define lcdc_readl(reg) __raw_readl((reg)) +#define lcdc_writel(reg, val) __raw_writel((val), (reg)) + +#ifndef CONFIG_DM_VIDEO + /* configurable parameters */ #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 #define ATMEL_LCDC_DMA_BURST_LEN 8 @@ -26,9 +37,6 @@ #define ATMEL_LCDC_FIFO_SIZE 512 -#define lcdc_readl(reg) __raw_readl((reg)) -#define lcdc_writel(reg, val) __raw_writel((val), (reg)) - /* * the CLUT register map as following * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0) @@ -218,3 +226,303 @@ void lcd_ctrl_init(void *lcdbase) /* Enable flushing if we enabled dcache */ lcd_set_flush_dcache(1); } + +#else + +enum { + LCD_MAX_WIDTH = 1024, + LCD_MAX_HEIGHT = 768, + LCD_MAX_LOG2_BPP = VIDEO_BPP16, +}; + +struct atmel_hlcdc_priv { + struct atmel_hlcd_regs *regs; + struct display_timing timing; + unsigned int vl_bpix; + unsigned int guard_time; + ulong clk_rate; +}; + +static int at91_hlcdc_enable_clk(struct udevice *dev) +{ + struct atmel_hlcdc_priv *priv = dev_get_priv(dev); + struct clk clk; + ulong clk_rate; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return -EINVAL; + + ret = clk_enable(&clk); + if (ret) + return ret; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) + return -ENODEV; + + priv->clk_rate = clk_rate; + + clk_free(&clk); + + return 0; +} + +static void atmel_hlcdc_init(struct udevice *dev) +{ + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + struct atmel_hlcdc_priv *priv = dev_get_priv(dev); + struct atmel_hlcd_regs *regs = priv->regs; + struct display_timing *timing = &priv->timing; + struct lcd_dma_desc *desc; + unsigned long value, vl_clk_pol; + + /* Disable DISP signal */ + lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); + while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) + udelay(1); + /* Disable synchronization */ + lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS); + while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) + udelay(1); + /* Disable pixel clock */ + lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_CLKDIS); + while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) + udelay(1); + /* Disable PWM */ + lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_PWMDIS); + while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) + udelay(1); + + /* Set pixel clock */ + value = priv->clk_rate / timing->pixelclock.typ; + if (priv->clk_rate % timing->pixelclock.typ) + value++; + + vl_clk_pol = 0; + if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) + vl_clk_pol = LCDC_LCDCFG0_CLKPOL; + + if (value < 1) { + /* Using system clock as pixel clock */ + lcdc_writel(&regs->lcdc_lcdcfg0, + LCDC_LCDCFG0_CLKDIV(0) + | LCDC_LCDCFG0_CGDISHCR + | LCDC_LCDCFG0_CGDISHEO + | LCDC_LCDCFG0_CGDISOVR1 + | LCDC_LCDCFG0_CGDISBASE + | vl_clk_pol + | LCDC_LCDCFG0_CLKSEL); + + } else { + lcdc_writel(&regs->lcdc_lcdcfg0, + LCDC_LCDCFG0_CLKDIV(value - 2) + | LCDC_LCDCFG0_CGDISHCR + | LCDC_LCDCFG0_CGDISHEO + | LCDC_LCDCFG0_CGDISOVR1 + | LCDC_LCDCFG0_CGDISBASE + | vl_clk_pol); + } + + /* Initialize control register 5 */ + value = 0; + + if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) + value |= LCDC_LCDCFG5_HSPOL; + if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)) + value |= LCDC_LCDCFG5_VSPOL; + +#ifndef LCD_OUTPUT_BPP + /* Output is 24bpp */ + value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; +#else + switch (LCD_OUTPUT_BPP) { + case 12: + value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP; + break; + case 16: + value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP; + break; + case 18: + value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP; + break; + case 24: + value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; + break; + default: + BUG(); + break; + } +#endif + + value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time); + value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); + lcdc_writel(&regs->lcdc_lcdcfg5, value); + + /* Vertical & Horizontal Timing */ + value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1); + value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1); + lcdc_writel(&regs->lcdc_lcdcfg1, value); + + value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ); + value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1); + lcdc_writel(&regs->lcdc_lcdcfg2, value); + + value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1); + value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1); + lcdc_writel(&regs->lcdc_lcdcfg3, value); + + /* Display size */ + value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1); + value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1); + lcdc_writel(&regs->lcdc_lcdcfg4, value); + + lcdc_writel(&regs->lcdc_basecfg0, + LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO); + + switch (VNBITS(priv->vl_bpix)) { + case 16: + lcdc_writel(&regs->lcdc_basecfg1, + LCDC_BASECFG1_RGBMODE_16BPP_RGB_565); + break; + case 32: + lcdc_writel(&regs->lcdc_basecfg1, + LCDC_BASECFG1_RGBMODE_24BPP_RGB_888); + break; + default: + BUG(); + break; + } + + lcdc_writel(&regs->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0)); + lcdc_writel(&regs->lcdc_basecfg3, 0); + lcdc_writel(&regs->lcdc_basecfg4, LCDC_BASECFG4_DMA); + + /* Disable all interrupts */ + lcdc_writel(&regs->lcdc_lcdidr, ~0UL); + lcdc_writel(&regs->lcdc_baseidr, ~0UL); + + /* Setup the DMA descriptor, this descriptor will loop to itself */ + desc = (struct lcd_dma_desc *)(uc_plat->base - 16); + + desc->address = (u32)uc_plat->base; + + /* Disable DMA transfer interrupt & descriptor loaded interrupt. */ + desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN + | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; + desc->next = (u32)desc; + + /* Flush the DMA descriptor if we enabled dcache */ + flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc)); + + lcdc_writel(&regs->lcdc_baseaddr, desc->address); + lcdc_writel(&regs->lcdc_basectrl, desc->control); + lcdc_writel(&regs->lcdc_basenext, desc->next); + lcdc_writel(&regs->lcdc_basecher, + LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN); + + /* Enable LCD */ + value = lcdc_readl(&regs->lcdc_lcden); + lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_CLKEN); + while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) + udelay(1); + value = lcdc_readl(&regs->lcdc_lcden); + lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_SYNCEN); + while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) + udelay(1); + value = lcdc_readl(&regs->lcdc_lcden); + lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_DISPEN); + while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) + udelay(1); + value = lcdc_readl(&regs->lcdc_lcden); + lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_PWMEN); + while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) + udelay(1); +} + +static int atmel_hlcdc_probe(struct udevice *dev) +{ + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct atmel_hlcdc_priv *priv = dev_get_priv(dev); + int ret; + + ret = at91_hlcdc_enable_clk(dev); + if (ret) + return ret; + + atmel_hlcdc_init(dev); + + uc_priv->xsize = priv->timing.hactive.typ; + uc_priv->ysize = priv->timing.vactive.typ; + uc_priv->bpix = priv->vl_bpix; + + /* Enable flushing if we enabled dcache */ + video_set_flush_dcache(dev, true); + + return 0; +} + +static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev) +{ + struct atmel_hlcdc_priv *priv = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + + priv->regs = (struct atmel_hlcd_regs *)dev_get_addr(dev); + if (!priv->regs) { + debug("%s: No display controller address\n", __func__); + return -EINVAL; + } + + if (fdtdec_decode_display_timing(blob, dev->of_offset, + 0, &priv->timing)) { + debug("%s: Failed to decode display timing\n", __func__); + return -EINVAL; + } + + if (priv->timing.hactive.typ > LCD_MAX_WIDTH) + priv->timing.hactive.typ = LCD_MAX_WIDTH; + + if (priv->timing.vactive.typ > LCD_MAX_HEIGHT) + priv->timing.vactive.typ = LCD_MAX_HEIGHT; + + priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0); + if (!priv->vl_bpix) { + debug("%s: Failed to get bits per pixel\n", __func__); + return -EINVAL; + } + + priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1); + + return 0; +} + +static int atmel_hlcdc_bind(struct udevice *dev) +{ + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + + uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * + (1 << LCD_MAX_LOG2_BPP) / 8; + + debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); + + return 0; +} + +static const struct udevice_id atmel_hlcdc_ids[] = { + { .compatible = "atmel,sama5d2-hlcdc" }, + { } +}; + +U_BOOT_DRIVER(atmel_hlcdfb) = { + .name = "atmel_hlcdfb", + .id = UCLASS_VIDEO, + .of_match = atmel_hlcdc_ids, + .bind = atmel_hlcdc_bind, + .probe = atmel_hlcdc_probe, + .ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv), +}; + +#endif -- 2.11.0

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[U-Boot] [PATCH] SPL: Add spl_early_board_init() generic function
by Lukasz Majewski 16 Jan '17

16 Jan '17

Some boards do require early adjustments (due to e.g. HW fix) in SPL code. In this particular case such operations must be performed just before ANY external IC is accessed (good example here is the I2C early bus access). Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- common/spl/Kconfig | 8 ++++++++ common/spl/spl.c | 6 ++++++ include/spl.h | 4 ++++ 3 files changed, 18 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index bb99f1f..7e6f9c4 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -185,6 +185,14 @@ config SPL_SAVEENV "reboot_image" and act accordingly and change the reboot_image to default mode using setenv and save the environemnt. +config SPL_EARLY_BOARD_INIT + bool "Support early board init code" + depends on SPL + help + Enable support for very early SPL board code adjustments. + Some boards require having adjustements done before any + peripherals being operational (e.g. I2C, SPI, UART). + config SPL_ETH_SUPPORT bool "Support Ethernet" depends on SPL_ENV_SUPPORT diff --git a/common/spl/spl.c b/common/spl/spl.c index bdb165a..a15647b 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -393,6 +393,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2) struct spl_image_info spl_image; int i; +#ifdef CONFIG_SPL_EARLY_BOARD_INIT + debug(">>spl:early_board_init()\n"); + + spl_early_board_init(); +#endif + debug(">>spl:board_init_r()\n"); #if defined(CONFIG_SYS_SPL_MALLOC_START) diff --git a/include/spl.h b/include/spl.h index e080a82..00a2058 100644 --- a/include/spl.h +++ b/include/spl.h @@ -215,6 +215,10 @@ int spl_init(void); void spl_board_init(void); #endif +#ifdef CONFIG_SPL_EARLY_BOARD_INIT +void spl_early_board_init(void); +#endif + /** * spl_was_boot_source() - check if U-Boot booted from SPL * -- 2.1.4

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[U-Boot] [PATCH v2 00/10] imx6ul: Add Engicam Is.IoT MX6UL support
by Jagan Teki 15 Jan '17

15 Jan '17

From: Jagan Teki <jagan(a)amarulasolutions.com> This patch set support Engicam Is.IoT MX6UL board support. Jagan Teki (10): configs: imx6: Don't define USDHC2_BASE_ADDR arm: imx6ul: Add Engicam Is.IoT MX6UL Starter Kit initial support arm: dts: imx6ul-isiot: Add I2C nodes imx6: isiotmx6ul: Add I2C support arm: dts: imx6ul-isiot: Add FEC node imx6: isiotmx6ul: Add FEC support arm: dts: imx6ul-isiot: Add eMMC node imx6: isiotmx6ul: Add NAND support imx6: isiotmx6ul: Add nandboot env support imx6ul: isiotmx6ul: Enable I2C support arch/arm/cpu/armv7/mx6/Kconfig | 13 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-isiot.dts | 170 ++++++++++++++++++ board/engicam/isiotmx6ul/Kconfig | 12 ++ board/engicam/isiotmx6ul/MAINTAINERS | 7 + board/engicam/isiotmx6ul/Makefile | 6 + board/engicam/isiotmx6ul/README | 28 +++ board/engicam/isiotmx6ul/isiotmx6ul.c | 316 ++++++++++++++++++++++++++++++++++ configs/imx6ul_isiot_mmc_defconfig | 47 +++++ configs/imx6ul_isiot_nand_defconfig | 49 ++++++ include/configs/imx6qdl_icore.h | 2 +- include/configs/imx6ul_geam.h | 2 +- include/configs/imx6ul_isiot.h | 205 ++++++++++++++++++++++ 13 files changed, 857 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/imx6ul-isiot.dts create mode 100644 board/engicam/isiotmx6ul/Kconfig create mode 100644 board/engicam/isiotmx6ul/MAINTAINERS create mode 100644 board/engicam/isiotmx6ul/Makefile create mode 100644 board/engicam/isiotmx6ul/README create mode 100644 board/engicam/isiotmx6ul/isiotmx6ul.c create mode 100644 configs/imx6ul_isiot_mmc_defconfig create mode 100644 configs/imx6ul_isiot_nand_defconfig create mode 100644 include/configs/imx6ul_isiot.h -- 1.9.1

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[U-Boot] [PATCH] igep00x0: enable CONFIG_FDT_FIXUP_PARTITIONS
by Ladislav Michl 15 Jan '17

15 Jan '17

SPL partition size depends on sector size and we want kernel to use the same layout, so let U-Boot modify FDT accordingly. Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- board/isee/igep00x0/igep00x0.c | 17 +++++++++++++++++ configs/igep0020_defconfig | 2 ++ configs/igep0030_defconfig | 2 ++ configs/igep0032_defconfig | 2 ++ 4 files changed, 23 insertions(+) diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 669f3dde7f..ae7959b1eb 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -23,6 +23,8 @@ #include <linux/mtd/nand.h> #include <linux/mtd/onenand.h> #include <jffs2/load_kernel.h> +#include <mtd_node.h> +#include <fdt_support.h> #include "igep00x0.h" DECLARE_GLOBAL_DATA_PTR; @@ -210,6 +212,21 @@ void board_mmc_power_init(void) } #endif +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + static struct node_info nodes[] = { + { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, + { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, }, + }; + + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + return 0; +} +#endif + void set_fdt(void) { switch (gd->bd->bi_arch_number) { diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig index c25b6b85a3..9e99c0c10a 100644 --- a/configs/igep0020_defconfig +++ b/configs/igep0020_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_TARGET_OMAP3_IGEP00X0=y +CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -35,3 +36,4 @@ CONFIG_CMD_UBI=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig index 925c42fd44..3478d4dd74 100644 --- a/configs/igep0030_defconfig +++ b/configs/igep0030_defconfig @@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_TARGET_OMAP3_IGEP00X0=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -27,3 +28,4 @@ CONFIG_CMD_UBI=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig index dad8dfaf0c..c72fb58e3b 100644 --- a/configs/igep0032_defconfig +++ b/configs/igep0032_defconfig @@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_TARGET_OMAP3_IGEP00X0=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -27,3 +28,4 @@ CONFIG_CMD_UBI=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_FDT_FIXUP_PARTITIONS=y -- 2.11.0

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[U-Boot] [PATCH v2] odroid-c2: Enable distro boot
by Andreas Färber 15 Jan '17

15 Jan '17

Use the generic "distro" boot framework to enable automatic DHCP boot. The fdt and kernel addresses are adopted from downstream; ramdisk and scriptaddr addresses were chosen arbitrarily. Signed-off-by: Andreas Färber <afaerber(a)suse.de> --- Kconfig | 1 + configs/odroid-c2_defconfig | 1 - include/configs/meson-gxbb-common.h | 14 ++++++++++++++ include/configs/odroid-c2.h | 2 ++ 4 files changed, 17 insertions(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index 3f79f6f..166fbf8 100644 --- a/Kconfig +++ b/Kconfig @@ -57,6 +57,7 @@ config DISTRO_DEFAULTS bool "Select defaults suitable for booting general purpose Linux distributions" default y if ARCH_SUNXI || TEGRA default y if ARCH_LS2080A + default y if ARCH_MESON default y if ARCH_ROCKCHIP default n select CMD_BOOTZ if ARM && !ARM64 diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index 7d0b2b1..119ab07 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -13,7 +13,6 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index 3bba2e6..75f6dc5 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -40,4 +40,18 @@ #include <config_distro_defaults.h> +#define BOOT_TARGET_DEVICES(func) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x01000000\0" \ + "scriptaddr=0x1f000000\0" \ + "kernel_addr_r=0x01080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x10000000\0" \ + MESON_FDTFILE_SETTING \ + BOOTENV + #endif /* __MESON_GXBB_COMMON_CONFIG_H */ diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h index 1d5b3d5..bf7e1af 100644 --- a/include/configs/odroid-c2.h +++ b/include/configs/odroid-c2.h @@ -12,6 +12,8 @@ #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE 115200 +#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0" + #include <configs/meson-gxbb-common.h> #endif /* __CONFIG_H */ -- 2.10.2

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[U-Boot] [PATCH] MAINTAINERS: Add maintainer for TI security related files
by Andrew F. Davis 15 Jan '17

15 Jan '17

Changes involving High-Security boards should be CC'd for additional assessment of the security implications. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- Recently some fastboot additions have been made that may effect security on our HS boards by letting some boot methods work around our chain-of- trust. It would be nice to get a CC for changes that directly effect these HS boards so I have a chance to check for this kind of thing. MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 793ff49f68..1ea7ae013a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,6 +434,17 @@ S: Maintained F: drivers/spmi/ F: include/spmi/ +TI SYSTEM SECURITY +M: Andrew F. Davis <afd(a)ti.com> +S: Supported +F: arch/arm/mach-omap2/omap5/sec_entry_cpu1.S +F: arch/arm/mach-omap2/omap5/sec-fxns.c +F: arch/arm/mach-omap2/sec-common.c +F: arch/arm/mach-omap2/config_secure.mk +F: configs/am43xx_hs_evm_defconfig +F: configs/am57xx_hs_evm_defconfig +F: configs/dra7xx_hs_evm_defconfig + TQ GROUP #M: Martin Krause <martin.krause(a)tq-systems.de> S: Orphaned (Since 2016-02) -- 2.11.0

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[U-Boot] [PATCH v2] odroid-c2: Enable distro boot
by Andreas Färber 15 Jan '17

15 Jan '17

Use the generic "distro" boot framework to enable automatic DHCP boot. The fdt and kernel addresses are adopted from downstream; ramdisk and scriptaddr addresses were chosen arbitrarily. Signed-off-by: Andreas Färber <afaerber(a)suse.de> --- Kconfig | 1 + configs/odroid-c2_defconfig | 1 - include/configs/meson-gxbb-common.h | 14 ++++++++++++++ include/configs/odroid-c2.h | 2 ++ 4 files changed, 17 insertions(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index 3f79f6f..166fbf8 100644 --- a/Kconfig +++ b/Kconfig @@ -57,6 +57,7 @@ config DISTRO_DEFAULTS bool "Select defaults suitable for booting general purpose Linux distributions" default y if ARCH_SUNXI || TEGRA default y if ARCH_LS2080A + default y if ARCH_MESON default y if ARCH_ROCKCHIP default n select CMD_BOOTZ if ARM && !ARM64 diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index 7d0b2b1..119ab07 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -13,7 +13,6 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index 3bba2e6..75f6dc5 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -40,4 +40,18 @@ #include <config_distro_defaults.h> +#define BOOT_TARGET_DEVICES(func) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x01000000\0" \ + "scriptaddr=0x1f000000\0" \ + "kernel_addr_r=0x01080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x10000000\0" \ + MESON_FDTFILE_SETTING \ + BOOTENV + #endif /* __MESON_GXBB_COMMON_CONFIG_H */ diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h index 1d5b3d5..bf7e1af 100644 --- a/include/configs/odroid-c2.h +++ b/include/configs/odroid-c2.h @@ -12,6 +12,8 @@ #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE 115200 +#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0" + #include <configs/meson-gxbb-common.h> #endif /* __CONFIG_H */ -- 2.10.2

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[U-Boot] [PATCH] ti_armv7_common: env: Use FIT image configs by default
by Andrew F. Davis 15 Jan '17

15 Jan '17

This allows us to specify a FIT configuration that will automatically use the correct images from the FIT blob. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- include/configs/ti_armv7_common.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index dbe494a6e3..6a94cd7bb4 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -124,8 +124,7 @@ "fit_bootfile=fitImage.itb\0" \ "update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \ "args_fit=setenv bootargs console=${console} \0" \ - "loadfit=run args_fit; bootm ${loadaddr}:kernel@1 " \ - "${loadaddr}:ramdisk@1 ${loadaddr}:${fdtfile};\0" \ + "loadfit=run args_fit; bootm ${loadaddr}#${fdtfile};\0" \ /* * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, -- 2.11.0

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[U-Boot] [PATCH] arm: omap-common: add secure ROM signature verify index for AM33xx
by Andrew F. Davis 15 Jan '17

15 Jan '17

On AM33xx devices the secure ROM uses a different call index for signature verification, the function and arguments are the same. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- arch/arm/mach-omap2/sec-common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 246a2393da..c5a000ac3a 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -21,7 +21,11 @@ #include <spl.h> /* Index for signature verify ROM API */ +#ifdef CONFIG_AM33XX +#define API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX (0x0000000C) +#else #define API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX (0x0000000E) +#endif static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN); -- 2.11.0

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[U-Boot] [PATCH] cmd: sata: fix init command return value
by Gary Bisson 15 Jan '17

15 Jan '17

Since commit aa6ab905b2, sata_initialize returns -1 if init_sata or scan_sata fails. But this return value becomes the do_sata return value which is equivalent to CMD_RET_USAGE. In case one issues 'sata init' and that the hardware fails to initialize, there's no need to display the command usage. Instead the command shoud just return the CMD_RET_FAILURE value. Fixes: aa6ab905b2 (sata: fix sata command can not being executed bug) Signed-off-by: Gary Bisson <gary.bisson(a)boundarydevices.com> --- cmd/sata.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/cmd/sata.c b/cmd/sata.c index f56622acc2..4c53022ff6 100644 --- a/cmd/sata.c +++ b/cmd/sata.c @@ -28,14 +28,15 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (sata_curr_device != -1) sata_stop(); - return sata_initialize(); + return (sata_initialize() < 0) ? + CMD_RET_FAILURE : CMD_RET_SUCCESS; } /* If the user has not yet run `sata init`, do it now */ if (sata_curr_device == -1) { rc = sata_initialize(); if (rc == -1) - return rc; + return CMD_RET_FAILURE; sata_curr_device = rc; } -- 2.11.0

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