January 2017 - U-Boot

[U-Boot] [PATCH 2/2][v3] arch: arm: update the IFC IP input clock
by Prabhakar Kushwaha 23 Jan '17

23 Jan '17

IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. So update IFC IP clock to be defined as per predefined clock divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Split the patch in 2 patch set Changes for v3: Rebased on top of u-boot commit arch/arm/cpu/armv7/ls102xa/clock.c | 9 +-------- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 10 ++-------- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 10 ++-------- 3 files changed, 5 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index 7a337e1..b7d61ad 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -19,10 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#ifdef CONFIG_FSL_IFC - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - u32 ccr; -#endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR); unsigned int cpu; const u8 core_cplx_pll[6] = { @@ -74,10 +70,7 @@ void get_sys_info(struct sys_info *sys_info) } #if defined(CONFIG_FSL_IFC) - ccr = in_be32(&ifc_regs.gregs->ifc_ccr); - ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - - sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus; #endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 3da7037..2d7775e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -22,10 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#ifdef CONFIG_FSL_IFC - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - u32 ccr; -#endif #if (defined(CONFIG_FSL_ESDHC) &&\ defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\ defined(CONFIG_SYS_DPAA_FMAN) @@ -156,10 +152,8 @@ void get_sys_info(struct sys_info *sys_info) #endif #if defined(CONFIG_FSL_IFC) - ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); - ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - - sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus / + CONFIG_SYS_FSL_IFC_CLK_DIV; #endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index f8fefc7..ab46431 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -26,10 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#ifdef CONFIG_FSL_IFC - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - u32 ccr; -#endif struct ccsr_clk_cluster_group __iomem *clk_grp[2] = { (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR), (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR) @@ -128,10 +124,8 @@ void get_sys_info(struct sys_info *sys_info) } #if defined(CONFIG_FSL_IFC) - ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); - ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - - sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus / + CONFIG_SYS_FSL_IFC_CLK_DIV; #endif } -- 2.7.4

1 0

[U-Boot] [PATCH 1/2][v3] arch: powerpc: update the IFC IP input clock
by Prabhakar Kushwaha 23 Jan '17

23 Jan '17

IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. So update IFC IP clock to be defined as per predefined clock divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Split the patch in 2 patch set Changes for v3: Rebased on top of u-boot commit README | 3 +++ arch/powerpc/cpu/mpc85xx/Kconfig | 21 +++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/speed.c | 10 ++-------- 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/README b/README index a95348a..9fda381 100644 --- a/README +++ b/README @@ -504,6 +504,9 @@ The following options need to be configured: CONFIG_SYS_FSL_IFC_LE Defines the IFC controller register space as Little Endian + CONFIG_SYS_FSL_IFC_CLK_DIV + Defines divider of platform clock(clock input to IFC controller). + CONFIG_SYS_FSL_PBL_PBI It enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 704f65b..bbe6d69 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1248,6 +1248,27 @@ config SYS_PPC_E500_DEBUG_TLB symbol should be set to the TLB1 entry to be used for this purpose. If unsure, do not change. +config SYS_FSL_IFC_CLK_DIV + int "Divider of platform clock" + depends on FSL_IFC + default 2 if ARCH_B4420 || \ + ARCH_B4860 || \ + ARCH_T1024 || \ + ARCH_T1023 || \ + ARCH_T1040 || \ + ARCH_T1042 || \ + ARCH_T4160 || \ + ARCH_T4240 + default 1 if ARCH_BSC9131 || \ + ARCH_BSC9132 || \ + ARCH_C29X || \ + ARCH_P1010 || \ + ARCH_T2080 || \ + ARCH_T2081 + help + Defines divider of platform clock(clock input to + IFC controller). + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index fcf5d92..adba092 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(sys_info_t *sys_info) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_FSL_IFC - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - u32 ccr; -#endif #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; @@ -640,10 +636,8 @@ void get_sys_info(sys_info_t *sys_info) #endif #if defined(CONFIG_FSL_IFC) - ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); - ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - - sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus / + CONFIG_SYS_FSL_IFC_CLK_DIV; #endif } -- 2.7.4

1 0

[U-Boot] [BUG] am335x: SPL: fails to load u-boot.img from vfat partition on eMMC
by Heiko Schocher 23 Jan '17

23 Jan '17

Hello Stefan, the am335x based shc board fails loading u-boot.img in SPL from vfat partition on eMMC card with current HEAD of mainline U-Boot: U-Boot SPL 2017.01-00294-g0c9e85f (Jan 23 2017 - 11:23:05) SHC MPU reference clock runs at 6 MHz Setting MPU clock to 594 MHz Enabling Spread Spectrum of 18 permille for MPU Trying to boot from MMC2 reading u-boot.img reading u-boot.img Detected with my weekly tbot tests of U-Boot. An automated git bisect cycle with tbot shows your patch: $ git bisect visualize commit 8d48c92b45aea91e2a2be90f2ed93677e85526f1 Author: Stefan BrÃ¼ns <stefan.bruens(a)rwth-aachen.de> Date: Sat Dec 17 03:55:10 2016 +0100 fs/fat: simplify get_fatent for FAT12 Instead of shuffling bits from two adjacent 16 bit words, use one 16 bit word with the appropriate byte offset in the buffer. Signed-off-by: Stefan Brüns <stefan.bruens(a)rwth-aachen.de> $ git bisect log git bisect start # bad: [0c9e85f67cd86d2d7a3424ea3ebff0e6db7a3915] Merge branch 'master' of git://git.denx.de/u-boot-uniphier git bisect bad 0c9e85f67cd86d2d7a3424ea3ebff0e6db7a3915 # good: [0c1d74fda7c0063eeca4d8d9fa8674e6ec2ef685] image: Add crypto_algo struct for RSA info git bisect good 0c1d74fda7c0063eeca4d8d9fa8674e6ec2ef685 # good: [fe9822556e051e6c24a3832532166ade00a81a8c] Merge branch 'master' of git://git.denx.de/u-boot-uniphier git bisect good fe9822556e051e6c24a3832532166ade00a81a8c # bad: [7876dcb5d46057403a715771a75c483add6a64c1] ARM64: zynqmp: Add missing earlycon for ep108 git bisect bad 7876dcb5d46057403a715771a75c483add6a64c1 # good: [36737f22b78a475c6bbc8a0467b51e4d95b52a7d] Merge git://git.denx.de/u-boot-dm git bisect good 36737f22b78a475c6bbc8a0467b51e4d95b52a7d # bad: [8098b8cb3f15c8b203de133106e4bce4b8fe956d] configs: engicam: Enable CONFIG_IMAGE_FORMAT_LEGACY git bisect bad 8098b8cb3f15c8b203de133106e4bce4b8fe956d # good: [6c1a808052ba6a875df7aa450b6df4b199f3a281] fs/fat: Avoid corruption of sectors following the FAT git bisect good 6c1a808052ba6a875df7aa450b6df4b199f3a281 # bad: [3d3a74cc8c774345be7d1661b215555ad41f4515] mmc: move MMC_SDHCI_IO_ACCESSORS to Kconfig git bisect bad 3d3a74cc8c774345be7d1661b215555ad41f4515 # bad: [3cc5bbb8e68dc67b7c3d2fdebef69408e5271469] fs/ext4: Initialize group descriptor size for revision level 0 filesystems git bisect bad 3cc5bbb8e68dc67b7c3d2fdebef69408e5271469 # bad: [085be482f6c62614ddbe51000a09db9dec360e90] ARM: revive CONFIG_USE_ARCH_MEMCPY/MEMSET for UniPhier and Tegra git bisect bad 085be482f6c62614ddbe51000a09db9dec360e90 # bad: [8d48c92b45aea91e2a2be90f2ed93677e85526f1] fs/fat: simplify get_fatent for FAT12 git bisect bad 8d48c92b45aea91e2a2be90f2ed93677e85526f1 # good: [b8948d2aef80717d3d2c4f37ec086ce3ea5ad24f] fs/fat: merge readwrite get_fatent_value() with readonly get_fatent() git bisect good b8948d2aef80717d3d2c4f37ec086ce3ea5ad24f # first bad commit: [8d48c92b45aea91e2a2be90f2ed93677e85526f1] fs/fat: simplify get_fatent for FAT12 Reverting this patch, and it works as expected: U-Boot SPL 2017.01-00294-g0c9e85f-dirty (Jan 23 2017 - 12:53:29) SHC MPU reference clock runs at 6 MHz Setting MPU clock to 594 MHz Enabling Spread Spectrum of 18 permille for MPU Trying to boot from MMC2 reading u-boot.img reading u-boot.img U-Boot 2017.01-00294-g0c9e85f-dirty (Jan 23 2017 - 12:53:29 +0100) CPU : AM335X-GP rev 2.1 I2C: ready DRAM: 512 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 Net: cpsw Enter 'shc' to enter prompt (times out) 0 Enter 'noautoboot' to enter prompt without timeout U-Boot# Any ideas what could be wrong here? Thanks! bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

2 1

[U-Boot] [PATCH] arm: layerscape: Enable UUID & GPT partition for NXP's ARM SoC
by Prabhakar Kushwaha 23 Jan '17

23 Jan '17

Enable UUID and GPT partition support for NXP's ARM based SoCs i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A. Also enable DOS partition for LS1012AFRDM boards. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- include/configs/ls1012afrdm.h | 5 +++++ include/configs/ls1012aqds.h | 4 ++++ include/configs/ls1012ardb.h | 4 ++++ include/configs/ls1021aiot.h | 3 +++ include/configs/ls1021aqds.h | 3 +++ include/configs/ls1021atwr.h | 3 +++ include/configs/ls1043aqds.h | 4 ++++ include/configs/ls1043ardb.h | 4 ++++ include/configs/ls1046aqds.h | 4 ++++ include/configs/ls1046ardb.h | 4 ++++ include/configs/ls2080aqds.h | 3 +++ include/configs/ls2080ardb.h | 3 +++ 12 files changed, 44 insertions(+) diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index f6f88e8..94f7460 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -42,6 +42,11 @@ #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif +#define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 0cc1791..ec4b825 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -154,6 +154,10 @@ #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 15410dd..1e8cc45 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -67,6 +67,10 @@ #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 7af4bc4..a441022 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -180,6 +180,9 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 128da8a..86b42dd 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -398,6 +398,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 1458332..25bebc0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -299,6 +299,9 @@ #define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 561a05a..431c8f8 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -100,6 +100,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION #define CONFIG_BOARD_LATE_INIT +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 71c26bd..36df331 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -310,6 +310,10 @@ #define SCSI_DEV_ID 0x9170 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #include <asm/fsl_secure_boot.h> #endif /* __LS1043ARDB_H__ */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 29e0aa5..3618a06 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -143,6 +143,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION #define CONFIG_BOARD_LATE_INIT +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 2fe8fc1..42597ac 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -225,6 +225,10 @@ #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \ "$kernel_start $kernel_size;" \ "bootm $kernel_load" diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 838568f..b3872b5 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -63,6 +63,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 31df781..9ffb48c 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -71,6 +71,9 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ -- 2.7.4

4 8

[U-Boot] [PATCH] Revert "build: Always build the libfdt python module"
by Simon Glass 23 Jan '17

23 Jan '17

This appears to cause problems with powerpc: +x86_64-linux-gnu-gcc: error: unrecognized command line option ‘-melf32ppclinux’ +error: command 'x86_64-linux-gnu-gcc' failed with exit status 1 +make[2]: *** [tools/_libfdt.so] Error 1 +make[1]: *** [tools] Error 2 +make: *** [sub-make] Error 2 It may need to be made ARM-specific. This reverts commit 1905c8fc711a527ff10550425498bc77e4db9ac3. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- tools/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index a609d058595..5b81dde4b06 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -111,7 +111,7 @@ fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o # Build a libfdt Python module if swig is available # Use 'sudo apt-get install swig libpython-dev' to enable this -hostprogs-y += \ +hostprogs-$(CONFIG_SPL_OF_PLATDATA) += \ $(if $(shell which swig 2> /dev/null),_libfdt.so) _libfdt.so-sharedobjs += $(LIBFDT_OBJS) libfdt: -- 2.11.0.483.g087da7b7c-goog

4 3

[U-Boot] [BUG] powerpc: tqm5200: does not compile with current HEAD
by Heiko Schocher 23 Jan '17

23 Jan '17

Hello, building powerpc based tqm5200 board fails with current HEAD (at least on fedora host): pollux:u-boot-tqm5200 hs [master] $ ./tools/buildman/buildman TQM5200S boards.cfg is up to date. Nothing to do. Building current source for 2 boards (2 threads, 4 jobs per thread) powerpc: + TQM5200S +In file included from /usr/include/python2.7/pyconfig.h:6:0, + from /usr/include/python2.7/Python.h:8, + from tools/libfdt_wrap.c:147: +/usr/include/python2.7/pyconfig-64.h:1202:0: Warnung: »_POSIX_C_SOURCE« redefiniert + #define _POSIX_C_SOURCE 200112L + +In file included from /usr/include/stdint.h:25:0, + from /usr/lib/gcc/x86_64-redhat-linux/6.3.1/include/stdint.h:9, + from include/compiler.h:19, + from include/libfdt_env.h:12, + from <Kommandozeile>:0: +/usr/include/features.h:225:0: Anmerkung: dies ist die Stelle der vorherigen Definition + # define _POSIX_C_SOURCE 200809L +/usr/include/python2.7/pyconfig-64.h:1224:0: Warnung: »_XOPEN_SOURCE« redefiniert + #define _XOPEN_SOURCE 600 +/usr/include/features.h:166:0: Anmerkung: dies ist die Stelle der vorherigen Definition + # define _XOPEN_SOURCE 700 +gcc: Fehler: nicht erkannte Kommandozeilenoption »-melf32ppclinux« +error: command 'gcc' failed with exit status 1 +make[2]: *** [tools/_libfdt.so] Fehler 1 +make[1]: *** [tools] Fehler 2 +make: *** [sub-make] Fehler 2 [...] Also no chance using ELDK ... reverting patch: 1905c8fc711a: build: Always build the libfdt python module and I can again build the TQM5200 board... Hmm.. first I wonder, why do we need at all such things like SWIG for a U-Boot build... ? Is this really needed? Here the Code in tools/Makefile: # Build a libfdt Python module if swig is available # Use 'sudo apt-get install swig libpython-dev' to enable this hostprogs-$(CONFIG_SPL_OF_PLATDATA) += \ $(if $(shell which swig 2> /dev/null),_libfdt.so) _libfdt.so-sharedobjs += $(LIBFDT_OBJS) libfdt: [...] Comment says we need swig *and* libpython-dev ... but the check is only for "swig" ... What is when there is no "libpython-dev" ? Like on fedora: # dnf install libpython-dev Last metadata expiration check: 1:50:58 ago on Mon Jan 23 07:49:26 2017. No package libpython-dev available. Error: Unable to find a match. Ok, the following patch applied to mainline, and current HEAD of U-Boot builds again for the tqm5200 board on my fedora host: diff --git a/tools/Makefile b/tools/Makefile index a609d05..a8a5599 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -112,7 +112,7 @@ fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o # Build a libfdt Python module if swig is available # Use 'sudo apt-get install swig libpython-dev' to enable this hostprogs-y += \ - $(if $(shell which swig 2> /dev/null),_libfdt.so) + $(if $(shell which swig libpython-dev 2> /dev/null),_libfdt.so) _libfdt.so-sharedobjs += $(LIBFDT_OBJS) libfdt: Any comments? Ideas? bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

3 3

[U-Boot] [PATCH] BOARD: MCCMON6: Provide support for iMX6q based mccmon6 board
by Lukasz Majewski 23 Jan '17

23 Jan '17

This patch provides u-boot support for Liebherr (LWN) mccmon6 board. Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- Changes for v5: - Remove network configuration data from envs - Clean up the envs - remove duplicated env variables Changes for v4: - Update board/liebherr/mccmon6/MAINTAINERS entry to quiet buildman warnings Changes for v3: - Define CONFIG_SYS_UBOOT_START to load u-boot image from NOR to correct address (so the SPL: NOR: Add CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE define to enable whole image copy from NOR can be dropped) - Update author information Changes for v2: - Provide space after "quiet" console boot parameter to not pollute next parameters --- This patch applies on mainline u-boot: SHA1: 2d8d190c8394b43c0989cdb04a50cb48d4e1f8da --- arch/arm/cpu/armv7/mx6/Kconfig | 5 + board/liebherr/mccmon6/Kconfig | 12 + board/liebherr/mccmon6/MAINTAINERS | 7 + board/liebherr/mccmon6/Makefile | 8 + board/liebherr/mccmon6/mccmon6.c | 490 +++++++++++++++++++++++++++ board/liebherr/mccmon6/mon6_imximage_nor.cfg | 9 + board/liebherr/mccmon6/mon6_imximage_sd.cfg | 9 + board/liebherr/mccmon6/spl.c | 317 +++++++++++++++++ configs/mccmon6_nor_defconfig | 36 ++ configs/mccmon6_sd_defconfig | 37 ++ include/configs/mccmon6.h | 324 ++++++++++++++++++ 11 files changed, 1254 insertions(+) create mode 100644 board/liebherr/mccmon6/Kconfig create mode 100644 board/liebherr/mccmon6/MAINTAINERS create mode 100644 board/liebherr/mccmon6/Makefile create mode 100644 board/liebherr/mccmon6/mccmon6.c create mode 100644 board/liebherr/mccmon6/mon6_imximage_nor.cfg create mode 100644 board/liebherr/mccmon6/mon6_imximage_sd.cfg create mode 100644 board/liebherr/mccmon6/spl.c create mode 100644 configs/mccmon6_nor_defconfig create mode 100644 configs/mccmon6_sd_defconfig create mode 100644 include/configs/mccmon6.h diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index c646966..9eddd7e 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -114,6 +114,10 @@ config TARGET_KOSAGI_NOVENA bool "Kosagi Novena" select SUPPORT_SPL +config TARGET_MCCMON6 + bool "mccmon6" + select SUPPORT_SPL + config TARGET_MX6CUBOXI bool "Solid-run mx6 boards" select SUPPORT_SPL @@ -327,6 +331,7 @@ source "board/phytec/pcm058/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" +source "board/liebherr/mccmon6/Kconfig" source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" diff --git a/board/liebherr/mccmon6/Kconfig b/board/liebherr/mccmon6/Kconfig new file mode 100644 index 0000000..4cc7fc2 --- /dev/null +++ b/board/liebherr/mccmon6/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MCCMON6 + +config SYS_BOARD + default "mccmon6" + +config SYS_VENDOR + default "liebherr" + +config SYS_CONFIG_NAME + default "mccmon6" + +endif diff --git a/board/liebherr/mccmon6/MAINTAINERS b/board/liebherr/mccmon6/MAINTAINERS new file mode 100644 index 0000000..c9c7183 --- /dev/null +++ b/board/liebherr/mccmon6/MAINTAINERS @@ -0,0 +1,7 @@ +MCCMON6 BOARD +M: Lukasz Majewski <lukma(a)denx.de> +S: Maintained +F: board/liebherr/mccmon6/ +F: include/configs/mccmon6.h +F: configs/mccmon6_nor_defconfig +F: configs/mccmon6_sd_defconfig diff --git a/board/liebherr/mccmon6/Makefile b/board/liebherr/mccmon6/Makefile new file mode 100644 index 0000000..e37baf8 --- /dev/null +++ b/board/liebherr/mccmon6/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2016-2017 +# Lukasz Majewski, DENX Software Engineering, lukma(a)denx.de +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mccmon6.o spl.o diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c new file mode 100644 index 0000000..eb5eae4 --- /dev/null +++ b/board/liebherr/mccmon6/mccmon6.c @@ -0,0 +1,490 @@ +/* + * Copyright (C) 2016-2017 + * Lukasz Majewski, DENX Software Engineering, lukma(a)denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/spi.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/io.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <netdev.h> +#include <micrel.h> +#include <phy.h> +#include <input.h> +#include <i2c.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define ETH_PHY_RESET IMX_GPIO_NR(1, 27) +#define ECSPI3_CS0 IMX_GPIO_NR(4, 24) +#define ECSPI3_FLWP IMX_GPIO_NR(4, 27) +#define NOR_WP IMX_GPIO_NR(1, 1) +#define DISPLAY_EN IMX_GPIO_NR(1, 2) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + /* Carrier MicroSD Card Detect */ + IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL + | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK + | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL + | MUX_PAD_CTRL(ENET_PAD_CTRL)), + /* KSZ9031 PHY Reset */ + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +static void setup_iomux_enet(void) +{ + SETUP_IOMUX_PADS(enet_pads); + + /* Reset KSZ9031 PHY */ + gpio_direction_output(ETH_PHY_RESET, 0); + mdelay(10); + gpio_set_value(ETH_PHY_RESET, 1); + udelay(100); +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR}, + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + /* + * eMMC don't have card detect pin - since it is soldered to the + * PCB board + */ + ret = 1; + break; + } + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + u32 index = 0; + + /* + * MMC MAP + * (U-Boot device node) (Physical Port) + * mmc0 Soldered on board eMMC device + * mmc1 MicroSD card + */ + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 8; + break; + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + gpio_direction_input(USDHC2_CD_GPIO); + break; + default: + printf("Warning: More USDHC controllers (%d) than supported (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; +} + +static iomux_v3_cfg_t const eimnor_pads[] = { + IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void eimnor_cs_setup(void) +{ + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; + + + /* NOR configuration */ + writel(0x00620181, &weim_regs->cs0gcr1); + writel(0x00000001, &weim_regs->cs0gcr2); + writel(0x0b020000, &weim_regs->cs0rcr1); + writel(0x0000b000, &weim_regs->cs0rcr2); + writel(0x0804a240, &weim_regs->cs0wcr1); + writel(0x00000000, &weim_regs->cs0wcr2); + + writel(0x00000120, &weim_regs->wcr); + writel(0x00000010, &weim_regs->wiar); + writel(0x00000000, &weim_regs->ear); + + set_chipselect_size(CS0_128); +} + +static void setup_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + gpio_direction_output(NOR_WP, 1); + + enable_eim_clk(1); + eimnor_cs_setup(); +} + +/* mccmon6 board has SPI Flash is connected to SPI3 */ +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1; +} + +static iomux_v3_cfg_t const ecspi3_pads[] = { + /* SPI3 */ + IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), +}; + +void setup_spi(void) +{ + SETUP_IOMUX_PADS(ecspi3_pads); + + enable_spi_clk(true, 2); + + /* set cs0 to high */ + gpio_direction_output(ECSPI3_CS0, 1); + + /* set flwp to high */ + gpio_direction_output(ECSPI3_FLWP, 1); +} + +struct i2c_pads_info mx6q_i2c1_pad_info = { + .scl = { + .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info mx6q_i2c2_pad_info = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 13) + } +}; + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + gpio_direction_output(DISPLAY_EN, 1); + + setup_eimnor(); + setup_spi(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); + + return 0; +} + +int board_late_init(void) +{ + setenv("board_name", "mccmon6"); + + return 0; +} + +int checkboard(void) +{ + puts("Board: MCCMON6\n"); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Default setting for GMII Clock Pad Skew Register 0x1EF: + * MMD Address 0x2h, Register 0x8h + * + * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew + * RX_CLK Pad Skew 0xF -> 0.9 nsec skew + * + * Adjustment -> write 0x3FF: + * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew + * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew + * + */ + ksz9031_phy_extended_write(phydev, 0x2, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF); + + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF); + + ksz9031_phy_extended_write(phydev, 0x2, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x3333); + + ksz9031_phy_extended_write(phydev, 0x2, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x2052); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + setup_eimnor(); + + gpio_direction_output(DISPLAY_EN, 1); +} +#endif /* CONFIG_SPL_BOARD_INIT */ + +#ifdef CONFIG_SPL_BUILD +void board_boot_order(u32 *spl_boot_list) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC2: + case BOOT_DEVICE_MMC1: + spl_boot_list[0] = BOOT_DEVICE_MMC2; + spl_boot_list[1] = BOOT_DEVICE_MMC1; + break; + + case BOOT_DEVICE_NOR: + spl_boot_list[0] = BOOT_DEVICE_NOR; + break; + } +} +#endif /* CONFIG_SPL_BUILD */ + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + char s[16]; + int ret; + /* + * We use BOOT_DEVICE_MMC1, but SD card is connected + * to MMC2 + * + * Correct "mapping" is delivered in board defined + * board_boot_order() function. + * + * SD card boot is regarded as a "development" one, + * hence we _always_ go through the u-boot. + * + */ + if (spl_boot_device() == BOOT_DEVICE_MMC1) + return 1; + + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + env_init(); + ret = getenv_f("boot_os", s, sizeof(s)); + if ((ret != -1) && (strcmp(s, "no") == 0)) + return 1; + + /* + * Check if SWUpdate recovery needs to be started + * + * recovery_status = NULL (not set - ret == -1) -> normal operation + * + * recovery_status = progress or + * recovery_status = failed or + * recovery_status = <any value> -> start SWUpdate + * + */ + ret = getenv_f("recovery_status", s, sizeof(s)); + if (ret != -1) + return 1; + + return 0; +} +#endif /* CONFIG_SPL_OS_BOOT */ diff --git a/board/liebherr/mccmon6/mon6_imximage_nor.cfg b/board/liebherr/mccmon6/mon6_imximage_nor.cfg new file mode 100644 index 0000000..35faa11 --- /dev/null +++ b/board/liebherr/mccmon6/mon6_imximage_nor.cfg @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2016-2017 + * Lukasz Majewski, DENX Software Engineering, lukma(a)denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +IMAGE_VERSION 2 +BOOT_FROM nor diff --git a/board/liebherr/mccmon6/mon6_imximage_sd.cfg b/board/liebherr/mccmon6/mon6_imximage_sd.cfg new file mode 100644 index 0000000..7a3063c --- /dev/null +++ b/board/liebherr/mccmon6/mon6_imximage_sd.cfg @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2016-2017 + * Lukasz Majewski, DENX Software Engineering, lukma(a)denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +IMAGE_VERSION 2 +BOOT_FROM sd diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c new file mode 100644 index 0000000..73beeaa --- /dev/null +++ b/board/liebherr/mccmon6/spl.c @@ -0,0 +1,317 @@ +/* + * Copyright (C) 2014 Wandboard + * Author: Tungyi Lin <tungyilin1127(a)gmail.com> + * Richard Hu <hakahu(a)gmail.com> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SPL_BUILD) +#include <asm/arch/mx6-ddr.h> +/* + * Driving strength: + * 0x30 == 40 Ohm + * 0x28 == 48 Ohm + */ + +#define IMX6DQ_DRIVE_STRENGTH 0x30 +#define IMX6SDL_DRIVE_STRENGTH 0x28 + +/* configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, + .dram_cas = IMX6DQ_DRIVE_STRENGTH, + .dram_ras = IMX6DQ_DRIVE_STRENGTH, + .dram_reset = IMX6DQ_DRIVE_STRENGTH, + .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, +}; + +/* configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6DQ_DRIVE_STRENGTH, + .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, +}; + +/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, + .dram_cas = IMX6SDL_DRIVE_STRENGTH, + .dram_ras = IMX6SDL_DRIVE_STRENGTH, + .dram_reset = IMX6SDL_DRIVE_STRENGTH, + .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, +}; + +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6SDL_DRIVE_STRENGTH, + .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, +}; + +/* H5T04G63AFR-PB */ +static struct mx6_ddr3_cfg h5t04g63afr = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* H5TQ2G63DFR-H9 */ +static struct mx6_ddr3_cfg h5tq2g63dfr = { + .mem_speed = 1333, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1350, + .trcmin = 4950, + .trasmin = 3600, +}; + +static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = { + .p0_mpwldectrl0 = 0x001f001f, + .p0_mpwldectrl1 = 0x001f001f, + .p1_mpwldectrl0 = 0x001f001f, + .p1_mpwldectrl1 = 0x001f001f, + .p0_mpdgctrl0 = 0x4301030d, + .p0_mpdgctrl1 = 0x03020277, + .p1_mpdgctrl0 = 0x4300030a, + .p1_mpdgctrl1 = 0x02780248, + .p0_mprddlctl = 0x4536393b, + .p1_mprddlctl = 0x36353441, + .p0_mpwrdlctl = 0x41414743, + .p1_mpwrdlctl = 0x462f453f, +}; + +/* DDR 64bit 2GB */ +static struct mx6_ddr_sysinfo mem_q = { + .dsize = 2, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { + .p0_mpwldectrl0 = 0x001f001f, + .p0_mpwldectrl1 = 0x001f001f, + .p1_mpwldectrl0 = 0x001f001f, + .p1_mpwldectrl1 = 0x001f001f, + .p0_mpdgctrl0 = 0x420e020e, + .p0_mpdgctrl1 = 0x02000200, + .p1_mpdgctrl0 = 0x42020202, + .p1_mpdgctrl1 = 0x01720172, + .p0_mprddlctl = 0x494c4f4c, + .p1_mprddlctl = 0x4a4c4c49, + .p0_mpwrdlctl = 0x3f3f3133, + .p1_mpwrdlctl = 0x39373f2e, +}; + +static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = { + .p0_mpwldectrl0 = 0x0040003c, + .p0_mpwldectrl1 = 0x0032003e, + .p0_mpdgctrl0 = 0x42350231, + .p0_mpdgctrl1 = 0x021a0218, + .p0_mprddlctl = 0x4b4b4e49, + .p0_mpwrdlctl = 0x3f3f3035, +}; + +/* DDR 64bit 1GB */ +static struct mx6_ddr_sysinfo mem_dl = { + .dsize = 2, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +/* DDR 32bit 512MB */ +static struct mx6_ddr_sysinfo mem_s = { + .dsize = 1, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +static void spl_dram_init(void) +{ + if (is_cpu_type(MXC_CPU_MX6SOLO)) { + mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr); + } else if (is_cpu_type(MXC_CPU_MX6DL)) { + mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr); + } else if (is_cpu_type(MXC_CPU_MX6Q)) { + mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); + mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr); + } + + udelay(100); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + gpr_init(); + + /* iomux */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig new file mode 100644 index 0000000..a320424 --- /dev/null +++ b/configs/mccmon6_nor_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MCCMON6=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_FLASH=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_OF_LIBFDT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_MTD=y +#CONFIG_CFI_FLASH=y \ No newline at end of file diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig new file mode 100644 index 0000000..2d13bac --- /dev/null +++ b/configs/mccmon6_sd_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MCCMON6=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_FLASH=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_OF_LIBFDT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_MTD=y +#CONFIG_CFI_FLASH=y \ No newline at end of file diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h new file mode 100644 index 0000000..0fa4401 --- /dev/null +++ b/include/configs/mccmon6.h @@ -0,0 +1,324 @@ +/* + * Copyright (C) 2016-2017 + * Lukasz Majewski, DENX Software Engineering, lukma(a)denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config_distro_defaults.h> +#include "mx6_common.h" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#include "imx6_spl.h" + +#define MACH_TYPE_WANDBOARD 4412 +#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000) +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000) +#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K) +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* + * Below defines are set but NOT really used since we by + * design force U-Boot run when we boot in development + * mode from SD card (SD2) + */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800) +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000) +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) + +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#undef CONFIG_SYS_NO_FLASH +/* NOR 16-bit mode */ +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_FLASH_VERIFY + +/* NOR Flash MTD */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } +#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } + +/* MTD support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +#define MTDIDS_DEFAULT "nor0=8000000.nor" +#define MTDPARTS_DEFAULT \ + "mtdparts=8000000.nor:" \ + "32m(a)0x0(mccmon6-image.nor)," \ + "256k(a)0x40000(u-boot-env.nor)," \ + "1m(a)0x80000(u-boot.nor)," \ + "8m(a)0x180000(kernel.nor)," \ + "8m(a)0x980000(swupdate-kernel.nor)," \ + "8m(a)0x1180000(swupdate-rootfs.nor)," \ + "128k(a)0x1980000(kernel-dtb.nor)," \ + "128k(a)0x19C0000(swupdate-kernel-dtb.nor)" + +/* USB Configs */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Ethernet Configuration */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdtfile=imx6q-mccmon6.dtb\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "boot_os=yes\0" \ + "download_kernel=" \ + "tftpboot ${kernel_addr} ${kernel_file};" \ + "tftpboot ${fdt_addr} ${fdtfile};\0" \ + "get_boot_medium=" \ + "setenv boot_medium nor;" \ + "setexpr.l _src_sbmr1 *0x020d8004;" \ + "setexpr _b_medium ${_src_sbmr1} '&' 0x00000040;" \ + "if test ${_b_medium} = 40; then " \ + "setenv boot_medium sdcard;" \ + "fi\0" \ + "kernel_file=uImage\0" \ + "load_kernel=" \ + "load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \ + "load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \ + "boot_sd=" \ + "echo '#######################';" \ + "echo '# Factory SDcard Boot #';" \ + "echo '#######################';" \ + "setenv mmcdev 1;" \ + "setenv mmcfactorydev 0;" \ + "setenv mmcfactorypart 1;" \ + "run factory_flash_img;\0" \ + "boot_nor=" \ + "setenv kernelnor 0x08180000;" \ + "setenv dtbnor 0x09980000;" \ + "setenv bootargs console=${console} quiet " \ + ""MTDPARTS_DEFAULT" " \ + "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \ + "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \ + "bootm ${kernelnor} - ${dtbloadaddr};\0" \ + "boot_recovery=" \ + "echo '#######################';" \ + "echo '# RECOVERY SWU Boot #';" \ + "echo '#######################';" \ + "setenv rootfsloadaddr 0x13000000;" \ + "setenv swukernelnor 0x08980000;" \ + "setenv swurootfsnor 0x09180000;" \ + "setenv swudtbnor 0x099A0000;" \ + "setenv bootargs console=${console} " \ + ""MTDPARTS_DEFAULT" " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}::off root=/dev/ram rw;" \ + "cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \ + "cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \ + "bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \ + "boot_tftp=" \ + "echo '#######################';" \ + "echo '# TFTP Boot #';" \ + "echo '#######################';" \ + "if run download_kernel; then " \ + "setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rootwait;" \ + "bootm ${kernel_addr} - ${fdt_addr};" \ + "fi\0" \ + "bootcmd=" \ + "if test -n ${recovery_status}; then " \ + "run boot_recovery;" \ + "else " \ + "if test ! -n ${boot_medium}; then " \ + "run get_boot_medium;" \ + "if test ${boot_medium} = sdcard; then " \ + "run boot_sd;" \ + "else " \ + "run boot_nor;" \ + "fi;" \ + "else " \ + "if test ${boot_medium} = tftp; then " \ + "run boot_tftp;" \ + "fi;" \ + "fi;" \ + "fi\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "fdt_addr=0x18000000\0" \ + "bootdev=1\0" \ + "bootpart=1\0" \ + "kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \ + "netdev=eth0\0" \ + "load_addr=0x11000000\0" \ + "dtbloadaddr=0x12000000\0" \ + "uboot_file=u-boot.img\0" \ + "SPL_file=SPL\0" \ + "load_uboot=tftp ${load_addr} ${uboot_file}\0" \ + "nor_img_addr=0x11000000\0" \ + "nor_img_file=core-image-lwn-mccmon6.nor\0" \ + "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \ + "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ + "nor_img_size=0x02000000\0" \ + "factory_script_file=factory.scr\0" \ + "factory_load_script=" \ + "if test -e mmc ${mmcdev}:${mmcfactorypart} " \ + "${factory_script_file}; then " \ + "load mmc ${mmcdev}:${mmcfactorypart} " \ + "${loadaddr} ${factory_script_file};" \ + "fi\0" \ + "factory_script=echo Running factory script from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "factory_flash_img="\ + "echo 'Flash mccmon6 with factory images'; " \ + "if run factory_load_script; then " \ + "run factory_script;" \ + "else " \ + "echo No factory script: ${factory_script_file} found on " \ + "device ${mmcdev};" \ + "run factory_nor_img;" \ + "run factory_eMMC_img;" \ + "fi\0" \ + "factory_eMMC_img="\ + "echo 'Update mccmon6 eMMC image'; " \ + "if load mmc ${mmcdev}:${mmcfactorypart} " \ + "${loadaddr} ${emmc_img_file}; then " \ + "setexpr fw_sz ${filesize} / 0x200;" \ + "setexpr fw_sz ${fw_sz} + 1;" \ + "mmc dev ${mmcfactorydev};" \ + "mmc write ${loadaddr} 0x0 ${fw_sz};" \ + "fi\0" \ + "factory_nor_img="\ + "echo 'Update mccmon6 NOR image'; " \ + "if load mmc ${mmcdev}:${mmcfactorypart} " \ + "${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "nor_update=" \ + "protect off ${nor_bank_start} +${nor_img_size};" \ + "erase ${nor_bank_start} +${nor_img_size};" \ + "setexpr nor_img_size ${nor_img_size} / 4; " \ + "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \ + "tftp_nor_uboot="\ + "echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \ + "setenv nor_img_file u-boot.img; " \ + "setenv nor_img_size 0x80000; " \ + "setenv nor_bank_start 0x08080000; " \ + "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "tftp_nor_uImg="\ + "echo 'Update mccmon6 NOR uImage via TFTP'; " \ + "setenv nor_img_file uImage; " \ + "setenv nor_img_size 0x500000; " \ + "setenv nor_bank_start 0x08180000; " \ + "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "tftp_nor_img="\ + "echo 'Update mccmon6 NOR image via TFTP'; " \ + "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "tftp_nor_SPL="\ + "if tftp ${load_addr} SPL_padded; then " \ + "erase 0x08000000 +0x20000;" \ + "cp.b ${load_addr} 0x08000000 0x20000;" \ + "fi;\0" \ + "tftp_sd_SPL="\ + "if mmc dev 1; then " \ + "if tftp ${load_addr} ${SPL_file}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${load_addr} 0x2 ${fw_sz};" \ + "fi;" \ + "fi;\0" \ + "tftp_sd_uboot="\ + "if mmc dev 1; then " \ + "if run load_uboot; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${load_addr} 0x8A ${fw_sz};" \ + "fi;" \ + "fi;\0" + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_SIZE (SZ_128K) + +/* Envs are stored in NOR flash */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (SZ_128K) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x60000) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#endif /* __CONFIG_H * */ -- 2.1.4

2 1

[U-Boot] [PATCH 00/12] sunxi: Allwinner H5 and OrangePi PC2 support
by Andre Przywara 23 Jan '17

23 Jan '17

This series introduces support for the Allwinner H5 SoC with four Cortex-A53 cores. The SoC's peripherals are very similar to the H3, although the cores and the BROM/SRAM layout resembles the A64. The first 6 patches contain some fixes and refactoring, to make code sharing between the three mentioned SoCs easier. Patch 07/12 adds support for the H5 DRAM controller, by extending the already existing combined H3/A64 DRAM code. Patch 08/12 renames the existing CONFIG_MACH_SUN8I_H3 config symbol to let it be used by all peripheral code that can be shared between the H3 and H5. Patch 10/12 introduces the H5 SoC config option into Kconfig, which defines this shared symbol as well. Patch 11/12 adds an easy device tree, which actually uses the H3 .dtsi and overwrites nodes which are different. This is good enough for U-Boot, the DT will be changed anyway once we get the DT merged into the Linux kernel. The final patch then adds the defconfig for the OrangePi PC2 board. Since this board comes with soldered SPI flash, we enable support for it in the SPL. This has been tested by writing the SPI flash with some special sunxi-fel version. The BROM loaded and executed the SPL, which in turn loaded and executed U-Boot proper. Both parts are 64-bit only for now. Ethernet support is enabled, but fails at the moment since the EMAC driver does not support setting a GPIO to enable the external Gigabit PHY. This should be a problem for H3 boards with Gigabit as well. At the moment this build suffers from the same problem as the A64: the ATF is missing, so Linux won't boot easily. However I finally managed to clean up the FIT extension series, which solves this problem in a quite elegant way. I will post this series after getting some sleep ;-) This series is on top of sunxi/next, which has three yet unmerged (and unrelated) patches compared to HEAD. So it should apply to both branches. Some of these patches will probably conflict with ongoing work from Icenowy, I am happy to rebase on any branch someone points me to. Please have a look and let me know your opinion! Cheers, Andre. Andre Przywara (12): sunxi: fix ACTLR.SMP assembly routine sunxi: simplify ACTLR.SMP bit set #ifdef sunxi: configs: merge sun9i and sun50i SPL memory definitions sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAM sunxi: provide ARMv8 mem_map for every ARM64 board SPI: SPL: sunxi: fix 64-bit build sunxi: DRAM: add Allwinner H5 support sunxi: prepare for sharing MACH_SUN8I_H3 config symbol sunxi: H5: add COUNTER_FREQUENCY sunxi: introduce Allwinner H5 config option sunxi: dts: add basic OrangePi PC 2 device tree file sunxi: configs: add basic OrangePi PC 2 defconfig arch/arm/dts/Makefile | 2 + arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 147 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 +- arch/arm/include/asm/arch-sunxi/cpu.h | 1 + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 4 +- arch/arm/include/asm/arch-sunxi/dram.h | 2 +- arch/arm/include/asm/arch-sunxi/spl.h | 2 +- arch/arm/mach-sunxi/Makefile | 2 +- arch/arm/mach-sunxi/board.c | 21 ++-- arch/arm/mach-sunxi/clock_sun6i.c | 6 +- arch/arm/mach-sunxi/cpu_info.c | 2 + arch/arm/mach-sunxi/dram_sun8i_h3.c | 97 ++++++++++++++--- arch/arm/mach-sunxi/usb_phy.c | 4 +- board/sunxi/Kconfig | 36 ++++++- board/sunxi/MAINTAINERS | 5 + configs/orangepi_pc2_defconfig | 16 +++ drivers/mtd/spi/Kconfig | 2 +- drivers/mtd/spi/sunxi_spi_spl.c | 16 +-- drivers/net/sun8i_emac.c | 2 +- drivers/power/Kconfig | 4 +- drivers/usb/host/ehci-sunxi.c | 2 +- include/configs/sun8i.h | 2 + include/configs/sunxi-common.h | 22 ++-- 23 files changed, 330 insertions(+), 71 deletions(-) create mode 100644 arch/arm/dts/sun50i-h5-orangepi-pc2.dts create mode 100644 configs/orangepi_pc2_defconfig -- 2.8.2

7 31

[U-Boot] [PATCH v3 0/7] arm: socfpga: update socfpga environments
by Dalon Westergreen 23 Jan '17

23 Jan '17

These patches update the boot and os partition numbers in the default uboot environment for a number of socfpga boards. Per request, common environment configurations have been moved to a shared header. Changes in v3: - Corrected error in common default environment Thanks, Dalon

3 10

[U-Boot] [PATCH 3/9 v2] mmc: Add Marvell Xenon SDHCI controller driver
by Stefan Roese 23 Jan '17

23 Jan '17

This driver implementes platform specific code for the Xenon SDHCI controller which is integrated in the Marvell MVEBU Armada 37xx and Armada 7k / 8K SoCs. History: This driver is ported from the Marvell U-Boot version 2015.01 which is written by Victor Gu <xigu(a)marvell.com> with minor changes ported from the Linux driver which is written by Ziji Hu <huziji(a)marvell.com>. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- v2: - Renamed MMC_XENON_SDHCI to MMC_SDHCI_XENON as requested by Masahiro for the new consistant MMC naming drivers/mmc/Kconfig | 11 + drivers/mmc/Makefile | 1 + drivers/mmc/xenon_sdhci.c | 589 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 601 insertions(+) create mode 100644 drivers/mmc/xenon_sdhci.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 9ed8da39ef..147e52d332 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -287,6 +287,17 @@ config MMC_SDHCI_SPEAR If unsure, say N. +config MMC_SDHCI_XENON + bool "SDHCI support for the Xenon SDHCI controller" + depends on MMC_SDHCI && DM_MMC && OF_CONTROL + help + Support for Xenon SDHCI host controller on Marvell Armada 3700 + 7k/8k ARM SoCs platforms + + If you have a controller with this interface, say Y here. + + If unsure, say N. + config MMC_SDHCI_TEGRA bool "SDHCI platform support for the Tegra SD/MMC Controller" depends on TEGRA diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 4dca09c955..6af7f79ff8 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o +obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c new file mode 100644 index 0000000000..f36b482288 --- /dev/null +++ b/drivers/mmc/xenon_sdhci.c @@ -0,0 +1,589 @@ +/* + * Driver for Marvell SOC Platform Group Xenon SDHC as a platform device + * + * Copyright (C) 2016 Marvell, All Rights Reserved. + * + * Author: Victor Gu <xigu(a)marvell.com> + * Date: 2016-8-24 + * + * Included parts of the Linux driver version which was written by: + * Hu Ziji <huziji(a)marvell.com> + * + * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01: + * Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> +#include <sdhci.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Register Offset of SD Host Controller SOCP self-defined register */ +#define SDHC_SYS_CFG_INFO 0x0104 +#define SLOT_TYPE_SDIO_SHIFT 24 +#define SLOT_TYPE_EMMC_MASK 0xFF +#define SLOT_TYPE_EMMC_SHIFT 16 +#define SLOT_TYPE_SD_SDIO_MMC_MASK 0xFF +#define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8 +#define NR_SUPPORTED_SLOT_MASK 0x7 + +#define SDHC_SYS_OP_CTRL 0x0108 +#define AUTO_CLKGATE_DISABLE_MASK BIT(20) +#define SDCLK_IDLEOFF_ENABLE_SHIFT 8 +#define SLOT_ENABLE_SHIFT 0 + +#define SDHC_SYS_EXT_OP_CTRL 0x010C +#define MASK_CMD_CONFLICT_ERROR BIT(8) + +#define SDHC_SLOT_OP_STATUS_CTRL 0x0128 +#define DELAY_90_DEGREE_MASK_EMMC5 BIT(7) +#define DELAY_90_DEGREE_SHIFT_EMMC5 7 +#define EMMC_5_0_PHY_FIXED_DELAY_MASK 0x7F +#define EMMC_PHY_FIXED_DELAY_MASK 0xFF +#define EMMC_PHY_FIXED_DELAY_WINDOW_MIN (EMMC_PHY_FIXED_DELAY_MASK >> 3) +#define SDH_PHY_FIXED_DELAY_MASK 0x1FF +#define SDH_PHY_FIXED_DELAY_WINDOW_MIN (SDH_PHY_FIXED_DELAY_MASK >> 4) + +#define TUN_CONSECUTIVE_TIMES_SHIFT 16 +#define TUN_CONSECUTIVE_TIMES_MASK 0x7 +#define TUN_CONSECUTIVE_TIMES 0x4 +#define TUNING_STEP_SHIFT 12 +#define TUNING_STEP_MASK 0xF +#define TUNING_STEP_DIVIDER BIT(6) + +#define FORCE_SEL_INVERSE_CLK_SHIFT 11 + +#define SDHC_SLOT_FIFO_CTRL 0x012c + +#define SDHC_SLOT_EMMC_CTRL 0x0130 +#define ENABLE_DATA_STROBE BIT(24) +#define SET_EMMC_RSTN BIT(16) +#define DISABLE_RD_DATA_CRC BIT(14) +#define DISABLE_CRC_STAT_TOKEN BIT(13) +#define EMMC_VCCQ_MASK 0x3 +#define EMMC_VCCQ_1_8V 0x1 +#define EMMC_VCCQ_3_3V 0x3 + +#define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144 +/* retuning compatible */ +#define RETUNING_COMPATIBLE 0x1 + +#define SDHC_SLOT_EXT_PRESENT_STATE 0x014C +#define LOCK_STATE 0x1 + +#define SDHC_SLOT_DLL_CUR_DLY_VAL 0x0150 + +/* Tuning Parameter */ +#define TMR_RETUN_NO_PRESENT 0xf +#define XENON_MAX_TUN_COUNT 0xb +#define DEF_TUNING_COUNT 0x9 + +#define MMC_TIMING_FAKE 0xFF + +#define DEFAULT_SDCLK_FREQ 400000 +#define LOWEST_SDCLK_FREQ 100000 + +/* Xenon specific Mode Select value */ +#define XENON_SDHCI_CTRL_HS200 0x5 +#define XENON_SDHCI_CTRL_HS400 0x6 + +#define EMMC_PHY_REG_BASE 0x170 +#define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE +#define OUTPUT_QSN_PHASE_SELECT (1 << 17) +#define SAMPL_INV_QSP_PHASE_SELECT (1 << 18) +#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 +#define EMMC_PHY_SLOW_MODE (1 << 29) +#define PHY_INITIALIZAION (1 << 31) +#define WAIT_CYCLE_BEFORE_USING_MASK 0xf +#define WAIT_CYCLE_BEFORE_USING_SHIFT 12 +#define FC_SYNC_EN_DURATION_MASK 0xf +#define FC_SYNC_EN_DURATION_SHIFT 8 +#define FC_SYNC_RST_EN_DURATION_MASK 0xf +#define FC_SYNC_RST_EN_DURATION_SHIFT 4 +#define FC_SYNC_RST_DURATION_MASK 0xf +#define FC_SYNC_RST_DURATION_SHIFT 0 + +#define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4) +#define DQ_ASYNC_MODE (1 << 4) +#define DQ_DDR_MODE_SHIFT 8 +#define DQ_DDR_MODE_MASK 0xff +#define CMD_DDR_MODE (1 << 16) + +#define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8) +#define REC_EN_SHIFT 24 +#define REC_EN_MASK 0xf +#define FC_DQ_RECEN (1 << 24) +#define FC_CMD_RECEN (1 << 25) +#define FC_QSP_RECEN (1 << 26) +#define FC_QSN_RECEN (1 << 27) +#define OEN_QSN (1 << 28) +#define AUTO_RECEN_CTRL (1 << 30) + +#define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc) +#define EMMC5_1_FC_QSP_PD BIT(9) +#define EMMC5_1_FC_QSP_PU BIT(25) +#define EMMC5_1_FC_CMD_PD BIT(8) +#define EMMC5_1_FC_CMD_PU BIT(24) +#define EMMC5_1_FC_DQ_PD 0xff +#define EMMC5_1_FC_DQ_PU (0xff << 16) + +#define EMMC_PHY_PAD_CONTROL2 (EMMC_PHY_REG_BASE + 0x10) +#define EMMC_PHY_DLL_CONTROL (EMMC_PHY_REG_BASE + 0x14) +#define DLL_DELAY_TEST_LOWER_SHIFT 8 +#define DLL_DELAY_TEST_LOWER_MASK 0xff +#define DLL_BYPASS_EN 0x1 + +#define EMMC_LOGIC_TIMING_ADJUST (EMMC_PHY_REG_BASE + 0x18) +#define EMMC_LOGIC_TIMING_ADJUST_LOW (EMMC_PHY_REG_BASE + 0x1c) + +/* Recommend by HW team */ +#define LOGIC_TIMING_VALUE 0x5a54 + +#define SDHCI_RETUNE_EVT_INTSIG 0x00001000 + +/* Hyperion only have one slot 0 */ +#define XENON_MMC_SLOT_ID_HYPERION 0 + +#define MMC_TIMING_LEGACY 0 +#define MMC_TIMING_MMC_HS 1 +#define MMC_TIMING_SD_HS 2 +#define MMC_TIMING_UHS_SDR12 3 +#define MMC_TIMING_UHS_SDR25 4 +#define MMC_TIMING_UHS_SDR50 5 +#define MMC_TIMING_UHS_SDR104 6 +#define MMC_TIMING_UHS_DDR50 7 +#define MMC_TIMING_MMC_DDR52 8 +#define MMC_TIMING_MMC_HS200 9 +#define MMC_TIMING_MMC_HS400 10 + +#define XENON_MMC_MAX_CLK 400000000 + +enum soc_pad_ctrl_type { + SOC_PAD_SD, + SOC_PAD_FIXED_1_8V, +}; + +struct xenon_sdhci_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct xenon_sdhci_priv { + struct sdhci_host host; + + u8 timing; + + unsigned int clock; + + void *pad_ctrl_reg; + int pad_type; +}; + +static int xenon_mmc_phy_init(struct sdhci_host *host) +{ + struct xenon_sdhci_priv *priv = host->mmc->priv; + u32 clock = priv->clock; + u32 wait; + u32 time; + u32 var; + + /* Enable QSP PHASE SELECT */ + var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); + var |= SAMPL_INV_QSP_PHASE_SELECT; + if ((priv->timing == MMC_TIMING_UHS_SDR50) || + (priv->timing == MMC_TIMING_UHS_SDR25) || + (priv->timing == MMC_TIMING_UHS_SDR12) || + (priv->timing == MMC_TIMING_SD_HS) || + (priv->timing == MMC_TIMING_LEGACY)) + var |= EMMC_PHY_SLOW_MODE; + sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); + + /* Poll for host MMC PHY clock init to be stable */ + /* Wait up to 10ms */ + time = 100; + while (time--) { + var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); + if (var & SDHCI_CLOCK_INT_STABLE) + break; + + udelay(100); + } + + if (time <= 0) { + error("Failed to enable MMC internal clock in time\n"); + return -ETIMEDOUT; + } + + /* Init PHY */ + var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); + var |= PHY_INITIALIZAION; + sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); + + /* Add duration of FC_SYNC_RST */ + wait = (var >> FC_SYNC_RST_DURATION_SHIFT) & FC_SYNC_RST_DURATION_MASK; + /* Add interval between FC_SYNC_EN and FC_SYNC_RST */ + wait += (var >> FC_SYNC_RST_EN_DURATION_SHIFT) & + FC_SYNC_RST_EN_DURATION_MASK; + /* Add duration of asserting FC_SYNC_EN */ + wait += (var >> FC_SYNC_EN_DURATION_SHIFT) & FC_SYNC_EN_DURATION_MASK; + /* Add duration of waiting for PHY */ + wait += (var >> WAIT_CYCLE_BEFORE_USING_SHIFT) & + WAIT_CYCLE_BEFORE_USING_MASK; + /* + * According to Moyang, 4 addtional bus clock and 4 AXI bus clock + * are required + */ + /* left shift 20 bits */ + wait += 8; + wait <<= 20; + + if (clock == 0) { + /* Use the possibly slowest bus frequency value */ + clock = 100000; + } + + /* Get the wait time in unit of ms */ + wait = wait / clock; + wait++; + + /* Poll for host eMMC PHY init to complete */ + /* Wait up to 10ms */ + time = 100; + while (time--) { + var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); + var &= PHY_INITIALIZAION; + if (!var) + break; + + /* wait for host eMMC PHY init to complete */ + udelay(100); + } + + if (time <= 0) { + error("Failed to init MMC PHY in time\n"); + return -ETIMEDOUT; + } + + return 0; +} + +#define ARMADA_3700_SOC_PAD_1_8V 0x1 +#define ARMADA_3700_SOC_PAD_3_3V 0x0 + +static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host) +{ + struct xenon_sdhci_priv *priv = host->mmc->priv; + + if (priv->pad_type == SOC_PAD_FIXED_1_8V) + writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg); + else if (priv->pad_type == SOC_PAD_SD) + writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg); +} + +static void xenon_mmc_phy_set(struct sdhci_host *host) +{ + struct xenon_sdhci_priv *priv = host->mmc->priv; + u32 var; + + /* Setup pad, set bit[30], bit[28] and bits[26:24] */ + var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL); + var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN | + FC_CMD_RECEN | FC_DQ_RECEN; + sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL); + + /* Set CMD and DQ Pull Up */ + var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1); + var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU); + var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD); + sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1); + + /* + * If timing belongs to high speed, set bit[17] of + * EMMC_PHY_TIMING_ADJUST register + */ + if ((priv->timing == MMC_TIMING_MMC_HS400) || + (priv->timing == MMC_TIMING_MMC_HS200) || + (priv->timing == MMC_TIMING_UHS_SDR50) || + (priv->timing == MMC_TIMING_UHS_SDR104) || + (priv->timing == MMC_TIMING_UHS_DDR50) || + (priv->timing == MMC_TIMING_UHS_SDR25) || + (priv->timing == MMC_TIMING_MMC_DDR52)) { + var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); + var |= OUTPUT_QSN_PHASE_SELECT; + sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); + } + + /* + * When setting EMMC_PHY_FUNC_CONTROL register, + * SD clock should be disabled + */ + var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); + var &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, var, SDHCI_CLOCK_CONTROL); + + var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL); + if (host->mmc->ddr_mode) { + var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE; + } else { + var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | + CMD_DDR_MODE); + } + sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL); + + /* Enable bus clock */ + var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); + var |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, var, SDHCI_CLOCK_CONTROL); + + xenon_mmc_phy_init(host); +} + +/* Enable/Disable the Auto Clock Gating function of this slot */ +static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable) +{ + u32 var; + + var = sdhci_readl(host, SDHC_SYS_OP_CTRL); + if (enable) + var &= ~AUTO_CLKGATE_DISABLE_MASK; + else + var |= AUTO_CLKGATE_DISABLE_MASK; + + sdhci_writel(host, var, SDHC_SYS_OP_CTRL); +} + +/* Enable specific slot */ +static void xenon_mmc_set_slot(struct sdhci_host *host, u8 slot, bool enable) +{ + u32 var; + + var = sdhci_readl(host, SDHC_SYS_OP_CTRL); + if (enable) + var |= (0x1 << slot) << SLOT_ENABLE_SHIFT; + else + var &= ~((0x1 << slot) << SLOT_ENABLE_SHIFT); + sdhci_writel(host, var, SDHC_SYS_OP_CTRL); +} + +/* Enable Parallel Transfer Mode */ +static void xenon_mmc_set_parallel_tran(struct sdhci_host *host, u8 slot, + bool enable) +{ + u32 var; + + var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL); + if (enable) + var |= (0x1 << slot); + else + var &= ~(0x1 << slot); + sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL); +} + +static void xenon_mmc_set_tuning(struct sdhci_host *host, u8 slot, bool enable) +{ + u32 var; + + /* Set the Re-Tuning Request functionality */ + var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL); + if (enable) + var |= RETUNING_COMPATIBLE; + else + var &= ~RETUNING_COMPATIBLE; + sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL); + + /* Set the Re-tuning Event Signal Enable */ + var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); + if (enable) + var |= SDHCI_RETUNE_EVT_INTSIG; + else + var &= ~SDHCI_RETUNE_EVT_INTSIG; + sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE); +} + +/* Mask command conflict error */ +static void xenon_mask_cmd_conflict_err(struct sdhci_host *host) +{ + u32 reg; + + reg = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL); + reg |= MASK_CMD_CONFLICT_ERROR; + sdhci_writel(host, reg, SDHC_SYS_EXT_OP_CTRL); +} + +/* Platform specific function for post set_ios configuration */ +static void xenon_sdhci_set_ios_post(struct sdhci_host *host) +{ + struct xenon_sdhci_priv *priv = host->mmc->priv; + uint speed = host->mmc->tran_speed; + int pwr_18v = 0; + + if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) == + SDHCI_POWER_180) + pwr_18v = 1; + + /* Set timing variable according to the configured speed */ + if (IS_SD(host->mmc)) { + /* SD/SDIO */ + if (pwr_18v) { + if (host->mmc->ddr_mode) + priv->timing = MMC_TIMING_UHS_DDR50; + else if (speed <= 25000000) + priv->timing = MMC_TIMING_UHS_SDR25; + else + priv->timing = MMC_TIMING_UHS_SDR50; + } else { + if (speed <= 25000000) + priv->timing = MMC_TIMING_LEGACY; + else + priv->timing = MMC_TIMING_SD_HS; + } + } else { + /* eMMC */ + if (host->mmc->ddr_mode) + priv->timing = MMC_TIMING_MMC_DDR52; + else if (speed <= 26000000) + priv->timing = MMC_TIMING_LEGACY; + else + priv->timing = MMC_TIMING_MMC_HS; + } + + /* Re-init the PHY */ + xenon_mmc_phy_set(host); +} + +/* Install a driver specific handler for post set_ios configuration */ +static const struct sdhci_ops xenon_sdhci_ops = { + .set_ios_post = xenon_sdhci_set_ios_post +}; + +static int xenon_sdhci_probe(struct udevice *dev) +{ + struct xenon_sdhci_plat *plat = dev_get_platdata(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct xenon_sdhci_priv *priv = dev_get_priv(dev); + struct sdhci_host *host = dev_get_priv(dev); + int ret; + + host->mmc = &plat->mmc; + host->mmc->priv = host; + host->mmc->dev = dev; + upriv->mmc = host->mmc; + + /* Set quirks */ + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR; + + /* Set default timing */ + priv->timing = MMC_TIMING_LEGACY; + + /* Disable auto clock gating during init */ + xenon_mmc_set_acg(host, false); + + /* Enable slot */ + xenon_mmc_set_slot(host, XENON_MMC_SLOT_ID_HYPERION, true); + + /* + * Set default power on SoC PHY PAD register (currently only + * available on the Armada 3700) + */ + if (priv->pad_ctrl_reg) + armada_3700_soc_pad_voltage_set(host); + + ret = sdhci_setup_cfg(&plat->cfg, host, XENON_MMC_MAX_CLK, 0); + if (ret) + return ret; + + plat->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | + MMC_MODE_DDR_52MHz; + + switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) { + case 8: + plat->cfg.host_caps |= MMC_MODE_8BIT; + break; + case 4: + plat->cfg.host_caps |= MMC_MODE_4BIT; + break; + case 1: + break; + default: + printf("Invalid \"bus-width\" value\n"); + return -EINVAL; + } + + host->ops = &xenon_sdhci_ops; + + ret = sdhci_probe(dev); + if (ret) + return ret; + + /* Enable parallel transfer */ + xenon_mmc_set_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION, true); + + /* Disable tuning functionality of this slot */ + xenon_mmc_set_tuning(host, XENON_MMC_SLOT_ID_HYPERION, false); + + /* Enable auto clock gating after init */ + xenon_mmc_set_acg(host, true); + + xenon_mask_cmd_conflict_err(host); + + return ret; +} + +static int xenon_sdhci_ofdata_to_platdata(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + struct xenon_sdhci_priv *priv = dev_get_priv(dev); + const char *name; + + host->name = dev->name; + host->ioaddr = (void *)dev_get_addr(dev); + + if (of_device_is_compatible(dev, "marvell,armada-3700-sdhci")) + priv->pad_ctrl_reg = (void *)dev_get_addr_index(dev, 1); + + name = fdt_getprop(gd->fdt_blob, dev->of_offset, "marvell,pad-type", + NULL); + if (name) { + if (0 == strcmp(name, "sd")) { + priv->pad_type = SOC_PAD_SD; + } else if (0 == strcmp(name, "fixed-1-8v")) { + priv->pad_type = SOC_PAD_FIXED_1_8V; + } else { + printf("Unsupported SOC PHY PAD ctrl type %s\n", name); + return -EINVAL; + } + } + + return 0; +} + +static int xenon_sdhci_bind(struct udevice *dev) +{ + struct xenon_sdhci_plat *plat = dev_get_platdata(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static const struct udevice_id xenon_sdhci_ids[] = { + { .compatible = "marvell,armada-8k-sdhci",}, + { .compatible = "marvell,armada-3700-sdhci",}, + { } +}; + +U_BOOT_DRIVER(xenon_sdhci_drv) = { + .name = "xenon_sdhci", + .id = UCLASS_MMC, + .of_match = xenon_sdhci_ids, + .ofdata_to_platdata = xenon_sdhci_ofdata_to_platdata, + .ops = &sdhci_ops, + .bind = xenon_sdhci_bind, + .probe = xenon_sdhci_probe, + .priv_auto_alloc_size = sizeof(struct xenon_sdhci_priv), + .platdata_auto_alloc_size = sizeof(struct xenon_sdhci_plat), +}; -- 2.11.0

2 2