January 2017 - U-Boot

[U-Boot] [PATCH v2] powerpc/t2080: CPU erratum A-007907
by Darwin Dingel 24 Jan '17

24 Jan '17

Core hang occurs when using L1 stashes. Workaround is to disable L1 stashes so software uses L2 cache for stashes instead. Reviewed-by: Chris Packham <chris.packham(a)alliedtelesis.co.nz> Signed-off-by: Darwin Dingel <darwin.dingel(a)alliedtelesis.co.nz> Cc: York Sun <york.sun(a)nxp.com> --- Changes for v2: - Enabled for T4240 and B4860 arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +++- arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++++++ arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ arch/powerpc/include/asm/processor.h | 1 + 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3b06ae4..197eb2f 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -329,7 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 puts("Work-around for Erratum A009663 enabled\n"); #endif - +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 + puts("Work-around for Erratum A007907 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 53b3729..0e744f0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -775,6 +775,13 @@ int cpu_init_r(void) sync(); } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); + sync(); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 /* * A-005812 workaround sets bit 32 of SPR 976 for SoCs running diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6d845e8..c2bf44b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -642,6 +642,7 @@ #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A007907 #else #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -748,6 +749,7 @@ #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_SRIO_LIODN +#define CONFIG_SYS_FSL_ERRATUM_A007907 #else #define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_DSP_CPUS 2 @@ -910,6 +912,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A007907 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define CONFIG_SYS_FSL_SFP_VER_3_0 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fdfca90..6f9b297 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -501,6 +501,7 @@ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ #define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */ +#define L1CSR2_DCSTASHID 0x000003ff /* Data Cache Stash ID */ #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ -- 2.10.1

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[U-Boot] [PATCH v2 0/2] ARM: am335x: Support chiliSOM and chiliBoard
by Marcin Niestroj 24 Jan '17

24 Jan '17

These patches add support for chiliSOM (http://grinn-global.com/chilisom/), and chiliBoard (which uses chiliSOM as it's base). chiliSOM consists of processor (TI AM335x), RAM memory (up to 512M DDR3) and flash (NAND). The idea is that every board vendor can use chiliSOM as it's base for designed board. Hence, we need a way to reuse common code between those board. chiliBoard is a development kit (and reference platform for chiliSOM), that mainly shows possibilities and use cases of chiliSOM. This is a second approach and we are moving chiliSOM sources to arch/arm/mach-omap2/am33xx/ directory. The same will happen with liteSOM support (which is already merged) after successful chiliSOM code review. Patches were developed and tested on 2017.01. Changes v1 -> v2: * chiliSOM was moved from arch/arm/mach-chilisom/chilisom.c to arch/arm/mach-omap2/chilisom.c (suggested by Tom) * CONFIG_CHILISOM -> CONFIG_AM33XX_CHILISOM (suggested by Tom) * converted include/configs/chiliboard.h header to SPDX license identifier (suggested by Tom) * removed USB gadget, CMD_DFU options from chiliboard_defconfig Marcin Niestroj (2): ARM: am335x: Add support for chiliSOM board/chiliboard: Add support for chiliBoard arch/arm/Kconfig | 1 + arch/arm/include/asm/arch-am33xx/chilisom.h | 15 ++ arch/arm/mach-omap2/am33xx/Kconfig | 10 ++ arch/arm/mach-omap2/am33xx/Makefile | 2 + arch/arm/mach-omap2/am33xx/chilisom.c | 185 +++++++++++++++++++ board/grinn/chiliboard/Kconfig | 15 ++ board/grinn/chiliboard/MAINTAINERS | 6 + board/grinn/chiliboard/Makefile | 6 + board/grinn/chiliboard/README | 31 ++++ board/grinn/chiliboard/board.c | 264 ++++++++++++++++++++++++++++ configs/chiliboard_defconfig | 48 +++++ include/configs/chiliboard.h | 220 +++++++++++++++++++++++ 12 files changed, 803 insertions(+) create mode 100644 arch/arm/include/asm/arch-am33xx/chilisom.h create mode 100644 arch/arm/mach-omap2/am33xx/chilisom.c create mode 100644 board/grinn/chiliboard/Kconfig create mode 100644 board/grinn/chiliboard/MAINTAINERS create mode 100644 board/grinn/chiliboard/Makefile create mode 100644 board/grinn/chiliboard/README create mode 100644 board/grinn/chiliboard/board.c create mode 100644 configs/chiliboard_defconfig create mode 100644 include/configs/chiliboard.h -- 2.11.0

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Re: [U-Boot] [PATCH] net: phy: dp83867: add support for MAC impedance configuration
by Grygorii Strashko 24 Jan '17

24 Jan '17

Sry CC:u-boot@lists.denx.de On 01/19/2017 04:30 PM, Grygorii Strashko wrote: > From: Mugunthan V N <mugunthanvnm(a)ti.com> > > Add support for programmable MAC impedance configuration and > fix typo in DT impedance parameters names. > > Signed-off-by: Mugunthan V N <mugunthanvnm(a)ti.com> > Signed-off-by: Grygorii Strashko <grygorii.strashko(a)ti.com> > --- > arch/arm/dts/dra72-evm-revc.dts | 4 ++-- > drivers/net/phy/ti.c | 31 +++++++++++++++++++++++++++++++ > 2 files changed, 33 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts > index 5a1bb34..bc814f1 100644 > --- a/arch/arm/dts/dra72-evm-revc.dts > +++ b/arch/arm/dts/dra72-evm-revc.dts > @@ -67,7 +67,7 @@ > ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; > ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; > ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; > - ti,min-output-imepdance; > + ti,min-output-impedance; > }; > > dp83867_1: ethernet-phy@3 { > @@ -75,6 +75,6 @@ > ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; > ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; > ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; > - ti,min-output-imepdance; > + ti,min-output-impedance; > }; > }; > diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c > index c55dd97..21b181a 100644 > --- a/drivers/net/phy/ti.c > +++ b/drivers/net/phy/ti.c > @@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; > /* Extended Registers */ > #define DP83867_RGMIICTL 0x0032 > #define DP83867_RGMIIDCTL 0x0086 > +#define DP83867_IO_MUX_CFG 0x0170 > > #define DP83867_SW_RESET BIT(15) > #define DP83867_SW_RESTART BIT(14) > @@ -84,10 +85,17 @@ DECLARE_GLOBAL_DATA_PTR; > #define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS > #define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB > > +/* IO_MUX_CFG bits */ > +#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f > + > +#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 > +#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f > + > struct dp83867_private { > int rx_id_delay; > int tx_id_delay; > int fifo_depth; > + int io_impedance; > }; > > /** > @@ -166,6 +174,15 @@ static int dp83867_of_init(struct phy_device *phydev) > { > struct dp83867_private *dp83867 = phydev->priv; > struct udevice *dev = phydev->dev; > + int node = dev->of_offset; > + const void *fdt = gd->fdt_blob; > + > + if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance")) > + dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; > + else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance")) > + dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; > + else > + dp83867->io_impedance = -EINVAL; > > dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, > "ti,rx-internal-delay", -1); > @@ -186,6 +203,7 @@ static int dp83867_of_init(struct phy_device *phydev) > dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY; > dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY; > dp83867->fifo_depth = DEFAULT_FIFO_DEPTH; > + dp83867->io_impedance = -EINVAL; > > return 0; > } > @@ -269,6 +287,19 @@ static int dp83867_config(struct phy_device *phydev) > > phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, > DP83867_DEVADDR, phydev->addr, delay); > + > + if (dp83867->io_impedance >= 0) { > + val = phy_read_mmd_indirect(phydev, > + DP83867_IO_MUX_CFG, > + DP83867_DEVADDR, > + phydev->addr); > + val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL; > + val |= dp83867->io_impedance & > + DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL; > + phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG, > + DP83867_DEVADDR, phydev->addr, > + val); > + } > } > > genphy_config_aneg(phydev); > -- regards, -grygorii

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[U-Boot] [PATCH 0/3] ARM: am335x: Support chiliSOM and chiliBoard
by Marcin Niestroj 24 Jan '17

24 Jan '17

These patches add support for chiliSOM (http://grinn-global.com/chilisom/), and chiliBoard (which uses chiliSOM as it's base). chiliSOM consists of processor (TI AM335x), RAM memory (up to 512M DDR3) and flash (NAND). The idea is that every board vendor can use chiliSOM as it's base for designed board. Hence, we need a way to reuse common code between those board. chiliBoard is a development kit (and reference platform for chiliSOM), that mainly shows possibilities and use cases of chiliSOM. Patches were developed and tested on 2017.01. Marcin Niestroj (3): ARM: Makefile: Fix config.mk inclusion for multiple mach-* dirs ARM: am335x: Add support for chiliSOM board/chiliboard: Add support for chiliBoard arch/arm/Kconfig | 3 + arch/arm/Makefile | 3 +- arch/arm/mach-chilisom/Kconfig | 4 + arch/arm/mach-chilisom/Makefile | 6 + arch/arm/mach-chilisom/chilisom.c | 185 +++++++++++++++++ arch/arm/mach-chilisom/include/mach/chilisom.h | 15 ++ arch/arm/mach-omap2/am33xx/Kconfig | 5 + board/grinn/chiliboard/Kconfig | 15 ++ board/grinn/chiliboard/MAINTAINERS | 6 + board/grinn/chiliboard/Makefile | 6 + board/grinn/chiliboard/README | 31 +++ board/grinn/chiliboard/board.c | 264 +++++++++++++++++++++++++ configs/chiliboard_defconfig | 55 ++++++ include/configs/chiliboard.h | 230 +++++++++++++++++++++ 14 files changed, 827 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-chilisom/Kconfig create mode 100644 arch/arm/mach-chilisom/Makefile create mode 100644 arch/arm/mach-chilisom/chilisom.c create mode 100644 arch/arm/mach-chilisom/include/mach/chilisom.h create mode 100644 board/grinn/chiliboard/Kconfig create mode 100644 board/grinn/chiliboard/MAINTAINERS create mode 100644 board/grinn/chiliboard/Makefile create mode 100644 board/grinn/chiliboard/README create mode 100644 board/grinn/chiliboard/board.c create mode 100644 configs/chiliboard_defconfig create mode 100644 include/configs/chiliboard.h -- 2.11.0

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[U-Boot] [PATCH v3 0/9] imx6ul: Add Engicam Is.IoT MX6UL support
by Jagan Teki 24 Jan '17

24 Jan '17

From: Jagan Teki <jagan(a)amarulasolutions.com> This patch set support Engicam Is.IoT MX6UL board support. Changes for v2: - Skiped eMMC node patch - Rebase to master Changes for v1: - Rebase to master Jagan Teki (9): configs: imx6: Don't define USDHC2_BASE_ADDR arm: imx6ul: Add Engicam Is.IoT MX6UL Starter Kit initial support arm: dts: imx6ul-isiot: Add I2C nodes imx6: isiotmx6ul: Add I2C support arm: dts: imx6ul-isiot: Add FEC node imx6: isiotmx6ul: Add FEC support imx6: isiotmx6ul: Add NAND support imx6: isiotmx6ul: Add nandboot env support imx6ul: isiotmx6ul: Enable I2C support arch/arm/cpu/armv7/mx6/Kconfig | 13 ++ arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6ul-isiot-mmc.dts | 50 ++++++ arch/arm/dts/imx6ul-isiot-nand.dts | 50 ++++++ arch/arm/dts/imx6ul-isiot.dtsi | 142 +++++++++++++++ board/engicam/isiotmx6ul/Kconfig | 12 ++ board/engicam/isiotmx6ul/MAINTAINERS | 7 + board/engicam/isiotmx6ul/Makefile | 6 + board/engicam/isiotmx6ul/README | 28 +++ board/engicam/isiotmx6ul/isiotmx6ul.c | 316 ++++++++++++++++++++++++++++++++++ configs/imx6ul_isiot_mmc_defconfig | 41 +++++ configs/imx6ul_isiot_nand_defconfig | 49 ++++++ include/configs/imx6qdl_icore.h | 2 +- include/configs/imx6ul_geam.h | 2 +- include/configs/imx6ul_isiot.h | 205 ++++++++++++++++++++++ 15 files changed, 924 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/imx6ul-isiot-mmc.dts create mode 100644 arch/arm/dts/imx6ul-isiot-nand.dts create mode 100644 arch/arm/dts/imx6ul-isiot.dtsi create mode 100644 board/engicam/isiotmx6ul/Kconfig create mode 100644 board/engicam/isiotmx6ul/MAINTAINERS create mode 100644 board/engicam/isiotmx6ul/Makefile create mode 100644 board/engicam/isiotmx6ul/README create mode 100644 board/engicam/isiotmx6ul/isiotmx6ul.c create mode 100644 configs/imx6ul_isiot_mmc_defconfig create mode 100644 configs/imx6ul_isiot_nand_defconfig create mode 100644 include/configs/imx6ul_isiot.h -- 1.9.1

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[U-Boot] u-boot.git or u-boot-x86.git for x86_64 u-boots?
by Joakim Tjernlund 24 Jan '17

24 Jan '17

I found two repos w.r.t x86_64 for u-boot, which one should I use? I am ATM only looking at USING the qemu-x86 target for now. BTW, I found tools/binman/binman.py only worked with python 2.7, maybe you can change the shebang to python2.7 as my default python is 3.4 Jocke

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[U-Boot] [PATCH 3/5] arch: arm: update the IFC IP input clock
by Prabhakar Kushwaha 24 Jan '17

24 Jan '17

IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. So update IFC IP clock to be defined as per predefined clock divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Split the patch in 2 patch set Changes for v3: Rebased on top of u-boot commit Changes for v4: Sending as it is Changes for v5: Sending as it is arch/arm/cpu/armv7/ls102xa/clock.c | 9 +-------- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 10 ++-------- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 10 ++-------- 3 files changed, 5 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index 7a337e1..b7d61ad 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -19,10 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#ifdef CONFIG_FSL_IFC - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - u32 ccr; -#endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR); unsigned int cpu; const u8 core_cplx_pll[6] = { @@ -74,10 +70,7 @@ void get_sys_info(struct sys_info *sys_info) } #if defined(CONFIG_FSL_IFC) - ccr = in_be32(&ifc_regs.gregs->ifc_ccr); - ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - - sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus; #endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 3da7037..2d7775e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -22,10 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#ifdef CONFIG_FSL_IFC - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - u32 ccr; -#endif #if (defined(CONFIG_FSL_ESDHC) &&\ defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\ defined(CONFIG_SYS_DPAA_FMAN) @@ -156,10 +152,8 @@ void get_sys_info(struct sys_info *sys_info) #endif #if defined(CONFIG_FSL_IFC) - ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); - ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - - sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus / + CONFIG_SYS_FSL_IFC_CLK_DIV; #endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index f8fefc7..ab46431 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -26,10 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#ifdef CONFIG_FSL_IFC - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - u32 ccr; -#endif struct ccsr_clk_cluster_group __iomem *clk_grp[2] = { (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR), (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR) @@ -128,10 +124,8 @@ void get_sys_info(struct sys_info *sys_info) } #if defined(CONFIG_FSL_IFC) - ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); - ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - - sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus / + CONFIG_SYS_FSL_IFC_CLK_DIV; #endif } -- 2.7.4

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[U-Boot] [PATCH 1/5][v5] arch: powerpc: Move CONFIG_FSL_IFC to Kconfig
by Prabhakar Kushwaha 24 Jan '17

24 Jan '17

Enable IFC from Kconfig. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v5: Added first time arch/powerpc/cpu/mpc85xx/Kconfig | 17 +++++++++++++++++ include/configs/B4860QDS.h | 1 - include/configs/BSC9131RDB.h | 1 - include/configs/BSC9132QDS.h | 1 - include/configs/C29XPCIE.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/T102xQDS.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T1040QDS.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/t4qds.h | 1 - 14 files changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 704f65b..c67b6b0 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -349,6 +349,7 @@ config ARCH_B4420 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_B4860 bool @@ -372,6 +373,7 @@ config ARCH_B4860 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_BSC9131 bool @@ -384,6 +386,7 @@ config ARCH_BSC9131 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select FSL_IFC config ARCH_BSC9132 bool @@ -400,6 +403,7 @@ config ARCH_BSC9132 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_IFC config ARCH_C29X bool @@ -412,6 +416,7 @@ config ARCH_C29X select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_6 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_IFC config ARCH_MPC8536 bool @@ -527,6 +532,7 @@ config ARCH_P1010 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_IFC config ARCH_P1011 bool @@ -769,6 +775,7 @@ config ARCH_T1023 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T1024 bool @@ -785,6 +792,7 @@ config ARCH_T1024 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T1040 bool @@ -802,6 +810,7 @@ config ARCH_T1040 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T1042 bool @@ -819,6 +828,7 @@ config ARCH_T1042 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T2080 bool @@ -838,6 +848,7 @@ config ARCH_T2080 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_T2081 bool @@ -857,6 +868,7 @@ config ARCH_T2081 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_T4160 bool @@ -877,6 +889,7 @@ config ARCH_T4160 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_T4240 bool @@ -898,6 +911,7 @@ config ARCH_T4240 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config BOOKE bool @@ -1224,6 +1238,9 @@ config SYS_PPC64 config SYS_PPC_E500_USE_DEBUG_TLB bool +config FSL_IFC + bool + config SYS_PPC_E500_DEBUG_TLB int "Temporary TLB entry for external debugger" depends on SYS_PPC_E500_USE_DEBUG_TLB diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 3ad9f80..4267d81 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -63,7 +63,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index a6f73f2..1fe22b6 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -46,7 +46,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_TSEC_ENET diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 8aec315..ef84ee7 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -68,7 +68,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 53ee98c..269cd49 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -68,7 +68,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index cd9cd9a..d043888 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -130,7 +130,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index c9a1334..4e46196 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 36eba4e..9b3d298 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8d6d986..e1aceb6 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index d574bbb..7c8ff5e 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -165,7 +165,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 210d8d8..9ec326a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -33,7 +33,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 1941188..b114234 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index e15b0ea..9136bf0 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -73,7 +73,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 0f59eb1..82e4691 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -- 2.7.4

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[U-Boot] [PATCH 0/5] IFC/ELBC: Update IP input clock
by Prabhakar Kushwaha 24 Jan '17

24 Jan '17

IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register used in current implementation governs IP output clock. So update IP clock to be defined as per predefined clock divisor of platform clock Prabhakar Kushwaha (5): arch: powerpc: Move CONFIG_FSL_IFC to Kconfig arch: powerpc: update the IFC IP input clock arch: arm: update the IFC IP input clock arch: powerpc: Move CONFIG_FSL_ELBC to Kconfig arch: powerpc: update the eLBC IP input clock README | 6 ++ arch/arm/cpu/armv7/ls102xa/clock.c | 9 +-- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 10 +-- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 10 +-- arch/powerpc/cpu/mpc85xx/Kconfig | 73 ++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/speed.c | 38 ++--------- arch/powerpc/cpu/mpc86xx/speed.c | 14 +---- include/configs/B4860QDS.h | 1 - include/configs/BSC9131RDB.h | 1 - include/configs/BSC9132QDS.h | 1 - include/configs/C29XPCIE.h | 1 - include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8569MDS.h | 2 - include/configs/MPC8572DS.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/P1022DS.h | 1 - include/configs/P1023RDB.h | 1 - include/configs/P2041RDB.h | 1 - include/configs/T102xQDS.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T1040QDS.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/UCP1020.h | 1 - include/configs/controlcenterd.h | 1 - include/configs/corenet_ds.h | 1 - include/configs/cyrus.h | 1 - include/configs/ids8313.h | 2 - include/configs/km/kmp204x-common.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/p1_twr.h | 1 - include/configs/t4qds.h | 1 - include/configs/ve8313.h | 1 - include/configs/xpedite537x.h | 1 - include/configs/xpedite550x.h | 1 - 41 files changed, 89 insertions(+), 107 deletions(-) -- 2.7.4

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[U-Boot] ext4: crash when writing a file
by Sébastien Szymanski 24 Jan '17

24 Jan '17

Hello, I am working on a i.MX6UL based board with a 4GB eMMC partitioned as following: Device Boot Start End Sectors Size Id Type /dev/sdb1 2048 264191 262144 128M 83 Linux /dev/sdb2 264192 4458495 4194304 2G 83 Linux /dev/sdb3 4458496 7634943 3176448 1.5G 83 Linux On the 2nd partition, I write this ext4 filesystem file generated by Buildroot: Filesystem volume name: "ROOTFS" Last mounted on: <not available> Filesystem UUID: b9833a36-e89d-429a-b120-c3b00bcb7785 Filesystem magic number: 0xEF53 Filesystem revision #: 1 (dynamic) Filesystem features: has_journal dir_index filetype extent sparse_super uninit_bg Filesystem flags: signed_directory_hash Default mount options: (none) Filesystem state: clean Errors behavior: Unknown (continue) Filesystem OS type: Linux Inode count: 3456 Block count: 91756 Reserved block count: 4587 Free blocks: 13458 Free inodes: 488 First block: 1 Block size: 1024 Fragment size: 1024 Blocks per group: 7648 Fragments per group: 7648 Inodes per group: 288 Inode blocks per group: 36 Last mount time: n/a Last write time: Tue Nov 29 09:44:52 2016 Mount count: 0 Maximum mount count: -1 Last checked: Tue Nov 29 09:44:52 2016 Check interval: 0 (<none>) Reserved blocks uid: 0 (user root) Reserved blocks gid: 0 (group root) First inode: 11 Inode size: 128 Journal inode: 8 Default directory hash: half_md4 Directory Hash Seed: a583a07f-6b59-442d-8e08-9be305f78d17 Journal backup: inode blocks This filesystem is written with the following commands: BIOS> setexpr nbblocks ${filesize} / 0x200 BIOS> setexpr nbblocks ${nbblocks} + 1 BIOS> mmc write ${loadaddr} 0x40800 ${nbblocks} MMC write: dev # 0, block # 264192, count 183513 ... 183513 blocks written: OK I can boot Linux with it without any issues, however if I try to write a file in it I get the following crash: BIOS> ext4write mmc 0:2 ${loadaddr} /boot/${kernelimg} ${filesize} File System is consistent file found, deleting update journal finished File System is consistent update journal finished data abort pc : [<8ff783ac>] lr : [<8ff86c95>] reloc pc : [<8780e3ac>] lr : [<8781cc95>] sp : 8ef696b8 ip : 00000000 fp : 8ffbc6d8 r10: 00000200 r9 : 8ef69ee8 r8 : 8ffbc744 r7 : 8ef9f600 r6 : 8ef999b6 r5 : 00000003 r4 : 8ffa35fc r3 : 8ef999b8 r2 : 00000001 r1 : fffffffe r0 : 8ef999c0 Flags: NzCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... I have investigated a bit and I found that the crash is in the ext4fs_deinit() function provoked by the free() call at line 722 (fs/ext4/ext4_write.c) and the ext4fs_deinit() is called in ext4fs_write() at line 980. If I resize the filesystem under Linux, I don't get the crash but the following error: ext4fs_devread read outside partition 4294967294 error in File System init ** Error ext4fs_write() ** ** Unable to write file /boot/opos6ul-linux.bin ** Any idea ? Regards, -- Sébastien Szymanski Software Engineer, Armadeus Systems sebastien.szymanski(a)armadeus.com Tel: +33 (0)9 72 29 41 44 Fax: +33 (0)9 72 28 79 26

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