January 2017 - U-Boot

[U-Boot] [PATCH] tools: Correct python building host tools
by Tom Rini 25 Jan '17

25 Jan '17

When we have python building tools for the host it will not check HOSTXX variables but only XX variables, for example LDFLAGS and not HOSTLDFLAGS. Cc: Simon Glass <sjg(a)chromium.org> Reported-by: Heiko Schocher <hs(a)denx.de> Fixes: 1905c8fc711a ("build: Always build the libfdt python module") Signed-off-by: Tom Rini <trini(a)konsulko.com> --- tools/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index a609d058595b..cefcedf683ca 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -117,7 +117,8 @@ _libfdt.so-sharedobjs += $(LIBFDT_OBJS) libfdt: tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c - python $(srctree)/lib/libfdt/setup.py "$(_hostc_flags)" $^ + LDFLAGS="$(HOSTLDFLAGS)" python $(srctree)/lib/libfdt/setup.py \ + "$(_hostc_flags)" $^ mv _libfdt.so $@ tools/libfdt_wrap.c: $(srctree)/lib/libfdt/libfdt.swig -- 1.9.1

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[U-Boot] [PATCH] bootz/booti: relocate ramdisk if CONFIG_SYS_BOOT_RAMDISK_HIGH set
by Cédric Schieli 25 Jan '17

25 Jan '17

In commit c2e7e72, the ramdisk relocation code was moved from image_setup_linux to do_bootm, leaving the bootz and booti cases broken. This patch fixes both by adding the BOOTM_STATE_RAMDISK state in their call to do_bootm_states if CONFIG_SYS_BOOT_RAMDISK_HIGH is set. Signed-off-by: Cédric Schieli <cschieli(a)gmail.com> --- cmd/booti.c | 3 +++ cmd/bootz.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/cmd/booti.c b/cmd/booti.c index 6c1c998..2d879f3 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -132,6 +132,9 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) images.os.os = IH_OS_LINUX; ret = do_bootm_states(cmdtp, flag, argc, argv, +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH + BOOTM_STATE_RAMDISK | +#endif BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO, &images, 1); diff --git a/cmd/bootz.c b/cmd/bootz.c index 9648fe9..ceff01b 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -76,6 +76,9 @@ int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) images.os.os = IH_OS_LINUX; ret = do_bootm_states(cmdtp, flag, argc, argv, +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH + BOOTM_STATE_RAMDISK | +#endif BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO, &images, 1); -- 2.10.2

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[U-Boot] [PATCH] arm: am57xx: cl-som-am57x: fix Ethernet
by Uri Mashiach 25 Jan '17

25 Jan '17

The module is continuously rebooting with the following message: Net: data abort pc : [<fff77f42>] lr : [<fff6e32b>] reloc pc : [<80816f42>] lr : [<8080d32b>] sp : fdf5ce48 ip : fdf5d79c fp : 00000017 r10: 8083cd58 r9 : fdf5cef0 r8 : fdf5d5d0 r7 : 48485000 r6 : 400000ff r5 : fdf5d6e0 r4 : fdf5d618 r3 : fdf5d5b4 r2 : fdf5d5d0 r1 : 643a3631 r0 : fdf5d6e0 Flags: nzCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Modifications: * Enable Ethernet configuration in the SPL. * Update PINMUX of PHY enable GPIO. Signed-off-by: Uri Mashiach <uri.mashiach(a)compulab.co.il> --- board/compulab/cl-som-am57x/mux.c | 2 +- include/configs/cl-som-am57x.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/compulab/cl-som-am57x/mux.c b/board/compulab/cl-som-am57x/mux.c index 5b71975..0db0609 100644 --- a/board/compulab/cl-som-am57x/mux.c +++ b/board/compulab/cl-som-am57x/mux.c @@ -102,7 +102,7 @@ static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = { {VIN2A_D22, (IEN | PDIS | PTD | M3) }, /* VIN2A_D22.RGMII1_RXD1 */ {VIN2A_D23, (IEN | PDIS | PTD | M3) }, /* VIN2A_D23.RGMII1_RXD0 */ /* Eth PHY1 reset GPIOs*/ - {VIN1B_CLK1, (IDIS | PDIS | PTD | M14)}, /* VIN1B_CLK1.GPIO2_31 */ + {VIN2A_CLK0, (IDIS | PDIS | PTD | M14)}, /* VIN2A_CLK0.GPIO3_28 */ }; #define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \ diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h index 6692acc..9111cbd 100644 --- a/include/configs/cl-som-am57x.h +++ b/include/configs/cl-som-am57x.h @@ -103,6 +103,8 @@ #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_MCS7830 +#endif /* !CONFIG_SPL_BUILD */ + /* CPSW Ethernet */ #define CONFIG_DRIVER_TI_CPSW #define CONFIG_MII @@ -120,8 +122,6 @@ #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_NET_RETRY_COUNT 10 -#endif /* !CONFIG_SPL_BUILD */ - /* Default environment */ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ -- 2.7.4

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[U-Boot] [PATCH 1/3] imx31_phycore: Split the eet variant out into a different TARGET
by Tom Rini 25 Jan '17

25 Jan '17

Rename CONFIG_IMX31_PHYCORE_EET to CONFIG_TARGET_IMX31_PHYCORE_EET and make this a distinct config target. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/arm/Kconfig | 6 +++++- board/imx31_phycore/Kconfig | 2 +- configs/imx31_phycore_eet_defconfig | 3 +-- include/configs/imx31_phycore.h | 2 +- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 855871c..472b3d4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -315,7 +315,11 @@ config TARGET_X600 select SUPPORT_SPL config TARGET_IMX31_PHYCORE - bool "Support imx31_phycore" + bool "Support imx31_phycore_eet" + select CPU_ARM1136 + +config TARGET_IMX31_PHYCORE_EET + bool "Support imx31_phycore_eet" select CPU_ARM1136 config TARGET_MX31ADS diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig index d3d2025..e897ee1 100644 --- a/board/imx31_phycore/Kconfig +++ b/board/imx31_phycore/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX31_PHYCORE +if TARGET_IMX31_PHYCORE || TARGET_IMX31_PHYCORE_EET config SYS_BOARD default "imx31_phycore" diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig index 1137194..bc9dea6 100644 --- a/configs/imx31_phycore_eet_defconfig +++ b/configs/imx31_phycore_eet_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y -CONFIG_TARGET_IMX31_PHYCORE=y +CONFIG_TARGET_IMX31_PHYCORE_EET=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index efeb008..de333e9 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -168,7 +168,7 @@ #define CONFIG_JFFS2_DEV "nor0" /* EET platform additions */ -#ifdef CONFIG_IMX31_PHYCORE_EET +#ifdef CONFIG_TARGET_IMX31_PHYCORE_EET #define CONFIG_MXC_GPIO #define CONFIG_HARD_SPI -- 2.1.4

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[U-Boot] [PATCH v2] rpi: Fix device tree path on ARM64
by Tuomas Tynkkynen 25 Jan '17

25 Jan '17

The directory structure of device tree files produced by the kernel's 'make dtbs_install' is different on ARM64, the RPi3 device tree file is in a 'broadcom' subdirectory there. Signed-off-by: Tuomas Tynkkynen <tuomas(a)tuxera.com> --- v2: Build the full DTB at compile-time, not runtime. board/raspberrypi/rpi/rpi.c | 48 +++++++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 22e87a2a13..2146534b36 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -65,6 +65,12 @@ struct msg_get_clock_rate { u32 end_tag; }; +#ifdef CONFIG_ARM64 +#define DTB_DIR "broadcom/" +#else +#define DTB_DIR "" +#endif + /* * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-r… * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 @@ -83,24 +89,24 @@ struct rpi_model { static const struct rpi_model rpi_model_unknown = { "Unknown model", - "bcm283x-rpi-other.dtb", + DTB_DIR "bcm283x-rpi-other.dtb", false, }; static const struct rpi_model rpi_models_new_scheme[] = { [0x4] = { "2 Model B", - "bcm2836-rpi-2-b.dtb", + DTB_DIR "bcm2836-rpi-2-b.dtb", true, }, [0x8] = { "3 Model B", - "bcm2837-rpi-3-b.dtb", + DTB_DIR "bcm2837-rpi-3-b.dtb", true, }, [0x9] = { "Zero", - "bcm2835-rpi-zero.dtb", + DTB_DIR "bcm2835-rpi-zero.dtb", false, }, }; @@ -108,87 +114,87 @@ static const struct rpi_model rpi_models_new_scheme[] = { static const struct rpi_model rpi_models_old_scheme[] = { [0x2] = { "Model B", - "bcm2835-rpi-b.dtb", + DTB_DIR "bcm2835-rpi-b.dtb", true, }, [0x3] = { "Model B", - "bcm2835-rpi-b.dtb", + DTB_DIR "bcm2835-rpi-b.dtb", true, }, [0x4] = { "Model B rev2", - "bcm2835-rpi-b-rev2.dtb", + DTB_DIR "bcm2835-rpi-b-rev2.dtb", true, }, [0x5] = { "Model B rev2", - "bcm2835-rpi-b-rev2.dtb", + DTB_DIR "bcm2835-rpi-b-rev2.dtb", true, }, [0x6] = { "Model B rev2", - "bcm2835-rpi-b-rev2.dtb", + DTB_DIR "bcm2835-rpi-b-rev2.dtb", true, }, [0x7] = { "Model A", - "bcm2835-rpi-a.dtb", + DTB_DIR "bcm2835-rpi-a.dtb", false, }, [0x8] = { "Model A", - "bcm2835-rpi-a.dtb", + DTB_DIR "bcm2835-rpi-a.dtb", false, }, [0x9] = { "Model A", - "bcm2835-rpi-a.dtb", + DTB_DIR "bcm2835-rpi-a.dtb", false, }, [0xd] = { "Model B rev2", - "bcm2835-rpi-b-rev2.dtb", + DTB_DIR "bcm2835-rpi-b-rev2.dtb", true, }, [0xe] = { "Model B rev2", - "bcm2835-rpi-b-rev2.dtb", + DTB_DIR "bcm2835-rpi-b-rev2.dtb", true, }, [0xf] = { "Model B rev2", - "bcm2835-rpi-b-rev2.dtb", + DTB_DIR "bcm2835-rpi-b-rev2.dtb", true, }, [0x10] = { "Model B+", - "bcm2835-rpi-b-plus.dtb", + DTB_DIR "bcm2835-rpi-b-plus.dtb", true, }, [0x11] = { "Compute Module", - "bcm2835-rpi-cm.dtb", + DTB_DIR "bcm2835-rpi-cm.dtb", false, }, [0x12] = { "Model A+", - "bcm2835-rpi-a-plus.dtb", + DTB_DIR "bcm2835-rpi-a-plus.dtb", false, }, [0x13] = { "Model B+", - "bcm2835-rpi-b-plus.dtb", + DTB_DIR "bcm2835-rpi-b-plus.dtb", true, }, [0x14] = { "Compute Module", - "bcm2835-rpi-cm.dtb", + DTB_DIR "bcm2835-rpi-cm.dtb", false, }, [0x15] = { "Model A+", - "bcm2835-rpi-a-plus.dtb", + DTB_DIR "bcm2835-rpi-a-plus.dtb", false, }, }; -- 2.11.0

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[U-Boot] [GIT PULL] Please pull u-boot-mmc master
by Jaehoon Chung 25 Jan '17

25 Jan '17

Dear Tom, Could you pull these patches on your master branch? The following changes since commit 0c9e85f67cd86d2d7a3424ea3ebff0e6db7a3915: Merge branch 'master' of git://git.denx.de/u-boot-uniphier (2017-01-22 17:07:48 -0500) are available in the git repository at: http://git.denx.de/u-boot-mmc.git master for you to fetch changes up to 919b485834a746cf839ccded41e456d17d57a31f: mmc: Print error code for mmc_complete_init failure (2017-01-23 15:37:42 +0900) ---------------------------------------------------------------- Jagan Teki (1): mmc: Print error code for mmc_complete_init failure Stefan Herbrechtsmeier (1): mmc: sdhci: Distinguish between base clock and maximum peripheral frequency drivers/mmc/atmel_sdhci.c | 7 +++++-- drivers/mmc/bcm2835_sdhci.c | 3 ++- drivers/mmc/ftsdc021_sdhci.c | 3 ++- drivers/mmc/kona_sdhci.c | 3 ++- drivers/mmc/mmc.c | 4 +++- drivers/mmc/msm_sdhci.c | 2 ++ drivers/mmc/mv_sdhci.c | 3 ++- drivers/mmc/pci_mmc.c | 1 + drivers/mmc/pic32_sdhci.c | 4 +++- drivers/mmc/rockchip_sdhci.c | 4 ++-- drivers/mmc/s5p_sdhci.c | 5 +++-- drivers/mmc/sdhci.c | 34 ++++++++++++++++++---------------- drivers/mmc/zynq_sdhci.c | 4 +++- include/sdhci.h | 13 +++++++------ 14 files changed, 55 insertions(+), 35 deletions(-) Best Regards, Jaehoon Chung

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Re: [U-Boot] [U-Boot, v4, 1/16] nand: sunxi: Fix modulo by zero error
by Leon Woestenberg 25 Jan '17

25 Jan '17

Hello Maxime, Jagan, [as I was not subscribed to the u-boot mailing list from this email address yet, I could not properly reply, nor do I have my git-send-patch setup yet.] I tried the patch series and reproduced the sunxi-spl-with-ecc.bin flow on an A13 Olinuxino board with NAND. I think the fix for the modulo by 0 must also be applied to the nand_read_buffer() function as follows: diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 24c5dcc..f7d31bc 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -486,17 +486,24 @@ static int nand_detect_config(struct nfc_config *conf, u32 offs, void *dest) static int nand_read_buffer(struct nfc_config *conf, uint32_t offs, unsigned int size, void *dest) { - int first_seed, page, ret; + int first_seed = 0, page, ret; size = ALIGN(size, conf->page_size); page = offs / conf->page_size; - first_seed = page % conf->nseeds; + if (conf->randomize) + first_seed = page % conf->nseeds; With that fix, I could boot U-Boot through the U-Boot SPL, fully from NAND on an A13-Olinuxino-WiFi board with 8192/640. Regards, Leon. > From patchwork Mon Jan 23 13:46:43 2017 > Content-Type: text/plain; charset="utf-8" > MIME-Version: 1.0 > Content-Transfer-Encoding: 7bit > Subject: [U-Boot,v4,1/16] nand: sunxi: Fix modulo by zero error > From: Maxime Ripard <maxime.ripard(a)free-electrons.com> > X-Patchwork-Id: 718570 > X-Patchwork-Delegate: jagannadh.teki(a)gmail.com > Message-Id: <57745204e0a659bdcce05f77a5681fa0ab60690b.1485179128.git-series.maxime.ripard(a)free-electrons.com> > To: Jagan Teki <jagan(a)openedev.com>, > Scott Wood <oss(a)buserror.net> > Cc: Thomas Petazzoni <thomas.petazzoni(a)free-electrons.com>, > Alexander Kaplan <alex(a)nextthing.co>, > Maxime Ripard <maxime.ripard(a)free-electrons.com>, u-boot(a)lists.denx.de > Date: Mon, 23 Jan 2017 14:46:43 +0100 > > When trying to autodetect the ECC and randomization configurations, the > driver starts with a randomization disabled and no seeds. > > In this case, the number of seeds is obviously 0, and the randomize boolean > is set to false. > > However, the logic that retrieves the seed for a given page offset will > blindly use the number of seeds, without testing if the randomization is > enabled, basically doing a modulo by 0. > > As it turns out, the libgcc in the common toolchain returns 0 here, which > was our expected value in such a case, and why we would not detect it. > However, U-Boot's libgcc will for some reason return from the function > instead, resulting in an error to load the U-Boot binary in the SPL. > > Signed-off-by: Maxime Ripard <maxime.ripard(a)free-electrons.com> > Acked-by: Boris Brezillon <boris.brezillon(a)free-electrons.com> > Acked-by: Scott Wood <oss(a)buserror.net> > --- > drivers/mtd/nand/sunxi_nand_spl.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c > index 1ef7366d4c42..eed4472bdc34 100644 > --- a/drivers/mtd/nand/sunxi_nand_spl.c > +++ b/drivers/mtd/nand/sunxi_nand_spl.c > @@ -245,7 +245,7 @@ static int nand_read_page(const struct nfc_config *conf, u32 offs, > { > dma_addr_t dst = (dma_addr_t)dest; > int nsectors = len / conf->ecc_size; > - u16 rand_seed; > + u16 rand_seed = 0; > u32 val; > int page; > > @@ -258,8 +258,9 @@ static int nand_read_page(const struct nfc_config *conf, u32 offs, > /* clear ecc status */ > writel(0, SUNXI_NFC_BASE + NFC_ECC_ST); > > - /* Choose correct seed */ > - rand_seed = random_seed[page % conf->nseeds]; > + /* Choose correct seed if randomized */ > + if (conf->randomize) > + rand_seed = random_seed[page % conf->nseeds]; > > writel((rand_seed << 16) | (conf->ecc_strength << 12) | > (conf->randomize ? NFC_ECC_RANDOM_EN : 0) | >

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[U-Boot] [PATCH] powerpc: Enable flush and invalidate dcache by range for MPC85xx
by Tony O'Brien 24 Jan '17

24 Jan '17

Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-ops for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues in some drivers when the dcache was flushed. While the root cause was under investigation, these functions were disabled in Commit cb1629f91a for affected SoCs, including the MPC85xx, to make the various drivers work. On the T208x USB stopped working after v2016.07 was pulled. After re-enabling the dcache functions for the MPC85xx it started working again. The USB and DPPA Ethernet drivers have been seen as operational after this change but other drivers cannot be tested. Reviewed-by: Chris Packham <chris.packham(a)alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien(a)alliedtelesis.co.nz> Cc: Marek Vasut <marex(a)denx.de> Cc: York Sun <york.sun(a)nxp.com> --- The USB and Ethernet functionality has been tested on both the T2080RDB and our own design but we don't have the hardware to test any of the other drivers. We will wait and see if it causes us any issues with other drivers. arch/powerpc/lib/ppccache.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index 66cf02dbd0..ad28c7c369 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -65,7 +65,7 @@ ppcSync: * flush_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(flush_dcache_range) -#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 @@ -89,7 +89,7 @@ _GLOBAL(flush_dcache_range) * invalidate_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(invalidate_dcache_range) -#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 -- 2.11.0

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[U-Boot] [PATCH v2] mpc85xx: pci: Implement workaround for Erratum A007815
by Tony O'Brien 24 Jan '17

24 Jan '17

The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin <hamish.martin(a)alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien(a)alliedtelesis.co.nz> --- Note that this does not implement the whole fix for this erratum, just what is necessary for our implementation. Since we are using a fixed RC configuration, no support has been added for EP mode or any consideration of link-up/down events. --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/fsl_pci.h | 4 +++- drivers/pci/fsl_pci_init.c | 7 +++++++ 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 402a1ff..aabb56b 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -330,6 +330,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 puts("Work-around for Erratum A009663 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + puts("Work-around for Erratum A007815 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index c92bc1e..c298e44 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -785,6 +785,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A007815 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define CONFIG_SYS_FSL_SFP_VER_3_0 diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 8bee8ca..cad341e 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -79,7 +79,9 @@ typedef struct ccsr_pci { u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ u32 pm_command; /* 0x02c - PCIE PM Command register */ - char res4[3016]; /* (- #xbf8 #x30)3016 */ + char res3[2188]; /* (0x8bc - 0x30 = 2188) */ + u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */ + char res4[824]; /* (0xbf8 - 0x8c0 = 824) */ u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 52792dc..af20cf0 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); } +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + /* The Read-Only Write Enable bit defaults to 1 instead of 0. + * Set to 0 to protect the read-only registers. + */ + clrbits_be32(&pci->dbi_ro_wr_en, 0x01); +#endif + /* Use generic setup_device to initialize standard pci regs, * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. -- 2.10.2

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[U-Boot] [PATCH] mpc85xx: pci: Implement workaround for Erratum A007815
by Tony O'Brien 24 Jan '17

24 Jan '17

The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin <hamish.martin(a)alliedtelesis.co.nz> --- Note that this does not implement the whole fix for this erratum, just what is necessary for our implementation. Since we are using a fixed RC configuration, no support has been added for EP mode or any consideration of link-up/down events. Signed-off-by: Tony O'Brien <tony.obrien(a)alliedtelesis.co.nz> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/fsl_pci.h | 4 +++- drivers/pci/fsl_pci_init.c | 7 +++++++ 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 402a1ff..aabb56b 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -330,6 +330,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 puts("Work-around for Erratum A009663 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + puts("Work-around for Erratum A007815 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index c92bc1e..c298e44 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -785,6 +785,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A007815 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define CONFIG_SYS_FSL_SFP_VER_3_0 diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 8bee8ca..cad341e 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -79,7 +79,9 @@ typedef struct ccsr_pci { u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ u32 pm_command; /* 0x02c - PCIE PM Command register */ - char res4[3016]; /* (- #xbf8 #x30)3016 */ + char res3[2188]; /* (0x8bc - 0x30 = 2188) */ + u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */ + char res4[824]; /* (0xbf8 - 0x8c0 = 824) */ u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 52792dc..af20cf0 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); } +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + /* The Read-Only Write Enable bit defaults to 1 instead of 0. + * Set to 0 to protect the read-only registers. + */ + clrbits_be32(&pci->dbi_ro_wr_en, 0x01); +#endif + /* Use generic setup_device to initialize standard pci regs, * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. -- 2.10.2

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