June 2016 - U-Boot

[U-Boot] [PATCH 0/5] tools: moveconfig: some more fix, cleanups, improvement
by Masahiro Yamada 22 Jun '16

22 Jun '16

I sent a pull request for moveconfig recently, but this tool can be improved more. (This series has no impact on the on-going BOOTDELAY fix-up.) Masahiro Yamada (5): tools: moveconfig: fix needless move for config with default 1 tools: moveconfig: change class WorkDir to class ReferenceSource tools: moveconfig: simplify source tree switching tools: moveconfig: simplify show_failed_boards() and show more info tools: moveconfig: show suspicious boards with possible misconversion tools/moveconfig.py | 130 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 81 insertions(+), 49 deletions(-) -- 1.9.1

2 15

[U-Boot] [PATCH] NFS: Add error message when U-Boot NFS version (V2) is not supported by NFS server
by Guillaume GARDET 22 Jun '16

22 Jun '16

Signed-off-by: Guillaume GARDET <guillaume.gardet(a)free.fr> Cc: joe.hershberger(a)ni.com --- net/nfs.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/net/nfs.c b/net/nfs.c index 78968d8..0ed47c9 100644 --- a/net/nfs.c +++ b/net/nfs.c @@ -481,8 +481,22 @@ static int nfs_lookup_reply(uchar *pkt, unsigned len) if (rpc_pkt.u.reply.rstatus || rpc_pkt.u.reply.verifier || rpc_pkt.u.reply.astatus || - rpc_pkt.u.reply.data[0]) + rpc_pkt.u.reply.data[0]){ + switch(ntohl(rpc_pkt.u.reply.astatus)){ + case 0: /* Not an error */ + break; + case 2: /* Remote can't support NFS version */ + printf("*** ERROR: NFS version not supported: Requested: V%d, accepted: min V%d - max V%d\n", + 2, + ntohl(rpc_pkt.u.reply.data[0]), + ntohl(rpc_pkt.u.reply.data[1])); + break; + default: /* Unknown error on 'accept state' flag */ + printf("*** ERROR: accept state error (%d)\n", ntohl(rpc_pkt.u.reply.astatus)); + break; + } return -1; + } memcpy(filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE); -- 1.8.4.5

4 5

[U-Boot] [PATCH] net: phy: marvell: Do not reset 88e1310 after autoneg
by Nathan Rossi 22 Jun '16

22 Jun '16

Commit a058052c "net: phy: do not read configuration register on reset", changes the behaviour of the phy_reset function such that the state of the BMCR register is not preserved during reset. Change the config function for the m88e1310 so that it does not do a reset after configuring auto-negotiation. Signed-off-by: Nathan Rossi <nathan(a)nathanrossi.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Stefan Roese <sr(a)denx.de> --- drivers/net/phy/marvell.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index d2e68d4..58d287b 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -476,10 +476,7 @@ static int m88e1310_config(struct phy_device *phydev) /* Ensure to return to page 0 */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); - genphy_config_aneg(phydev); - phy_reset(phydev); - - return 0; + return genphy_config_aneg(phydev); } static struct phy_driver M88E1011S_driver = { -- 2.8.1

5 4

[U-Boot] [PATCH] net: phy: micrel: add support for KSZ886x switches in MIIM mode
by Alexey Firago 22 Jun '16

22 Jun '16

This patch adds a phy driver for the Micrel KSZ886x switches. Similarly to the KSZ8895, SoC MAC is directly connected to the switch MAC on the switch CPU port, so the link to the switch is always up. KSZ886x switches can be used in the following configuration modes: - Unmanaged mode with config stored in external EEPROM - Managed mode over SPI - Managed mode over I2C - Managed mode over mdio/mdc (aka MIIM or SMI) This patch supports only unmanaged and MIIM modes. Based on Micrel KSZ886x driver from Linux kernel and Micrel KSZ8895 driver from U-Boot. Verified with the KSZ8863MLL. Signed-off-by: Alexey Firago <alexey_firago(a)mentor.com> --- drivers/net/phy/micrel.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 8fcf737..58891f8 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -482,6 +482,31 @@ static struct phy_driver ksz9031_driver = { .readext = &ksz9031_phy_extread, }; +int ksz886x_config(struct phy_device *phydev) +{ + /* we are connected directly to the switch without + * dedicated PHY. */ + phydev->link = 1; + phydev->duplex = DUPLEX_FULL; + phydev->speed = SPEED_100; + return 0; +} + +static int ksz886x_startup(struct phy_device *phydev) +{ + return 0; +} + +static struct phy_driver ksz886x_driver = { + .name = "Micrel KSZ886x Switch", + .uid = 0x00221430, + .mask = 0xfffff0, + .features = PHY_BASIC_FEATURES, + .config = &ksz886x_config, + .startup = &ksz886x_startup, + .shutdown = &genphy_shutdown, +}; + int phy_micrel_init(void) { phy_register(&KSZ804_driver); @@ -495,5 +520,6 @@ int phy_micrel_init(void) #endif phy_register(&ksz9031_driver); phy_register(&ksz8895_driver); + phy_register(&ksz886x_driver); return 0; } -- 1.9.1

3 2

[U-Boot] [PATCH] net: rtl8169: fix switching between adapters
by Stephen Warren 22 Jun '16

22 Jun '16

From: Stephen Warren <swarren(a)nvidia.com> The rtl8169 driver uses a global variable to store the register address of the adapter being operated upon. This is updated to point at the correct adapter when sending or receiving a packet, or shutting down the adapter, but not when initializing the adapter. Consequently, switching between different adapters within the same U-Boot runtime does not work correctly since the driver programs the wrong registers during rtl8169_eth_start() -> rtl8169_common_start() -> rtl8169_hw_start(). Note that since rtl8169_eth_stop() does set the global variable, the second consecutive attempt to use the "new" adapter did work even before this patch, because each time network usage is shut down, the network core calls stop, which sets the variable so that the next start does actually initialize the hardware, and the adapter works. Equally, rtl8169_eth_probe() calls rtl_init() which sets the global, so if using only a single device, or if picking the "right" device (based on probe order) when multiple devices are present, ioaddr will already be set correctly from the get-go, so the issue does not occur. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- Note that as with almost any patch, I believe NVIDIA copyright applies to the submission. However, I don't want to block all my work based on that other conversion, so I'm just going to deliberately ignore our policy of adding/updating copyright headers to files when editing them. Hopefully doing so deliberately (rather than the usual case of just forgetting) doesn't get me fired. --- drivers/net/rtl8169.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 163b9df55c9b..843b083f8f90 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -850,9 +850,11 @@ static void rtl8169_init_ring(pci_dev_t dev) } #ifdef CONFIG_DM_ETH -static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr) +static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr, + unsigned long dev_iobase) #else -static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr) +static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr, + unsigned long dev_iobase) #endif { int i; @@ -862,6 +864,8 @@ static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr) printf ("%s\n", __FUNCTION__); #endif + ioaddr = dev_iobase; + rtl8169_init_ring(dev); rtl8169_hw_start(dev); /* Construct a perfect filter frame with the mac address as first match @@ -885,8 +889,9 @@ static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr) static int rtl8169_eth_start(struct udevice *dev) { struct eth_pdata *plat = dev_get_platdata(dev); + struct rtl8169_private *priv = dev_get_priv(dev); - rtl8169_common_start(dev, plat->enetaddr); + rtl8169_common_start(dev, plat->enetaddr, priv->iobase); return 0; } @@ -897,7 +902,7 @@ RESET - Finish setting up the ethernet interface static int rtl_reset(struct eth_device *dev, bd_t *bis) { rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv, - dev->enetaddr); + dev->enetaddr, dev->iobase); return 0; } -- 2.8.1

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[U-Boot] [PATCH] pci: tegra: correctly program PADS_REFCLK registers
by Stephen Warren 21 Jun '16

21 Jun '16

From: Stephen Warren <swarren(a)nvidia.com> The value that should be programmed into the PADS_REFCLK register varies per SoC. Fix the Tegra PCIe driver to program the correct values. Future SoCs will require different values in cfg0/1, so the two values are stored separately in the per-SoC data structures. For reference, the values are all documented in NV bug 1771116 comment 20. The Tegra210 value doesn't match the current TRM, but I've filed a bug to get the TRM fixed. Earlier TRMs don't document the value this register should contain, but the ASIC team has validated all these values, except for the Tegra20 value which is simply left unchanged in this patch. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- drivers/pci/pci_tegra.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index c5b04daffa65..1aa56fc93739 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -154,15 +154,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ -/* Default value provided by HW engineering is 0xfa5c */ -#define PADS_REFCLK_CFG_VALUE \ - ( \ - (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ - (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ - (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ - (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ - ) - #define RP_VEND_XP 0x00000F00 #define RP_VEND_XP_DL_UP (1 << 30) @@ -198,6 +189,8 @@ struct tegra_pcie_soc { unsigned int num_ports; unsigned long pads_pll_ctl; unsigned long tx_ref_sel; + u32 pads_refclk_cfg0; + u32 pads_refclk_cfg1; bool has_pex_clkreq_en; bool has_pex_bias_ctrl; bool has_cml_clk; @@ -628,11 +621,9 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) pads_writel(pcie, value, soc->pads_pll_ctl); /* configure the reference clock driver */ - value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); - pads_writel(pcie, value, PADS_REFCLK_CFG0); - + pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); if (soc->num_ports > 2) - pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); + pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); /* wait for the PLL to lock */ err = tegra_pcie_pll_wait(pcie, 500); @@ -943,6 +934,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = { .num_ports = 2, .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, + .pads_refclk_cfg0 = 0xfa5cfa5c, .has_pex_clkreq_en = false, .has_pex_bias_ctrl = false, .has_cml_clk = false, @@ -952,6 +944,8 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = { .num_ports = 3, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .pads_refclk_cfg0 = 0xfa5cfa5c, + .pads_refclk_cfg1 = 0xfa5cfa5c, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_cml_clk = true, @@ -961,6 +955,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = { .num_ports = 2, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .pads_refclk_cfg0 = 0x44ac44ac, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_cml_clk = true, @@ -970,6 +965,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = { .num_ports = 2, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .pads_refclk_cfg0 = 0x90b890b8, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_cml_clk = true, -- 2.9.0

1 0

[U-Boot] [PATCH] x86: Add Advantech SOM-DB5800/SOM-6867 support
by George McCollister 21 Jun '16

21 Jun '16

Add support for Advantech SOM-DB5800 with the SOM-6867 installed. This is very similar to conga-qeval20-qa3-e3845 in that there is a reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867) installed. Currently supported: - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on SOM-DB5800. - 4x USB 2.0 (EHCI) - Video - SATA - Ethernet - PCIe - Realtek ALC892 HD Audio Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO HDA_SDI0 is set in DT to enable HD Audio codec. Pin defaults for codec pin complexs are not changed. Not supported: - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500) - USB 3.0 (XHCI) - TPM Signed-off-by: George McCollister <george.mccollister(a)gmail.com> --- arch/x86/Kconfig | 4 + arch/x86/dts/Makefile | 3 +- arch/x86/dts/baytrail_som-db5800-som-6867.dts | 299 +++++++++++++++++++++ board/advantech/Kconfig | 28 ++ board/advantech/som-db5800-som-6867/.gitignore | 3 + board/advantech/som-db5800-som-6867/Kconfig | 28 ++ board/advantech/som-db5800-som-6867/MAINTAINERS | 7 + board/advantech/som-db5800-som-6867/Makefile | 8 + .../som-db5800-som-6867/acpi/mainboard.asl | 11 + board/advantech/som-db5800-som-6867/dsdt.asl | 14 + .../som-db5800-som-6867/som-db5800-som-6867.c | 28 ++ board/advantech/som-db5800-som-6867/start.S | 9 + configs/som-db5800-som-6867_defconfig | 61 +++++ include/configs/som-db5800-som-6867.h | 41 +++ 14 files changed, 543 insertions(+), 1 deletion(-) create mode 100644 arch/x86/dts/baytrail_som-db5800-som-6867.dts create mode 100644 board/advantech/Kconfig create mode 100644 board/advantech/som-db5800-som-6867/.gitignore create mode 100644 board/advantech/som-db5800-som-6867/Kconfig create mode 100644 board/advantech/som-db5800-som-6867/MAINTAINERS create mode 100644 board/advantech/som-db5800-som-6867/Makefile create mode 100644 board/advantech/som-db5800-som-6867/acpi/mainboard.asl create mode 100644 board/advantech/som-db5800-som-6867/dsdt.asl create mode 100644 board/advantech/som-db5800-som-6867/som-db5800-som-6867.c create mode 100644 board/advantech/som-db5800-som-6867/start.S create mode 100644 configs/som-db5800-som-6867_defconfig create mode 100644 include/configs/som-db5800-som-6867.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 29d2307..29d1120 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -8,6 +8,9 @@ choice prompt "Mainboard vendor" default VENDOR_EMULATION +config VENDOR_ADVANTECH + bool "advantech" + config VENDOR_CONGATEC bool "congatec" @@ -29,6 +32,7 @@ config VENDOR_INTEL endchoice # board-specific options below +source "board/advantech/Kconfig" source "board/congatec/Kconfig" source "board/coreboot/Kconfig" source "board/efi/Kconfig" diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 23156bb..4f07f41 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -14,7 +14,8 @@ dtb-y += bayleybay.dtb \ minnowmax.dtb \ qemu-x86_i440fx.dtb \ qemu-x86_q35.dtb \ - broadwell_som-6896.dtb + broadwell_som-6896.dtb \ + baytrail_som-db5800-som-6867.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts new file mode 100644 index 0000000..e4df151 --- /dev/null +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -0,0 +1,299 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * Copyright (C) 2016, George McCollister <george.mccollister(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "Advantech SOM-DB5800-SOM-6867"; + compatible = "advantech,som-db5800-som-6867", "intel,baytrail"; + + aliases { + serial0 = &serial; + spi0 = &spi; + }; + + config { + silent_console = <0>; + }; + + pch_pinctrl { + compatible = "intel,x86-pinctrl"; + reg = <0 0>; + + /* HDA_RSTB */ + soc_gpio_s0_8@0 { + gpio-offset = <0x0 8>; + pad-offset = <0x220>; + mode-func = <2>; + }; + + /* HDA_SYNC */ + soc_gpio_s0_9@0 { + gpio-offset = <0x0 9>; + pad-offset = <0x250>; + mode-func = <2>; + pull-assign = <1>; + }; + + /* HDA_CLK */ + soc_gpio_s0_10@0 { + gpio-offset = <0x0 10>; + pad-offset = <0x240>; + mode-func = <2>; + }; + + /* HDA_SDO */ + soc_gpio_s0_11@0 { + gpio-offset = <0x0 11>; + pad-offset = <0x260>; + mode-func = <2>; + pull-assign = <1>; + }; + + /* HDA_SDI0 */ + soc_gpio_s0_12@0 { + gpio-offset = <0x0 12>; + pad-offset = <0x270>; + mode-func = <2>; + }; + }; + + chosen { + stdout-path = "/serial"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <1>; + intel,apic-id = <2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <2>; + intel,apic-id = <4>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <3>; + intel,apic-id = <6>; + }; + + }; + + pci { + compatible = "intel,pci-baytrail", "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "pci8086,0f1c", "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,actl-addr = <0>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 1) INTD PIRQD + PCI_BDF(0, 30, 2) INTB PIRQB + PCI_BDF(0, 30, 3) INTC PIRQC + PCI_BDF(0, 30, 4) INTD PIRQD + PCI_BDF(0, 30, 5) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* + * PCIe root ports downstream + * interrupts + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; + + spi: spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9-spi"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "macronix,mx25l6405d", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006f0000 0x00010000>; + }; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; + }; + }; + + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <1>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-azalia; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + fsp,serial-debug-port-address = <0x3f8>; + fsp,serial-debug-port-type = <1>; + }; + + microcode { + update@0 { +#include "microcode/m0130673325.dtsi" + }; + update@1 { +#include "microcode/m0130679907.dtsi" + }; + }; + +}; diff --git a/board/advantech/Kconfig b/board/advantech/Kconfig new file mode 100644 index 0000000..a8d4969 --- /dev/null +++ b/board/advantech/Kconfig @@ -0,0 +1,28 @@ +if VENDOR_ADVANTECH + +choice + prompt "Mainboard model" + optional + +config TARGET_SOM_DB5800_SOM_6867 + bool "Advantech SOM-DB5800 & SOM-6867" + help + Advantech SOM-DB5800 COM Express development board with SOM-6867 + installed. + + SOM-6867 is a COM Express Type 6 Compact Module with either an Intel + Atom E3845 or Celeron N2920 processor. + + SOM-DB5800 is a COM Express Development board with: + 10/100/1000 Ethernet + PCIe slots + 4x USB ports + HDMI/DisplayPort/DVI, LVDS, VGA + SATA ports + ALC892 HD Audio Codec + +endchoice + +source "board/advantech/som-db5800-som-6867/Kconfig" + +endif diff --git a/board/advantech/som-db5800-som-6867/.gitignore b/board/advantech/som-db5800-som-6867/.gitignore new file mode 100644 index 0000000..6eb8a54 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig new file mode 100644 index 0000000..f6f3748 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/Kconfig @@ -0,0 +1,28 @@ +if TARGET_SOM_DB5800_SOM_6867 + +config SYS_BOARD + default "som-db5800-som-6867" + +config SYS_VENDOR + default "advantech" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "som-db5800-som-6867" + +config SYS_TEXT_BASE + default 0xfff00000 if !EFI_STUB + default 0x01110000 if EFI_STUB + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR if !EFI_STUB + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/board/advantech/som-db5800-som-6867/MAINTAINERS b/board/advantech/som-db5800-som-6867/MAINTAINERS new file mode 100644 index 0000000..92989bf --- /dev/null +++ b/board/advantech/som-db5800-som-6867/MAINTAINERS @@ -0,0 +1,7 @@ +Advantech SOM-DB5800-SOM-6867 +M: George McCollister <george.mccollister(a)gmail.com> +S: Maintained +F: board/advantech/som-db5800-som-6867 +F: include/configs/som-db5800-som-6867.h +F: configs/som-db5800-som-6867_defconfig +F: arch/x86/dts/baytrail_som-db5800-som-6867.dts diff --git a/board/advantech/som-db5800-som-6867/Makefile b/board/advantech/som-db5800-som-6867/Makefile new file mode 100644 index 0000000..9837aa0 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015, Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += som-db5800-som-6867.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/advantech/som-db5800-som-6867/acpi/mainboard.asl b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl new file mode 100644 index 0000000..21785ea --- /dev/null +++ b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/advantech/som-db5800-som-6867/dsdt.asl b/board/advantech/som-db5800-som-6867/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c new file mode 100644 index 0000000..73bb565 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * Copyright (C) 2016 George McCollister <george.mccollister(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <winbond_w83627.h> +#include <asm/gpio.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h> + +int board_early_init_f(void) +{ + /* + * The FSP enables the BayTrail internal legacy UART (again). + * Disable it again, so that the one on the EC can be used. + */ + setup_internal_uart(0); + + return 0; +} + +int arch_early_init_r(void) +{ + return 0; +} diff --git a/board/advantech/som-db5800-som-6867/start.S b/board/advantech/som-db5800-som-6867/start.S new file mode 100644 index 0000000..2c941a4 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig new file mode 100644 index 0000000..60a1558 --- /dev/null +++ b/configs/som-db5800-som-6867_defconfig @@ -0,0 +1,61 @@ +CONFIG_X86=y +CONFIG_VENDOR_ADVANTECH=y +CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867" +CONFIG_TARGET_SOM_DB5800_SOM_6867=y +CONFIG_HAVE_INTEL_ME=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_SEABIOS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h new file mode 100644 index 0000000..0ed816c --- /dev/null +++ b/include/configs/som-db5800-som-6867.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_ARCH_MISC_INIT + +#define CONFIG_PCI_PNP +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd,vga\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} + +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x006ef000 + +#endif /* __CONFIG_H */ -- 2.8.0

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[U-Boot] [PATCH v3] Kconfig: Add a new DISTRO_DEFAULTS Kconfig option
by Hans de Goede 21 Jun '16

21 Jun '16

DISTRO_DEFAULTS is intended to mirror / replace include/config_distro_defaults.h. The intend is for boards which include this file to select this from their Kconfig files and when moving setting to Kconfig which are #define-ed in config_distro_defaults.h to select this from DISTRO_DEFAULTS so that boards which have selected DISTRO_DEFAULTS will keep the same configuration as before without needing any defconfig file changes. The initial list of selected things matches all settings recently removed from config_distro_defaults.h because they have been converted to Kconfig, with the exception of CMD_ELF and CMD_NET, which have a default of y, if the default of these ever changes they should be selected by DISTRO_DEFAULTS too. For testing and example purposes this commit also converts ARCH_SUNXI to use DISTRO_DEFAULT instead of selecting everything it needs itself. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- Changes in v2: -Use "default y if ARCH_SUNXI" instead of selecting DISTRO_DEFAULT for sunxi -Document how to enable DISTRO_DEFAULT in doc/README.distro Changes in v3: -Rebase on latest master --- Kconfig | 17 +++++++++++++++++ arch/arm/Kconfig | 9 --------- doc/README.distro | 6 ++++++ 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/Kconfig b/Kconfig index 817f4f0..3ceff25 100644 --- a/Kconfig +++ b/Kconfig @@ -53,6 +53,23 @@ config CC_OPTIMIZE_FOR_SIZE This option is enabled by default for U-Boot. +config DISTRO_DEFAULTS + bool "Select defaults suitable for booting general purpose Linux distributions" + default y if ARCH_SUNXI + default n + select CMD_BOOTZ + select CMD_DHCP + select CMD_EXT2 + select CMD_EXT4 + select CMD_FAT + select CMD_FS_GENERIC + select CMD_MII + select CMD_PING + select HUSH_PARSER + help + Select this to enable various options and commands which are suitable + for building u-boot for booting general purpose Linux distributions. + config SYS_MALLOC_F bool "Enable malloc() pool before relocation" default y if DM diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f48be96..e9d2fc9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -610,16 +610,8 @@ config TARGET_CM_T43 config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" - select CMD_BOOTZ - select CMD_DHCP - select CMD_EXT2 - select CMD_EXT4 - select CMD_FAT - select CMD_FS_GENERIC select CMD_GPIO - select CMD_MII select CMD_MMC if MMC - select CMD_PING select CMD_USB select DM select DM_ETH @@ -627,7 +619,6 @@ config ARCH_SUNXI select DM_KEYBOARD select DM_SERIAL select DM_USB - select HUSH_PARSER select OF_BOARD_SETUP select OF_CONTROL select OF_SEPARATE diff --git a/doc/README.distro b/doc/README.distro index e1b7216..77d5c6d 100644 --- a/doc/README.distro +++ b/doc/README.distro @@ -162,6 +162,12 @@ U-Boot Implementation Enabling the distro options --------------------------- +In your board's defconfig, enable the DISTRO_DEFAULTS option by adding +a line with "CONFIG_DISTRO_DEFAULTS=y". If you want to enable this +from Kconfig itself, for e.g. all boards using a specific SoC then +add a "default y if ARCH_FOO" to the DISTRO_DEFAULTS section of +the Kconfig file in the root of the u-boot sources. + In your board configuration file, include the following: ------------------------------------------------------------ -- 2.7.4

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[U-Boot] [PATCH v2] usb: gadget: f_thor: Free the allocated out request buffer
by Michal Simek 21 Jun '16

21 Jun '16

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Fix the memory leak by freeing the allocated out request buffer Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Simplify logic reported by Marek drivers/usb/gadget/f_thor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index a60e9487e774..cd4d9e659a39 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -891,6 +891,7 @@ static void thor_func_disable(struct usb_function *f) } if (dev->out_ep->driver_data) { + free(dev->out_req->buf); dev->out_req->buf = NULL; usb_ep_free_request(dev->out_ep, dev->out_req); usb_ep_disable(dev->out_ep); -- 1.9.1

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[U-Boot] imx7d spansion spi flash first sector
by Michael Trimarchi 21 Jun '16

21 Jun '16

Hi I'm trying to flash on a spansion spi flash connected on qspi on imx7d board. SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB I have some problem: - I can't erase the first sector - I don't know if BOOT_FROM qspi BOOT_OFFSET FLASH_OFFSET_QSPI I need to use those or the spi one. What is the correct procedure to flash on it? Michael -- | Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com |

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