June 2016 - U-Boot

[U-Boot] Please pull u-boot-dm
by Simon Glass 20 Jun '16

20 Jun '16

Hi Tom, This includes changes to the clock API so I'd like to get this into this release to avoid too much churn. The following changes since commit 9ab165d8b05706284de0ee9bd402346c54ae6b15: SPL ext: cosmetic: correct error message in spl_load_image_ext() (2016-06-19 09:57:48 -0400) are available in the git repository at: git://git.denx.de/u-boot-dm.git for you to fetch changes up to 135aa95002646c46e89de93fa36adad1b010548f: clk: convert API to match reset/mailbox style (2016-06-19 17:05:55 -0600) ---------------------------------------------------------------- Angelo Dureghello (1): dm: add manual relocation for devices Robert P. J. Day (1): lib/libfdt/: General aesthetic/style fixes. Stephen Warren (5): mailbox: rename headers mailbox: add Tegra186 HSP driver Add a reset driver framework/uclass reset: implement a reset test clk: convert API to match reset/mailbox style mario.six(a)gdsys.cc (2): gpio: pca953x: Fix register reading past 8th GPIO sandbox: gpio: doc: Fix parameter documentation arch/arm/dts/tegra186.dtsi | 13 +++ arch/arm/include/asm/arch-rockchip/clock.h | 12 --- arch/arm/mach-rockchip/board.c | 39 +++++++- arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 15 ++- arch/arm/mach-snapdragon/clock-apq8016.c | 10 +- arch/arm/mach-tegra/Kconfig | 2 + arch/arm/mach-zynq/clk.c | 1 - arch/mips/mach-pic32/cpu.c | 45 +++++---- arch/sandbox/dts/test.dts | 28 +++++- arch/sandbox/include/asm/clk.h | 111 +++++++++++++++++++++ arch/sandbox/include/asm/gpio.h | 16 +-- arch/sandbox/include/asm/reset.h | 21 ++++ arch/sandbox/include/asm/test.h | 9 -- board/microchip/pic32mzda/pic32mzda.c | 21 +++- configs/sandbox_defconfig | 10 +- doc/device-tree-bindings/reset/reset.txt | 75 ++++++++++++++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/clk/Makefile | 1 + drivers/clk/clk-uclass.c | 202 +++++++++++++++++++++++++++----------- drivers/clk/clk_fixed_rate.c | 13 +-- drivers/clk/clk_pic32.c | 32 +++--- drivers/clk/clk_rk3036.c | 83 ++++------------ drivers/clk/clk_rk3288.c | 143 +++++---------------------- drivers/clk/clk_sandbox.c | 85 ++++++++++------ drivers/clk/clk_sandbox_test.c | 101 +++++++++++++++++++ drivers/clk/exynos/clk-exynos7420.c | 42 ++++---- drivers/clk/uniphier/clk-uniphier-core.c | 26 ++--- drivers/clk/uniphier/clk-uniphier-mio.c | 1 - drivers/core/root.c | 15 +++ drivers/gpio/pca953x_gpio.c | 4 +- drivers/i2c/rk_i2c.c | 6 +- drivers/mailbox/Kconfig | 7 ++ drivers/mailbox/Makefile | 1 + drivers/mailbox/mailbox-uclass.c | 4 +- drivers/mailbox/sandbox-mbox-test.c | 2 +- drivers/mailbox/sandbox-mbox.c | 2 +- drivers/mailbox/tegra-hsp.c | 163 +++++++++++++++++++++++++++++++ drivers/mmc/msm_sdhci.c | 13 ++- drivers/mmc/rockchip_dw_mmc.c | 6 +- drivers/mmc/uniphier-sd.c | 15 +-- drivers/reset/Kconfig | 23 +++++ drivers/reset/Makefile | 7 ++ drivers/reset/reset-uclass.c | 131 +++++++++++++++++++++++++ drivers/reset/sandbox-reset-test.c | 55 +++++++++++ drivers/reset/sandbox-reset.c | 108 +++++++++++++++++++++ drivers/serial/serial_msm.c | 13 ++- drivers/serial/serial_pic32.c | 7 +- drivers/serial/serial_s5p.c | 6 +- drivers/spi/rk_spi.c | 6 +- drivers/usb/host/ehci-generic.c | 14 +-- drivers/video/rockchip/rk_edp.c | 11 +-- drivers/video/rockchip/rk_hdmi.c | 12 +-- drivers/video/rockchip/rk_lvds.c | 1 - drivers/video/rockchip/rk_vop.c | 11 ++- include/clk-uclass.h | 95 ++++++++++++++++++ include/clk.h | 220 +++++++++++++++++++++++++----------------- include/dm/uclass-id.h | 1 + include/dt-bindings/mailbox/tegra-hsp.h | 14 +++ include/{mailbox_uclass.h => mailbox-uclass.h} | 4 +- include/{mailbox_client.h => mailbox.h} | 6 +- include/reset-uclass.h | 81 ++++++++++++++++ include/reset.h | 135 ++++++++++++++++++++++++++ lib/libfdt/Makefile | 12 ++- lib/libfdt/README | 16 +-- lib/libfdt/fdt.c | 2 +- lib/libfdt/fdt_addresses.c | 2 +- lib/libfdt/fdt_empty_tree.c | 3 +- lib/libfdt/fdt_region.c | 144 +++++++++++++-------------- lib/libfdt/fdt_ro.c | 10 +- lib/libfdt/fdt_rw.c | 6 +- lib/libfdt/fdt_strerror.c | 2 +- lib/libfdt/fdt_sw.c | 3 +- lib/libfdt/fdt_wip.c | 6 +- test/dm/Makefile | 1 + test/dm/clk.c | 110 ++++++++++++++------- test/dm/reset.c | 39 ++++++++ 77 files changed, 2028 insertions(+), 687 deletions(-) create mode 100644 arch/sandbox/include/asm/clk.h create mode 100644 arch/sandbox/include/asm/reset.h create mode 100644 doc/device-tree-bindings/reset/reset.txt create mode 100644 drivers/clk/clk_sandbox_test.c create mode 100644 drivers/mailbox/tegra-hsp.c create mode 100644 drivers/reset/Kconfig create mode 100644 drivers/reset/Makefile create mode 100644 drivers/reset/reset-uclass.c create mode 100644 drivers/reset/sandbox-reset-test.c create mode 100644 drivers/reset/sandbox-reset.c create mode 100644 include/clk-uclass.h create mode 100644 include/dt-bindings/mailbox/tegra-hsp.h rename include/{mailbox_uclass.h => mailbox-uclass.h} (96%) rename include/{mailbox_client.h => mailbox.h} (98%) create mode 100644 include/reset-uclass.h create mode 100644 include/reset.h create mode 100644 test/dm/reset.c Regards, Simon

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[U-Boot] Setting CONFIG_BOOTDELAY=2 for xilinx boards
by Masahiro Yamada 20 Jun '16

20 Jun '16

Hi Michal, I see CONFIG_BOOTDELAY=3 in the defconfigs you are maintaining. If it is no problem, can you drop "CONFIG_BOOTDELAY=3", please? I did so for my boards. Please see my patch: http://patchwork.ozlabs.org/patch/636878/ I have Zynq Zedboard, and I am quite sure CONFIG_BOOTDELAY=2 (, which is now the default of Kconfig) should work for it, but I think you have better access to other Xilinx boards (including Avnet boards with Xilinx SoC). Thanks. -- Best Regards Masahiro Yamada

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[U-Boot] [PATCH v3 0/7] spl: nand: sunxi: implement auto-detection
by Boris Brezillon 20 Jun '16

20 Jun '16

Hello, This patch series aims at adding support for NAND auto-detection to the sunxi SPL NAND driver. As explained in patch 7, this auto-detection is nothing more than a dumb "trial and error" logic, but it allows one to use the same SPL binary for all kind of sunxi boards booting from NAND. Of course, this approach might increase a bit the boot-time, but this is something we could address by adding a "default NAND config", that would be tested before launching the auto-detection procedure. Now let's detail a bit what's inside this patch-set. Patch 1 is a cleanup removing support for BootROM configs, which in my opinion are not only inefficient but also not reliable (at least the current implementation does not guarantee that you'll be using the correct configuration when reading the NAND). Piotr, Hans, any comment? Is this a real problem if we get rid of syndrome/BootROM configs? I mean, are you really using this mode? If that's not the case, I'd prefer dropping support for this feature. ITOH, if you really need this mode, then I'd recommend adding Kconfig options to specify the exact config to be used rather than randomly testing configs (see my explanation in patch 1). Patch 2 is reworking the SYS_NAND_U_BOOT_OFFS Kconfig dependency model to make it usable on all platforms (not only sunxi). Patch 3 is adding generic support for redundant u-boot images, which is particularly useful on modern NANDs where corruptions is likely to happen. Patch 4 is just getting rid of the open-coded version of redundant u-boot image support in the sunxi NAND driver. Patch 5 is a simple improvement of the NAND controller status polling loop, which is really important to make the "trial and error" approach efficient (we try to limit the impact on boot-time here). Patch 6 and 7 are implementing the auto-detection logic. Best Regards, Boris Changes since v2: - rework the Kconfig options for SYS_U_BOOT_OFFS and SYS_U_BOOT_REDUND_OFFS Changes since v1: - added Hans ack - fixed 2 typos in patch 7 Boris Brezillon (7): spl: nand: sunxi: remove support for so-called 'syndrome' mode spl: nand: rework SYS_NAND_U_BOOT_OFFS Kconfig option dependency spl: nand: support redundant u-boot image spl: nand: sunxi: stop guessing the redundant u-boot offset spl: nand: sunxi: rework status polling loop spl: nand: sunxi: split 'load page' and 'read page' logic spl: nand: sunxi: add support for NAND config auto-detection common/spl/spl_nand.c | 5 + drivers/mtd/nand/Kconfig | 21 +- drivers/mtd/nand/sunxi_nand_spl.c | 480 ++++++++++++++++++++++++-------------- 3 files changed, 332 insertions(+), 174 deletions(-) -- 2.7.4

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[U-Boot] [PATCH] fastboot: nand: fix compile error
by Peng Fan 20 Jun '16

20 Jun '16

Error info " common/fb_nand.c: In function 'fb_nand_lookup': common/fb_nand.c:65:3: error: 'mtd' undeclared (first use in this function) *mtd = nand_info[dev->id->num]; ^ " Correct fb_nand_lookup parameter name to fix this issue. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Maxime Ripard <maxime.ripard(a)free-electrons.com> Cc: Scott Wood <oss(a)buserror.net> Cc: Tom Rini <trini(a)konsulko.com> --- common/fb_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/fb_nand.c b/common/fb_nand.c index e55ea38..ae34f48 100644 --- a/common/fb_nand.c +++ b/common/fb_nand.c @@ -34,7 +34,7 @@ __weak int board_fastboot_write_partition_setup(char *name) } static int fb_nand_lookup(const char *partname, char *response, - struct mtd_info **nand, + struct mtd_info **mtd, struct part_info **part) { struct mtd_device *dev; -- 2.6.2

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[U-Boot] [PATCH 0/6] mtd fixes for u-boot-2016.07-rc1
by Ladislav Michl 20 Jun '16

20 Jun '16

This patch serie contains various bugfixes related to mtd found during converting igep00x0 to use UBI. All patches was sent previously as a part of RFCs, but as noone commented so far, I'm resending them separately. Former versions already sent was marked as "superseded" in patchwork. Best regards, ladis

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[U-Boot] [PATCH 0/5] LS2080ARDB: Enable EFI boot support
by Alexander Graf 20 Jun '16

20 Jun '16

We now have EFI support in U-Boot which worked out of the box on all systems that I tried it on so far. Except for the LS2080ARDB. With this patch set I can successfully boot grub2 and Linux from there on such a system - even using PXE. Alexander Graf (5): ls2080: Exit dpaa only right before exiting U-Boot ls2080: Disable dcache during ddr init efi_loader: AArch64: Run EFI payloads in EL2 if U-Boot runs in EL3 ls2080ardb: Reserve DP-DDR RAM ls2080ardb: Convert to distro boot arch/arm/include/asm/armv8/mmu.h | 19 ++++++++++++------- arch/arm/lib/bootm.c | 11 +++++++++++ board/freescale/ls2080a/ddr.c | 2 ++ board/freescale/ls2080a/ls2080a.c | 1 - board/freescale/ls2080aqds/ddr.c | 2 ++ board/freescale/ls2080aqds/ls2080aqds.c | 4 ---- board/freescale/ls2080ardb/ddr.c | 2 ++ board/freescale/ls2080ardb/ls2080ardb.c | 13 +++++++++---- cmd/bootefi.c | 11 +++++++++++ drivers/net/fsl-mc/mc.c | 22 ++++++++++++++++++++-- include/configs/ls2080ardb.h | 24 +++++++++++++++++++++++- lib/efi_loader/efi_boottime.c | 10 ++++++++++ 12 files changed, 102 insertions(+), 19 deletions(-) -- 1.8.5.6

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[U-Boot] [PATCH v5 1/2] powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL
by Sumit Garg 20 Jun '16

20 Jun '16

As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta(a)nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)nxp.com> Signed-off-by: Sumit Garg <sumit.garg(a)nxp.com> --- Changes in v2: Patches rebased Changes in v3: Patches rebased Changes in v4: Generic changes in lib, drivers, common Makefiles removed from this patchset. Rebased this patchset on top of patch [1], so this patchset is dependent on patch [1]. [1]https://patchwork.ozlabs.org/patch/627664/ Changes in v5: Check for def CONFIG_SPL_DM and ndef CONFIG_SPL_FRAMEWORK instead of def CONFIG_DM macro to include call to dm_init_and_scan(). As dm_init_and_scan() is called as part of common SPL framework, so no need to call it again but in case of powerpc platforms which currently do not use common SPL framework, so need to include this function call here. arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 8 +++++ arch/powerpc/cpu/mpc8xxx/pamu_table.c | 8 +++++ arch/powerpc/include/asm/fsl_secure_boot.h | 28 +++++++++++++++ board/freescale/common/fsl_chain_of_trust.c | 54 +++++++++++++++++++++++++++++ drivers/crypto/fsl/jr.c | 16 +++++++++ drivers/mtd/nand/fsl_ifc_spl.c | 24 +++++++++++++ include/fsl_validate.h | 1 + 7 files changed, 139 insertions(+) diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 9421f1e..ede8e66 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -239,15 +239,23 @@ int pamu_init(void) spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES; /* Allocate space for Primary PAACT Table */ +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_PPAACT_ADDR)) + ppaact = (void *)CONFIG_SPL_PPAACT_ADDR; +#else ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size); if (!ppaact) return -1; +#endif memset(ppaact, 0, ppaact_size); /* Allocate space for Secondary PAACT Table */ +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SPAACT_ADDR)) + sec = (void *)CONFIG_SPL_SPAACT_ADDR; +#else sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size); if (!sec) return -1; +#endif memset(sec, 0, spaact_size); ppaact_phys = virt_to_phys((void *)ppaact); diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index 26c5ea4..a8e6f51 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -28,6 +28,14 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) i++; #endif +#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR)) + tbl->start_addr[i] = + (uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR); + tbl->size[i] = 256 * 1024; /* 256K CPC flash */ + tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; + + i++; +#endif debug("PAMU address\t\t\tsize\n"); for (j = 0; j < i ; j++) debug("%llx \t\t\t%llx\n", tbl->start_addr[j], tbl->size[j]); diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 826f9c9..99eec7f 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -72,6 +72,32 @@ #ifdef CONFIG_CHAIN_OF_TRUST +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_DM 1 +#define CONFIG_SPL_CRYPTO_SUPPORT +#define CONFIG_SPL_HASH_SUPPORT +#define CONFIG_SPL_RSA +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +/* + * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init + * due to space crunch on CPC and thus malloc will not work. + */ +#define CONFIG_SPL_PPAACT_ADDR 0x2e000000 +#define CONFIG_SPL_SPAACT_ADDR 0x2f000000 +#define CONFIG_SPL_JR0_LIODN_S 454 +#define CONFIG_SPL_JR0_LIODN_NS 458 +/* + * Define the key hash for U-Boot here if public/private key pair used to + * sign U-boot are different from the SRK hash put in the fuse + * Example of defining KEY_HASH is + * #define CONFIG_SPL_UBOOT_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + * else leave it defined as NULL + */ + +#define CONFIG_SPL_UBOOT_KEY_HASH NULL +#endif /* ifdef CONFIG_SPL_BUILD */ + #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON @@ -82,6 +108,7 @@ #define CONFIG_FSL_CAAM #endif +#ifndef CONFIG_SPL_BUILD /* fsl_setenv_chain_of_trust() must be called from * board_late_init() */ @@ -119,5 +146,6 @@ #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ #include <config_fsl_chain_trust.h> +#endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index ecfcc82..7bf9827 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -6,7 +6,17 @@ #include <common.h> #include <fsl_validate.h> +#include <fsl_secboot_err.h> #include <fsl_sfp.h> +#include <dm/root.h> + +#ifdef CONFIG_ADDR_MAP +#include <asm/mmu.h> +#endif + +#ifdef CONFIG_FSL_CORENET +#include <asm/fsl_pamu.h> +#endif #ifdef CONFIG_LS102XA #include <asm/arch/immap_ls102xa.h> @@ -52,6 +62,7 @@ int fsl_check_boot_mode_secure(void) return 0; } +#ifndef CONFIG_SPL_BUILD int fsl_setenv_chain_of_trust(void) { /* Check Boot Mode @@ -68,3 +79,46 @@ int fsl_setenv_chain_of_trust(void) setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); return 0; } +#endif + +#ifdef CONFIG_SPL_BUILD +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) +{ + int res; + + /* Check Boot Mode + * If Boot Mode is Non-Secure, skip validation + */ + if (fsl_check_boot_mode_secure() == 0) + return; + + printf("SPL: Validating U-Boot image\n"); + +#ifdef CONFIG_ADDR_MAP + init_addr_map(); +#endif + +#ifdef CONFIG_FSL_CORENET + if (pamu_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#endif + +#ifdef CONFIG_FSL_CAAM + if (sec_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT); +#endif + +/* dm_init_and_scan is called as part of common SPL framework, so no + * need to call it again but in case of powerpc platforms which currently + * do not use common SPL framework, so need to call this function here. + */ +#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK)) + dm_init_and_scan(false); +#endif + res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH, + &img_addr); + + if (res == 0) + printf("SPL: Validation of U-boot successful\n"); +} +#endif /* ifdef CONFIG_SPL_BUILD */ diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 510fa4e..1d4dd32 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -599,10 +599,26 @@ int sec_init_idx(uint8_t sec_idx) sec_out32(&sec->mcfgr, mcr); #ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SPL_BUILD + /* For SPL Build, Set the Liodns in SEC JR0 for + * creating PAMU entries corresponding to these. + * For normal build, these are set in set_liodns(). + */ + liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK; + liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK; + + liodnr = sec_in32(&sec->jrliodnr[0].ls) & + ~(JRNSLIODN_MASK | JRSLIODN_MASK); + liodnr = liodnr | + (liodn_ns << JRNSLIODN_SHIFT) | + (liodn_s << JRSLIODN_SHIFT); + sec_out32(&sec->jrliodnr[0].ls, liodnr); +#else liodnr = sec_in32(&sec->jrliodnr[0].ls); liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT; liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; #endif +#endif ret = jr_init(sec_idx); if (ret < 0) { diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index cbeb74a..30aa966 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -11,6 +11,9 @@ #include <asm/io.h> #include <fsl_ifc.h> #include <linux/mtd/nand.h> +#ifdef CONFIG_CHAIN_OF_TRUST +#include <fsl_validate.h> +#endif static inline int is_blank(uchar *addr, int page_size) { @@ -268,6 +271,27 @@ void nand_boot(void) */ flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); #endif + +#ifdef CONFIG_CHAIN_OF_TRUST + /* + * As U-Boot header is appended at end of U-boot image, so + * calculate U-boot header address using U-boot header size. + */ +#define CONFIG_U_BOOT_HDR_ADDR \ + ((CONFIG_SYS_NAND_U_BOOT_START + \ + CONFIG_SYS_NAND_U_BOOT_SIZE) - \ + CONFIG_U_BOOT_HDR_SIZE) + spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR, + CONFIG_SYS_NAND_U_BOOT_START); + /* + * In case of failure in validation, spl_validate_uboot would + * not return back in case of Production environment with ITS=1. + * Thus U-Boot will not start. + * In Development environment (ITS=0 and SB_EN=1), the function + * may return back in case of non-fatal failures. + */ +#endif + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); } diff --git a/include/fsl_validate.h b/include/fsl_validate.h index a71e1ce..7695b30 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -254,4 +254,5 @@ int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, int fsl_check_boot_mode_secure(void); int fsl_setenv_chain_of_trust(void); +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); #endif -- 1.8.1.4

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[U-Boot] pull request: u-boot-uniphier/master
by Masahiro Yamada 20 Jun '16

20 Jun '16

Hi Tom, Please pull some more patches for UniPhier SoCs! The following changes since commit 9ab165d8b05706284de0ee9bd402346c54ae6b15: SPL ext: cosmetic: correct error message in spl_load_image_ext() (2016-06-19 09:57:48 -0400) are available in the git repository at: git://git.denx.de/u-boot-uniphier master for you to fetch changes up to 7c8ef0feb97586d35b0296b48903daef8c06ab21: ARM: uniphier: use the default CONFIG_BOOTDELAY=2 (2016-06-20 07:15:39 +0900) ---------------------------------------------------------------- Masahiro Yamada (5): ARM: uniphier: change CPU_RELEASE_ADDR to the head of DRAM space ARM: uniphier: introduce CONFIG_ARM_UNIPHIER_{32, 64}BIT ARM: uniphier: move CONFIG_ARMV8_MULTIENTRY to Kconfig ARM: uniphier: reserve memory for DRAM PHY training on PH1-LD20 ARM: uniphier: use the default CONFIG_BOOTDELAY=2 arch/arm/Kconfig | 1 + arch/arm/mach-uniphier/Kconfig | 25 ++++++++++++++-------- arch/arm/mach-uniphier/dram_init.c | 40 ++++++++++++++++++++++++++++++++++++ configs/uniphier_ld11_defconfig | 1 - configs/uniphier_ld20_defconfig | 1 - configs/uniphier_ld4_sld8_defconfig | 1 - configs/uniphier_pro4_defconfig | 1 - configs/uniphier_pxs2_ld6b_defconfig | 1 - configs/uniphier_sld3_defconfig | 1 - include/configs/uniphier.h | 3 +-- 10 files changed, 59 insertions(+), 16 deletions(-) -- Best Regards Masahiro Yamada

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[U-Boot] [PATCH v2] dm: atmel: Add driver model support for the ehci driver
by Wenyou Yang 20 Jun '16

20 Jun '16

Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Collect Acked-by tag. - Update the clk API based on [PATCH] clk: convert API to match reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/). drivers/usb/host/Kconfig | 7 +++ drivers/usb/host/ehci-atmel.c | 116 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 89580cc..b8dd18e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -60,6 +60,13 @@ config USB_EHCI if USB_EHCI_HCD +config USB_EHCI_ATMEL + bool "Support for Atmel on-chip EHCI USB controller" + depends on ARCH_AT91 + default y + ---help--- + Enables support for the on-chip EHCI controller on Atmel chips. + config USB_EHCI_MARVELL bool "Support for MVEBU (AXP / A38x) on-chip EHCI USB controller" depends on ARCH_MVEBU diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index 1d7d280..5d0e9ad 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -7,12 +7,18 @@ */ #include <common.h> +#include <clk_client.h> +#include <dm.h> #include <usb.h> #include <asm/io.h> #include <asm/arch/clk.h> #include "ehci.h" +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_USB + int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { @@ -41,3 +47,113 @@ int ehci_hcd_stop(int index) return 0; } + +#else + +struct ehci_atmel_priv { + struct ehci_ctrl ehci; +}; + +static int ehci_atmel_enable_clk(struct udevice *dev) +{ + struct udevice *dev_clk; + struct clk clk; + int periph; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 1, &clk); + if (ret) + return -EINVAL; + + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); + if (periph < 0) + return -EINVAL; + + dev_clk = dev_get_parent(clk.dev); + if (!dev_clk) + return -ENODEV; + + ret = clk_request(dev_clk, &clk); + if (ret) + return ret; + + clk.id = periph; + ret = clk_enable(&clk); + if (ret) + return ret; + + clk_free(&clk); + + return 0; +} + +static int ehci_atmel_probe(struct udevice *dev) +{ + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + fdt_addr_t hcd_base; + int ret; + + ret = ehci_atmel_enable_clk(dev); + if (ret) { + debug("Failed to enable USB Host clock\n"); + return ret; + } + + /* + * Get the base address for EHCI controller from the device node + */ + hcd_base = dev_get_addr(dev); + if (hcd_base == FDT_ADDR_T_NONE) { + debug("Can't get the EHCI register base address\n"); + return -ENXIO; + } + + hccr = (struct ehci_hccr *)hcd_base; + hcor = (struct ehci_hcor *) + ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + debug("echi-atmel: init hccr %x and hcor %x hc_length %d\n", + (u32)hccr, (u32)hcor, + (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); +} + +static int ehci_atmel_remove(struct udevice *dev) +{ + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "atmel,at91sam9g45-ehci", }, + { } +}; + +U_BOOT_DRIVER(ehci_atmel) = { + .name = "ehci_atmel", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .probe = ehci_atmel_probe, + .remove = ehci_atmel_remove, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ehci_atmel_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +#endif -- 2.7.4

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[U-Boot] [PATCH v4] dm: at91: Add driver model support for the spi driver
by Wenyou Yang 20 Jun '16

20 Jun '16

Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v4: - Collect Reviewed-by tag. - Update the clk API based on [PATCH] clk: convert API to match reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/). - Remove check on dev_get_parent() return. - Fixed the return value, -ENODEV->-EINVAL. - Retain #include <asm/arch/clk.h> line. Changes in v3: - Remove redundant log print. Changes in v2: - Add clock support. drivers/spi/Kconfig | 9 ++ drivers/spi/atmel_spi.c | 303 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 312 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index b7fd8e5..2ac145c 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -32,6 +32,15 @@ config ATH79_SPI uses driver model and requires a device tree binding to operate. please refer to doc/device-tree-bindings/spi/spi-ath79.txt. +config ATMEL_SPI + bool "Atmel SPI driver" + depends on ARCH_AT91 + select SPI_FLASH + select SPI_FLASH_ATMEL + help + Enable the Atmel SPI driver. This driver can be used to access + the SPI Flash, such as AT25DF321. + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index ed6278b..b7f1aa6 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -4,6 +4,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <clk_client.h> +#include <dm.h> +#include <fdtdec.h> #include <spi.h> #include <malloc.h> @@ -11,9 +14,15 @@ #include <asm/arch/clk.h> #include <asm/arch/hardware.h> +#include <asm/arch/at91_spi.h> +#include <asm/gpio.h> #include "atmel_spi.h" +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_SPI + static int spi_has_wdrbt(struct atmel_spi_slave *slave) { unsigned int ver; @@ -209,3 +218,297 @@ out: return 0; } + +#else + +#define MAX_CS_COUNT 4 + +struct atmel_spi_platdata { + struct at91_spi *regs; +}; + +struct atmel_spi_priv { + unsigned int freq; /* Default frequency */ + unsigned int mode; + ulong bus_clk_rate; + struct gpio_desc cs_gpios[MAX_CS_COUNT]; +}; + +static int atmel_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); + struct atmel_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct at91_spi *reg_base = bus_plat->regs; + u32 cs = slave_plat->cs; + u32 freq = priv->freq; + u32 scbr, csrx, mode; + + scbr = (priv->bus_clk_rate + freq - 1) / freq; + if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) + return -EINVAL; + + if (scbr < 1) + scbr = 1; + + csrx = ATMEL_SPI_CSRx_SCBR(scbr); + csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); + + if (!(priv->mode & SPI_CPHA)) + csrx |= ATMEL_SPI_CSRx_NCPHA; + if (priv->mode & SPI_CPOL) + csrx |= ATMEL_SPI_CSRx_CPOL; + + writel(csrx, &reg_base->csr[cs]); + + mode = ATMEL_SPI_MR_MSTR | + ATMEL_SPI_MR_MODFDIS | + ATMEL_SPI_MR_WDRBT | + ATMEL_SPI_MR_PCS(~(1 << cs)); + + writel(mode, &reg_base->mr); + + writel(ATMEL_SPI_CR_SPIEN, &reg_base->cr); + + return 0; +} + +static int atmel_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); + + writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr); + + return 0; +} + +static void atmel_spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + u32 cs = slave_plat->cs; + + dm_gpio_set_value(&priv->cs_gpios[cs], 0); +} + +static void atmel_spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + u32 cs = slave_plat->cs; + + dm_gpio_set_value(&priv->cs_gpios[cs], 1); +} + +static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); + struct at91_spi *reg_base = bus_plat->regs; + + u32 len_tx, len_rx, len; + u32 status; + const u8 *txp = dout; + u8 *rxp = din; + u8 value; + + if (bitlen == 0) + goto out; + + /* + * The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + /* + * The controller can do automatic CS control, but it is + * somewhat quirky, and it doesn't really buy us much anyway + * in the context of U-Boot. + */ + if (flags & SPI_XFER_BEGIN) { + atmel_spi_cs_activate(dev); + + /* + * sometimes the RDR is not empty when we get here, + * in theory that should not happen, but it DOES happen. + * Read it here to be on the safe side. + * That also clears the OVRES flag. Required if the + * following loop exits due to OVRES! + */ + readl(&reg_base->rdr); + } + + for (len_tx = 0, len_rx = 0; len_rx < len; ) { + status = readl(&reg_base->sr); + + if (status & ATMEL_SPI_SR_OVRES) + return -1; + + if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) { + if (txp) + value = *txp++; + else + value = 0; + writel(value, &reg_base->tdr); + len_tx++; + } + + if (status & ATMEL_SPI_SR_RDRF) { + value = readl(&reg_base->rdr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) { + /* + * Wait until the transfer is completely done before + * we deactivate CS. + */ + do { + status = readl(&reg_base->sr); + } while (!(status & ATMEL_SPI_SR_TXEMPTY)); + + atmel_spi_cs_deactivate(dev); + } + + return 0; +} + +static int atmel_spi_set_speed(struct udevice *bus, uint speed) +{ + struct atmel_spi_priv *priv = dev_get_priv(bus); + + priv->freq = speed; + + return 0; +} + +static int atmel_spi_set_mode(struct udevice *bus, uint mode) +{ + struct atmel_spi_priv *priv = dev_get_priv(bus); + + priv->mode = mode; + + return 0; +} + +static const struct dm_spi_ops atmel_spi_ops = { + .claim_bus = atmel_spi_claim_bus, + .release_bus = atmel_spi_release_bus, + .xfer = atmel_spi_xfer, + .set_speed = atmel_spi_set_speed, + .set_mode = atmel_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static int atmel_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct atmel_spi_priv *priv = dev_get_priv(bus); + int ret; + + ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios, + ARRAY_SIZE(priv->cs_gpios), 0); + if (ret < 0) { + error("Can't get %s gpios! Error: %d", bus->name, ret); + return ret; + } + + return 0; +} + +static int atmel_spi_enable_clk(struct udevice *bus) +{ + struct atmel_spi_priv *priv = dev_get_priv(bus); + struct udevice *dev_clk; + struct clk clk; + ulong clk_rate; + int periph; + int ret; + + ret = clk_get_by_index(bus, 0, &clk); + if (ret) + return -EINVAL; + + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); + if (periph < 0) + return -EINVAL; + + dev_clk = dev_get_parent(clk.dev); + ret = clk_request(dev_clk, &clk); + if (ret) + return ret; + + clk.id = periph; + ret = clk_enable(&clk); + if (ret) + return ret; + + ret = clk_get_by_index(dev_clk, 0, &clk); + if (ret) + return ret; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) + return -EINVAL; + + priv->bus_clk_rate = clk_rate; + + clk_free(&clk); + + return 0; +} + +static int atmel_spi_probe(struct udevice *bus) +{ + struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); + int ret; + + ret = atmel_spi_enable_clk(bus); + if (ret) + return ret; + + bus_plat->regs = (struct at91_spi *)dev_get_addr(bus); + + writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr); + + return 0; +} + +static const struct udevice_id atmel_spi_ids[] = { + { .compatible = "atmel,at91rm9200-spi" }, + { } +}; + +U_BOOT_DRIVER(atmel_spi) = { + .name = "atmel_spi", + .id = UCLASS_SPI, + .of_match = atmel_spi_ids, + .ops = &atmel_spi_ops, + .ofdata_to_platdata = atmel_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata), + .priv_auto_alloc_size = sizeof(struct atmel_spi_priv), + .probe = atmel_spi_probe, +}; +#endif -- 2.7.4

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