May 2016 - U-Boot

[U-Boot] [PATCH] armv8: ls2080a: update eth prime
by Prabhakar Kushwaha 24 May '16

24 May '16

As per new PHY framework, DPNI naming convetion is no more used. Use new naming convention. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- include/configs/ls2080aqds.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 91fad0a..b6a4796 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -381,7 +381,7 @@ unsigned long get_board_ddr_clk(void); #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "DPNI1" +#define CONFIG_ETHPRIME "DPMAC1@xgmii" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 15a1172..0c97315 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -374,7 +374,7 @@ unsigned long get_board_sys_clk(void); #define AQR405_IRQ_MASK 0x36 #define CONFIG_MII -#define CONFIG_ETHPRIME "DPNI1" +#define CONFIG_ETHPRIME "DPMAC1@xgmii" #define CONFIG_PHY_GIGE #define CONFIG_PHY_AQUANTIA #endif -- 1.9.1

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[U-Boot] [PATCH] armv8: ls2080: enable sec_init in U-Boot
by Aneesh Bansal 24 May '16

24 May '16

Define CONFIG_FSL_CAAM for LS2080 which would enable call to sec_init() during U-Boot. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)nxp.com> --- include/configs/ls2080a_common.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 13ce349..4150e17 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -28,6 +28,8 @@ /* We need architecture specific misc initializations */ #define CONFIG_ARCH_MISC_INIT +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* Link Definitions */ #ifdef CONFIG_SPL #define CONFIG_SYS_TEXT_BASE 0x80400000 @@ -307,5 +309,10 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif #endif /* __LS2_COMMON_H */ -- 1.8.1.4

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[U-Boot] [PATCH] armv8/fdt: add fixup_crypto_node
by Alex Porosanu 24 May '16

24 May '16

For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in order to update the SEC internal version (aka SEC ERA). This patch adds the same functionality to the ARMv8 SoCs. Signed-off-by: Alex Porosanu <alexandru.porosanu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 1e875c4..d17227a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -20,6 +20,8 @@ #ifdef CONFIG_MP #include <asm/arch/mp.h> #endif +#include <fsl_sec.h> +#include <asm/arch-fsl-layerscape/soc.h> int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -75,6 +77,23 @@ void ft_fixup_cpu(void *blob) void ft_cpu_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FSL_LSCH2 + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr = in_be32(&gur->svr); + + /* delete crypto node if not on an E-processor */ + if (!IS_E_PROCESSOR(svr)) + fdt_fixup_crypto_node(blob, 0); +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 + else { + ccsr_sec_t __iomem *sec; + + sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); + } +#endif +#endif + #ifdef CONFIG_MP ft_fixup_cpu(blob); #endif -- 1.9.3

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[U-Boot] [PATCH] armv8: ls2080a: Update MAINTAINERS file
by Prabhakar Kushwaha 24 May '16

24 May '16

Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- board/freescale/ls2080aqds/MAINTAINERS | 2 +- board/freescale/ls2080ardb/MAINTAINERS | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 558cef1..853a69d 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -1,5 +1,5 @@ LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar(a)freescale.com> +M: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> S: Maintained F: board/freescale/ls2080aqds/ F: board/freescale/ls2080a/ls2080aqds.c diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index 0817711d..b9afc79 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -1,5 +1,5 @@ LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar(a)freescale.com> +M: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> S: Maintained F: board/freescale/ls2080ardb/ F: board/freescale/ls2080a/ls2080ardb.c -- 1.9.1

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[U-Boot] [PATCH v2] armv8/ls1043: Add workaround for DDR erratum A-008850
by Shengzhou Liu 24 May '16

24 May '16

Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- v2: moved part 2 of 2 to public soc.c arch/arm/cpu/armv8/fsl-layerscape/soc.c | 36 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + board/freescale/ls1043aqds/ddr.c | 1 + board/freescale/ls1043aqds/ddr.h | 2 ++ board/freescale/ls1043aqds/ls1043aqds.c | 8 ----- board/freescale/ls1043ardb/ddr.c | 2 ++ board/freescale/ls1043ardb/ddr.h | 3 ++ board/freescale/ls1043ardb/ls1043ardb.c | 8 ----- include/fsl_ddr_sdram.h | 4 +++ 9 files changed, 49 insertions(+), 16 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0cb0100..0fb5c7f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -12,6 +12,8 @@ #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr.h> #ifdef CONFIG_CHAIN_OF_TRUST #include <fsl_validate.h> #endif @@ -271,6 +273,39 @@ static void erratum_a009660(void) #endif } +static void erratum_a008850_early(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 1 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + + /* disables propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + /* disable the re-ordering in DDRC */ + ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); +#endif +} + +void erratum_a008850_post(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 2 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + u32 tmp; + + /* enable propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + /* enable the re-ordering in DDRC */ + tmp = ddr_in32(&ddr->eor); + tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); + ddr_out32(&ddr->eor, tmp); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -295,6 +330,7 @@ void fsl_lsch2_early_init_f(void) CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); /* Erratum */ + erratum_a008850_early(); /* part 1 of 2 */ erratum_a009929(); erratum_a009660(); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2..a24dc28 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -191,6 +191,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 #define CONFIG_SYS_FSL_ERRATUM_A009942 diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 3d3c533..0fd835d 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -116,6 +116,7 @@ phys_size_t initdram(int board_type) dram_size = fsl_ddr_sdram(); #endif + erratum_a008850_post(); #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h index 8adb660..d3f4082 100644 --- a/board/freescale/ls1043aqds/ddr.h +++ b/board/freescale/ls1043aqds/ddr.h @@ -7,6 +7,8 @@ #ifndef __DDR_H__ #define __DDR_H__ +extern void erratum_a008850_post(void); + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index fba6b88..fc097d9 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -307,14 +307,6 @@ int misc_init_r(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *) - CONFIG_SYS_CCI400_ADDR; - - /* Set CCI-400 control override register to enable barrier - * transaction */ - out_le32(&cci->ctrl_ord, - CCI400_CTRLORD_EN_BARRIER); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_retimer_init(); diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 11bc0f2..1e2fd2e 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -177,6 +177,8 @@ phys_size_t initdram(int board_type) #else dram_size = fsl_ddr_sdram_size(); #endif + erratum_a008850_post(); + #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); #endif diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h index b17eb80..8ca166b 100644 --- a/board/freescale/ls1043ardb/ddr.h +++ b/board/freescale/ls1043ardb/ddr.h @@ -6,6 +6,9 @@ #ifndef __DDR_H__ #define __DDR_H__ + +extern void erratum_a008850_post(void); + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index ec5fdbf..8d80135 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -83,14 +83,6 @@ int board_early_init_f(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - - /* - * Set CCI-400 control override register to enable barrier - * transaction - */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - #ifdef CONFIG_FSL_IFC init_final_memctl_regs(); #endif diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index cf316a4..44ae7fb 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -146,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define WR_DATA_DELAY_SHIFT 10 #endif +/* DDR_EOR register */ +#define DDR_EOR_RD_REOD_DIS 0x07000000 +#define DDR_EOR_WD_REOD_DIS 0x00100000 + /* DDR_MD_CNTL */ #define MD_CNTL_MD_EN 0x80000000 #define MD_CNTL_CS_SEL_CS0 0x00000000 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] driver/ddr/fsl: Force enabling parity for A-009803
by Shengzhou Liu 24 May '16

24 May '16

Default address parity is disabled for DDR4 UDIMM for considing performance, it needs to enable parity for A-009803 workaround. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- drivers/ddr/fsl/options.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index d0075ff..dcef0bb 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -1016,6 +1016,9 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, } } +#ifdef CONFIG_SYS_FSL_ERRATUM_A009803 + popts->ap_en = 1; +#endif /* * BSTTOPRE precharge interval * -- 2.1.0.27.g96db324

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[U-Boot] [GIT PULL v2] Xilinx changes
by Michal Simek 24 May '16

24 May '16

Hi Tom, here are patches I have collected. I expect some others changes will come after that. I have fixed one MB compilation issue in v2 (just missing one variable). Sorry for that. Thanks, Michal The following changes since commit d7d000311285e4b8d11e089ca13ea456a01be3b8: Merge branch 'master' of git://git.denx.de/u-boot-mips (2016-05-23 11:51:37 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master for you to fetch changes up to ad5b5801264e573bfbf17a20b04c546985c5bfc1: ARM: zynq: Simplify zynq configuration (2016-05-24 13:22:50 +0200) ---------------------------------------------------------------- Alexander Graf (1): ARM64: zynqmp: Align gic ranges for 64k in device tree Masahiro Yamada (2): ARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined or not ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-bus Michal Simek (27): gpio: zynq: Add support for reading gpio pin state ARM64: zynqmp: Enable HUSH parser for all zynqmp targets ARM64: zynqmp: Enable missing distro default options ARM64: zynqmp: Add support for reading MAC from eeprom ARM64: zynqmp: Enable eMMC boot partitions commands ARM64: zynqmp: Wire up debug_uart setup ARM: zynq: Add support for SPL_LOAD_FIT ARM64: zynqmp: Remove CONFIG_PREBOOT ARM64: zynqmp: Enable SPI_FLASH and FLASH_BAR for ep108 ARM64: zynqmp: Add debug uart for zc1751-dc1 spl: Introduce new function spl_board_prepare_for_boot ARM64: zynqmp: Enable option to overwrite default variables ARM: zynq: Call ps7_post_config() for SPL SPL: FIT: Enable SPL_FIT_LOAD in RAM based boot mode tools: zynqmpimage: Add Xilinx ZynqMP boot header generation ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSI ARM64: zynqmp: Add SPL support support ARM64: zynqmp: Enable CLK framework fpga: Fix typo in function comment mkimage: Report information about fpga net: xilinx: Handle error value from phy_startup() phy: Return correct error code when timeout happens net: phy: Handle phy_startup() error codes properly image: Add boot_get_fpga() to load fpga with bootm phy: Wire return value from phy_config() phy: marvell: Do not reset phy after negotiation ARM: zynq: Simplify zynq configuration arch/arm/Kconfig | 1 + arch/arm/cpu/armv8/zynqmp/Makefile | 1 + arch/arm/cpu/armv8/zynqmp/spl.c | 107 +++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/zynq-7000.dtsi | 2 +- arch/arm/dts/zynqmp.dtsi | 9 ++++- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 + arch/arm/mach-zynq/Kconfig | 48 +++--------------------- arch/arm/mach-zynq/spl.c | 25 +++++++++++++ board/xilinx/zynq/Makefile | 12 +----- board/xilinx/zynq/custom_hw_platform/.gitignore | 1 - board/xilinx/zynq/{MicroZed_hw_platform => zynq-microzed}/ps7_init_gpl.c | 0 board/xilinx/zynq/{MicroZed_hw_platform => zynq-microzed}/ps7_init_gpl.h | 0 board/xilinx/zynq/{ZC702_hw_platform => zynq-zc702}/ps7_init_gpl.c | 0 board/xilinx/zynq/{ZC702_hw_platform => zynq-zc702}/ps7_init_gpl.h | 0 board/xilinx/zynq/{ZC706_hw_platform => zynq-zc706}/ps7_init_gpl.c | 0 board/xilinx/zynq/{ZC706_hw_platform => zynq-zc706}/ps7_init_gpl.h | 0 board/xilinx/zynq/{zed_hw_platform => zynq-zed}/ps7_init_gpl.c | 0 board/xilinx/zynq/{zed_hw_platform => zynq-zed}/ps7_init_gpl.h | 0 board/xilinx/zynq/{zybo_hw_platform => zynq-zybo}/ps7_init_gpl.c | 0 board/xilinx/zynq/{zybo_hw_platform => zynq-zybo}/ps7_init_gpl.h | 0 board/xilinx/zynqmp/Makefile | 23 +++++++++++- board/xilinx/zynqmp/xil_io.h | 35 ++++++++++++++++++ board/xilinx/zynqmp/zynqmp.c | 17 +++++++++ common/bootm.c | 10 +++++ common/image-fit.c | 11 +++++- common/image.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++ common/spl/spl.c | 51 ++++++++++++++++++++----- configs/xilinx_zynqmp_ep_defconfig | 9 +++++ configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 8 ++++ configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 3 ++ configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 3 ++ configs/xilinx_zynqmp_zcu102_defconfig | 8 ++++ configs/xilinx_zynqmp_zcu102_revB_defconfig | 8 ++++ configs/zynq_microzed_defconfig | 2 +- configs/zynq_picozed_defconfig | 2 +- configs/zynq_zc702_defconfig | 1 + configs/zynq_zc706_defconfig | 2 +- configs/zynq_zc770_xm010_defconfig | 2 +- configs/zynq_zc770_xm011_defconfig | 2 +- configs/zynq_zc770_xm012_defconfig | 2 +- configs/zynq_zc770_xm013_defconfig | 2 +- configs/zynq_zed_defconfig | 2 +- configs/zynq_zybo_defconfig | 2 +- doc/uImage.FIT/multi-with-fpga.its | 67 +++++++++++++++++++++++++++++++++ doc/uImage.FIT/source_file_format.txt | 3 ++ drivers/fpga/fpga.c | 2 +- drivers/gpio/zynq_gpio.c | 22 +++++++++++ drivers/net/phy/broadcom.c | 34 +++++++++++------ drivers/net/phy/davicom.c | 9 +++-- drivers/net/phy/et1011c.c | 10 +++-- drivers/net/phy/lxt.c | 9 +++-- drivers/net/phy/marvell.c | 39 ++++++++++--------- drivers/net/phy/micrel.c | 7 +++- drivers/net/phy/natsemi.c | 18 ++++++--- drivers/net/phy/phy.c | 15 ++++---- drivers/net/phy/realtek.c | 28 +++++++++----- drivers/net/phy/smsc.c | 10 +++-- drivers/net/phy/vitesse.c | 8 ++-- drivers/net/xilinx_emaclite.c | 6 ++- drivers/net/zynq_gem.c | 8 ++-- include/bootstage.h | 1 + include/configs/xilinx_zynqmp.h | 59 ++++++++++++++++++++++++++++- include/configs/xilinx_zynqmp_zcu102.h | 6 +++ include/configs/zynq-common.h | 6 +-- include/image.h | 7 +++- include/spl.h | 1 + scripts/Makefile.spl | 7 ++++ tools/Makefile | 1 + tools/zynqmpimage.c | 269 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 69 files changed, 1000 insertions(+), 159 deletions(-) create mode 100644 arch/arm/cpu/armv8/zynqmp/spl.c delete mode 100644 board/xilinx/zynq/custom_hw_platform/.gitignore rename board/xilinx/zynq/{MicroZed_hw_platform => zynq-microzed}/ps7_init_gpl.c (100%) rename board/xilinx/zynq/{MicroZed_hw_platform => zynq-microzed}/ps7_init_gpl.h (100%) rename board/xilinx/zynq/{ZC702_hw_platform => zynq-zc702}/ps7_init_gpl.c (100%) rename board/xilinx/zynq/{ZC702_hw_platform => zynq-zc702}/ps7_init_gpl.h (100%) rename board/xilinx/zynq/{ZC706_hw_platform => zynq-zc706}/ps7_init_gpl.c (100%) rename board/xilinx/zynq/{ZC706_hw_platform => zynq-zc706}/ps7_init_gpl.h (100%) rename board/xilinx/zynq/{zed_hw_platform => zynq-zed}/ps7_init_gpl.c (100%) rename board/xilinx/zynq/{zed_hw_platform => zynq-zed}/ps7_init_gpl.h (100%) rename board/xilinx/zynq/{zybo_hw_platform => zynq-zybo}/ps7_init_gpl.c (100%) rename board/xilinx/zynq/{zybo_hw_platform => zynq-zybo}/ps7_init_gpl.h (100%) create mode 100644 board/xilinx/zynqmp/xil_io.h create mode 100644 doc/uImage.FIT/multi-with-fpga.its create mode 100644 tools/zynqmpimage.c --- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] [PULL] u-boot-atmel/master -> u-boot/master
by Andreas Bießmann 24 May '16

24 May '16

Hi Tom, this is a resend of the pull request send late in release cycle for 2016.05. The following changes since commit d7d000311285e4b8d11e089ca13ea456a01be3b8: Merge branch 'master' of git://git.denx.de/u-boot-mips (2016-05-23 11:51:37 -0400) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to bb0c63a5f3b05770e8cb6171be57ca69995bd447: ARM: sama5d2: Implement boot device autodetection (2016-05-24 08:08:37 +0200) ---------------------------------------------------------------- Marek Vasut (2): ARM: atmel: Enable FIT image support for SAMA5Dx ARM: sama5d2: Implement boot device autodetection Wenyou Yang (6): ARM: at91: sama5d2: add macro & field definitions board: atmel: add SAMA5D2 PTC Engineering board board: atmel: sama5d2_xplained: fix the missing pin config of SDMMC0 ARM: at91: clock: fix the GCK's clock source ARM: at91: clock: complete the GCK's clock sources board: sama5d2_xplained: change SDHCI GCK's clock source to UPLL arch/arm/mach-at91/Kconfig | 6 + arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/armv7/clock.c | 11 + arch/arm/mach-at91/bootparams_atmel.S | 18 ++ arch/arm/mach-at91/include/mach/clk.h | 2 + arch/arm/mach-at91/include/mach/sama5_sfr.h | 24 ++ arch/arm/mach-at91/include/mach/sama5d2.h | 17 ++ arch/arm/mach-at91/spl.c | 36 +++ board/atmel/sama5d2_ptc/Kconfig | 15 ++ board/atmel/sama5d2_ptc/MAINTAINERS | 7 + board/atmel/sama5d2_ptc/Makefile | 8 + board/atmel/sama5d2_ptc/sama5d2_ptc.c | 285 ++++++++++++++++++++++++ board/atmel/sama5d2_xplained/sama5d2_xplained.c | 5 +- configs/sama5d2_ptc_nandflash_defconfig | 12 + configs/sama5d2_ptc_spiflash_defconfig | 12 + configs/sama5d2_xplained_mmc_defconfig | 1 + configs/sama5d2_xplained_spiflash_defconfig | 1 + configs/sama5d3_xplained_mmc_defconfig | 1 + configs/sama5d3_xplained_nandflash_defconfig | 1 + configs/sama5d3xek_mmc_defconfig | 1 + configs/sama5d3xek_nandflash_defconfig | 1 + configs/sama5d3xek_spiflash_defconfig | 1 + configs/sama5d4_xplained_mmc_defconfig | 1 + configs/sama5d4_xplained_nandflash_defconfig | 1 + configs/sama5d4_xplained_spiflash_defconfig | 1 + configs/sama5d4ek_mmc_defconfig | 1 + configs/sama5d4ek_nandflash_defconfig | 1 + configs/sama5d4ek_spiflash_defconfig | 1 + include/configs/sama5d2_ptc.h | 155 +++++++++++++ 29 files changed, 625 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-at91/bootparams_atmel.S create mode 100644 board/atmel/sama5d2_ptc/Kconfig create mode 100644 board/atmel/sama5d2_ptc/MAINTAINERS create mode 100644 board/atmel/sama5d2_ptc/Makefile create mode 100644 board/atmel/sama5d2_ptc/sama5d2_ptc.c create mode 100644 configs/sama5d2_ptc_nandflash_defconfig create mode 100644 configs/sama5d2_ptc_spiflash_defconfig create mode 100644 include/configs/sama5d2_ptc.h

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[U-Boot] Please pull u-boot-x86
by Bin Meng 24 May '16

24 May '16

Hi Tom, This introduces U-Boot ACPI support on Intel BayTrail platform with Ubuntu/Windows installation and boot support, QEMU fw_cfg interface codes refactoring to be used on other platforms, as well as some bug fixes and updates to Intel Quark support. The following changes since commit 4b6e1fda107e5244e80ebc41865650ac2873dc88: Merge git://git.denx.de/u-boot-dm (2016-05-17 13:58:27 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git master for you to fetch changes up to 8216b11cdd50515fbc423a4b2709a00865b8621d: x86: galileo: Override SMBIOS product name (2016-05-23 15:27:43 +0800) ---------------------------------------------------------------- Bin Meng (61): x86: Drop asm/acpi.h x86: Fix build warning in tables.c when CONFIG_SEABIOS x86: acpi: Fix compiler warnings in write_acpi_tables() x86: irq: Reserve IRQ9 for ACPI in PIC mode x86: irq: Enable SCI on IRQ9 x86: dts: Update to include ACTL register details acpi: Change build log for ASL files acpi: Explicitly spell out dsdt.c in the make rule acpi: Specify U-Boot include path for ASL files acpi: Output all errors/warnings/remarks when compiling ASL x86: acpi: Remove unused codes x86: acpi: Various changes to acpi_table.h x86: acpi: Reorder code in acpi_table.h x86: acpi: Remove acpi_create_ssdt_generator() x86: acpi: Change fill_header() x86: acpi: Adjust order in acpi_table.c x86: acpi: Use u32 in table write routines x86: acpi: Align FACS table to a 64 byte boundary x86: acpi: Clean up table header revisions x86: acpi: Add some generic ASL libraries x86: acpi: Return table length in acpi_create_madt_lapics() x86: baytrail: Add platform ASL files x86: baytrail: Generate ACPI FADT/MADT tables x86: baytrail: Enable ACPI table generation for all boards x86: baytrail: Add .gitignore for ACPI enabled boards x86: Remove acpi=off boot parameter when ACPI is on x86: doc: Minor update for accuracy x86: doc: Document ACPI support x86: minnowmax: Adjust U-Boot environment address in SPI flash x86: Call board_final_cleanup() in last_stage_init() x86: Fix up PIRQ routing table checksum earlier x86: Compile coreboot_table.c only for SeaBIOS x86: Prepare configuration tables in dedicated high memory region x86: Unify reserve_arch() for all x86 boards x86: Reserve configuration tables in high memory x86: Use high_table_malloc() for tables passing to SeaBIOS x86: acpi: Switch to ACPI mode by ourselves instead of requested by OSPM x86: acpi: Remove the unnecessary checksum calculation of DSDT x86: acpi: Remove header length check when writing tables x86: doc: Update information about IGD with SeaBIOS x86: baytrail: Enable SeaBIOS on all boards x86: doc: Mention Ubuntu/Windows installation and boot support acpi: Quieten IASL output when 'make -s' is used x86: baytrail: Add internal UART ASL description x86: baytrail: Add GPIO ASL description x86: doc: Add porting hints for ACPI with Windows acpi: Clean IASL generated intermediate files x86: crownbay: Disable boot stage support x86: Add some notes for MRC cache with Intel FSP x86: baytrail: Update to latest microcode x86: Use latest microcode for all BayTrail boards x86: galileo: Enable CPU driver x86: Don't touch IA32_APIC_BASE MSR on Intel Quark x86: Remove SMP limitation in lapic_setup() x86: Call lapic_setup() in interrupt_init() x86: quark: Assign a unique I/O APIC ID x86: broadwell: Correct I/O APIC ID x86: galileo: Enable MP table generation x86: kconfig: Add two options for SMBIOS manufacturer and product name x86: Switch to use SMBIOS Kconfig options when writing SMBIOS tables x86: galileo: Override SMBIOS product name Miao Yan (13): x86: qemu: fix ACPI Kconfig options cmd: qfw: add API to iterate firmware list cmd: qfw: remove qemu_fwcfg_free_files() cmd: qfw: make fwcfg_present and fwcfg_dma_present public x86: qemu: split qfw command interface and qfw core x86: qemu: move x86 specific operations out of qfw core x86: qemu: add comment about qfw register endianness cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h] cmd: qfw: do not require default macros when building qfw command cmd: qfw: do not depend on x86 cmd: qfw: bring ACPI generation code into qfw core x86: qemu: rename qemu/acpi_table.c config: sandbox: enable qfw and cmd_qfw for testing Tom Rini (1): x86: qemu: Move qfw command over to cmd and add Kconfig entry Makefile | 1 + arch/x86/Kconfig | 47 +- arch/x86/cpu/baytrail/Makefile | 1 + arch/x86/cpu/baytrail/acpi.c | 163 ++++ arch/x86/cpu/baytrail/valleyview.c | 8 - arch/x86/cpu/broadwell/pch.c | 3 +- arch/x86/cpu/broadwell/sdram.c | 5 - arch/x86/cpu/coreboot/coreboot.c | 20 +- arch/x86/cpu/cpu.c | 27 + arch/x86/cpu/interrupts.c | 8 +- arch/x86/cpu/irq.c | 31 + arch/x86/cpu/ivybridge/lpc.c | 1 - arch/x86/cpu/ivybridge/model_206ax.c | 3 - arch/x86/cpu/ivybridge/northbridge.c | 1 - arch/x86/cpu/ivybridge/sdram.c | 5 - arch/x86/cpu/lapic.c | 35 +- arch/x86/cpu/mp_init.c | 8 +- arch/x86/cpu/qemu/Makefile | 3 +- arch/x86/cpu/qemu/cpu.c | 2 +- arch/x86/cpu/qemu/e820.c | 43 + arch/x86/cpu/qemu/qemu.c | 50 +- arch/x86/cpu/quark/quark.c | 13 +- arch/x86/dts/bayleybay.dts | 5 +- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 5 +- arch/x86/dts/crownbay.dts | 1 + arch/x86/dts/galileo.dts | 13 + arch/x86/dts/microcode/m0130673322.dtsi | 3284 ---------------------------------------------------------------------- arch/x86/dts/microcode/m0130673325.dtsi | 3284 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/x86/dts/microcode/m0130679901.dtsi | 3284 ---------------------------------------------------------------------- arch/x86/dts/microcode/m0130679907.dtsi | 3284 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/x86/dts/minnowmax.dts | 5 +- arch/x86/dts/qemu-x86_q35.dts | 2 + arch/x86/include/asm/acpi.h | 24 - arch/x86/include/asm/acpi/debug.asl | 136 +++ arch/x86/include/asm/acpi/globutil.asl | 113 +++ arch/x86/include/asm/acpi/statdef.asl | 82 ++ arch/x86/include/asm/acpi_table.h | 446 ++++------ arch/x86/include/asm/arch-baytrail/acpi/gpio.asl | 95 ++ arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h | 111 +++ arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl | 493 +++++++++++ arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl | 48 ++ arch/x86/include/asm/arch-baytrail/acpi/irqroute.h | 27 + arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 181 ++++ arch/x86/include/asm/arch-baytrail/acpi/platform.asl | 36 + arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl | 13 + arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl | 211 +++++ arch/x86/include/asm/arch-baytrail/acpi/usb.asl | 34 + arch/x86/include/asm/arch-baytrail/acpi/xhci.asl | 31 + arch/x86/include/asm/arch-baytrail/device.h | 74 ++ arch/x86/include/asm/arch-baytrail/iomap.h | 70 ++ arch/x86/include/asm/arch-baytrail/irq.h | 86 ++ arch/x86/include/asm/coreboot_tables.h | 19 + arch/x86/include/asm/global_data.h | 4 + arch/x86/include/asm/irq.h | 4 + arch/x86/lib/Makefile | 4 +- arch/x86/lib/acpi_table.c | 380 ++++---- arch/x86/lib/bootm.c | 9 - arch/x86/lib/coreboot_table.c | 31 + arch/x86/lib/pirq_routing.c | 4 - arch/x86/lib/smbios.c | 10 +- arch/x86/lib/tables.c | 3 +- board/congatec/conga-qeval20-qa3-e3845/.gitignore | 3 + board/congatec/conga-qeval20-qa3-e3845/Makefile | 1 + board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl | 13 + board/congatec/conga-qeval20-qa3-e3845/dsdt.asl | 14 + board/intel/bayleybay/.gitignore | 3 + board/intel/bayleybay/Makefile | 1 + board/intel/bayleybay/acpi/mainboard.asl | 11 + board/intel/bayleybay/dsdt.asl | 14 + board/intel/galileo/Kconfig | 11 + board/intel/minnowmax/.gitignore | 3 + board/intel/minnowmax/Makefile | 1 + board/intel/minnowmax/acpi/mainboard.asl | 11 + board/intel/minnowmax/dsdt.asl | 14 + cmd/Kconfig | 7 + cmd/Makefile | 1 + cmd/qfw.c | 194 +++++ configs/bayleybay_defconfig | 2 + configs/conga-qeval20-qa3-e3845_defconfig | 2 + configs/crownbay_defconfig | 3 - configs/galileo_defconfig | 3 + configs/minnowmax_defconfig | 2 + configs/qemu-x86_defconfig | 1 + configs/sandbox_defconfig | 1 + doc/README.x86 | 121 ++- doc/device-tree-bindings/misc/intel,irq-router.txt | 5 + drivers/misc/Kconfig | 6 + drivers/misc/Makefile | 1 + arch/x86/cpu/qemu/fw_cfg.c => drivers/misc/qfw.c | 466 +++------- include/configs/minnowmax.h | 2 +- include/configs/x86-common.h | 9 +- arch/x86/include/asm/fw_cfg.h => include/qfw.h | 31 +- scripts/Makefile.lib | 8 +- 93 files changed, 9859 insertions(+), 7530 deletions(-) create mode 100644 arch/x86/cpu/baytrail/acpi.c create mode 100644 arch/x86/cpu/qemu/e820.c delete mode 100644 arch/x86/dts/microcode/m0130673322.dtsi create mode 100644 arch/x86/dts/microcode/m0130673325.dtsi delete mode 100644 arch/x86/dts/microcode/m0130679901.dtsi create mode 100644 arch/x86/dts/microcode/m0130679907.dtsi delete mode 100644 arch/x86/include/asm/acpi.h create mode 100644 arch/x86/include/asm/acpi/debug.asl create mode 100644 arch/x86/include/asm/acpi/globutil.asl create mode 100644 arch/x86/include/asm/acpi/statdef.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/gpio.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/lpc.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/platform.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/usb.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/xhci.asl create mode 100644 arch/x86/include/asm/arch-baytrail/device.h create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 board/congatec/conga-qeval20-qa3-e3845/.gitignore create mode 100644 board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl create mode 100644 board/congatec/conga-qeval20-qa3-e3845/dsdt.asl create mode 100644 board/intel/bayleybay/.gitignore create mode 100644 board/intel/bayleybay/acpi/mainboard.asl create mode 100644 board/intel/bayleybay/dsdt.asl create mode 100644 board/intel/minnowmax/.gitignore create mode 100644 board/intel/minnowmax/acpi/mainboard.asl create mode 100644 board/intel/minnowmax/dsdt.asl create mode 100644 cmd/qfw.c rename arch/x86/cpu/qemu/fw_cfg.c => drivers/misc/qfw.c (53%) rename arch/x86/include/asm/fw_cfg.h => include/qfw.h (80%) Regards, Bin

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[U-Boot] [PATCH 1/3] net: xilinx: Handle error value from phy_startup()
by Michal Simek 24 May '16

24 May '16

Handle error returned by phy_startup() properly. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/xilinx_emaclite.c | 4 +++- drivers/net/zynq_gem.c | 5 ++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 5862bf0a7e2d..badb99d67c61 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -302,7 +302,9 @@ static int setup_phy(struct udevice *dev) phydev->advertising = supported; emaclite->phydev = phydev; phy_config(phydev); - phy_startup(phydev); + ret = phy_startup(phydev); + if (ret) + return ret; if (!phydev->link) { printf("%s: No link.\n", phydev->dev->name); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index aec8077f10b3..3704ce0dd78a 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -360,6 +360,7 @@ static int zynq_phy_init(struct udevice *dev) static int zynq_gem_init(struct udevice *dev) { u32 i, nwconfig; + int ret; unsigned long clk_rate = 0; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs = priv->iobase; @@ -427,7 +428,9 @@ static int zynq_gem_init(struct udevice *dev) priv->init++; } - phy_startup(priv->phydev); + ret = phy_startup(priv->phydev); + if (ret) + return ret; if (!priv->phydev->link) { printf("%s: No link.\n", priv->phydev->dev->name); -- 1.9.1

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