May 2016 - U-Boot

[U-Boot] [PATCH] armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY
by shh.xie＠gmail.com 24 May '16

24 May '16

From: Shaohui Xie <Shaohui.Xie(a)nxp.com> To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)nxp.com> --- board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ include/configs/ls1043ardb.h | 1 + 2 files changed, 5 insertions(+) diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index ec5fdbf..9e9f24d 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -84,6 +84,8 @@ int board_early_init_f(void) int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + /* * Set CCI-400 control override register to enable barrier @@ -106,6 +108,8 @@ int board_init(void) #ifdef CONFIG_U_QE u_qe_init(); #endif + /* invert AQR105 IRQ pins polarity */ + out_be32(&scfg->intpcr, AQR105_IRQ_MASK); return 0; } diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index bc40b06..bfc1a5c 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -254,6 +254,7 @@ #define CONFIG_PHY_VITESSE #define CONFIG_PHY_REALTEK #define CONFIG_PHY_AQUANTIA +#define AQR105_IRQ_MASK 0x40000000 #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/3] Multiple FSL Security Engine RNG instantation
by Alex Porosanu 24 May '16

24 May '16

This series of patches add the neccesary support for allowing multi-SEC SoCs, like the C292 & C293 to instantiate the respecting RNGs. Alex Porosanu (3): arch/arm: add SEC JR0 offset arch/arm, arch/powerpc: add # of SEC engines on the SOC crypto/fsl: add support for multiple SEC engines initialization arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 9 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 +- arch/arm/include/asm/arch-ls102xa/config.h | 2 + arch/arm/include/asm/arch-mx6/imx-regs.h | 9 +- arch/arm/include/asm/arch-mx7/imx-regs.h | 11 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 + arch/powerpc/include/asm/config_mpc85xx.h | 6 + board/freescale/c29xpcie/c29xpcie.c | 2 +- drivers/crypto/fsl/jr.c | 271 ++++++++++++--------- drivers/crypto/fsl/jr.h | 3 + include/fsl_sec.h | 6 +- 12 files changed, 210 insertions(+), 128 deletions(-) -- 1.9.3

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[U-Boot] [PATCH 3/3] ls102xa: spl: fix the macro name of MMC mode
by Gong Qianyu 24 May '16

24 May '16

There is no MODE_FAT but MODE_FS. Fix it. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> --- arch/arm/cpu/armv7/ls102xa/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c index 1dfbf54..0289058 100644 --- a/arch/arm/cpu/armv7/ls102xa/spl.c +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -20,7 +20,7 @@ u32 spl_boot_mode(void) switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: #ifdef CONFIG_SPL_FAT_SUPPORT - return MMCSD_MODE_FAT; + return MMCSD_MODE_FS; #else return MMCSD_MODE_RAW; #endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 2/3] fsl-layerscape: spl: fix the macro name of MMC mode
by Gong Qianyu 24 May '16

24 May '16

There is no MODE_FAT but MODE_FS. Fix it. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 4c8a9a0..5883c00 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -29,7 +29,7 @@ u32 spl_boot_mode(void) switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: #ifdef CONFIG_SPL_FAT_SUPPORT - return MMCSD_MODE_FAT; + return MMCSD_MODE_FS; #else return MMCSD_MODE_RAW; #endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/3] fsl-layerscape: spl: remove duplicate init_early_memctl_regs()
by Gong Qianyu 24 May '16

24 May '16

init_early_memctl_regs() will also be called in board_early_init_f(). So remove the duplicate call in spl code. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index c1229c8..4c8a9a0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -49,9 +49,6 @@ void board_init_f(ulong dummy) #ifdef CONFIG_LS2080A arch_cpu_init(); #endif -#ifdef CONFIG_FSL_IFC - init_early_memctl_regs(); -#endif board_early_init_f(); timer_init(); #ifdef CONFIG_LS2080A -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] armv8: ls1043a: remove redundant code in board files
by Gong Qianyu 24 May '16

24 May '16

gd->env_addr will be initialized in env_init() in common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined. So no need to do it again. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> --- board/freescale/ls1043aqds/ls1043aqds.c | 4 ---- board/freescale/ls1043ardb/ls1043ardb.c | 5 ----- 2 files changed, 9 deletions(-) diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index fba6b88..a59b8f4 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -325,10 +325,6 @@ int board_init(void) #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif - -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif return 0; } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index ec5fdbf..f1d4c39 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -19,7 +19,6 @@ #include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> -#include <environment.h> #include <fsl_sec.h> #include "cpld.h" #ifdef CONFIG_U_QE @@ -95,10 +94,6 @@ int board_init(void) init_final_memctl_regs(); #endif -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif - #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: ls1043a: copy kernel from QSPI when booting with QSPI enabled
by Gong Qianyu 24 May '16

24 May '16

IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS. So this patch could fix 'sync abort' caused by autoboot that tries to access IFC address. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> --- include/configs/ls1043a_common.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e900c50..d4a181e 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -264,8 +264,13 @@ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ + "e0000 f00000 && bootm $kernel_load" +#else #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" +#endif #define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8/ls1043ardb: fix the limitation of using 'cpld reset'
by Gong Qianyu 24 May '16

24 May '16

The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> --- board/freescale/ls1043ardb/cpld.c | 26 ++++++++++++++++++++++++-- board/freescale/ls1043ardb/cpld.h | 1 + 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 78c2824..c645283 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value) /* Set the boot bank to the alternate bank */ void cpld_set_altbank(void) { + u16 reg = CPLD_CFG_RCW_SRC_NOR; u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); u8 reg7 = CPLD_READ(vbank); - CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL); + cpld_rev_bit(&reg5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; CPLD_WRITE(vbank, reg7); @@ -42,7 +50,21 @@ void cpld_set_altbank(void) /* Set the boot bank to the default bank */ void cpld_set_defbank(void) { - CPLD_WRITE(global_rst, 1); + u16 reg = CPLD_CFG_RCW_SRC_NOR; + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(&reg5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(vbank, 0); + + CPLD_WRITE(system_rst, 1); } void cpld_set_nand(void) diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index bd59c0e..cb175b5 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_SW_MUX_BANK_SEL 0x40 #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_NOR 0x025 #define CPLD_CFG_RCW_SRC_NAND 0x106 #define CPLD_CFG_RCW_SRC_SD 0x040 #endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/1]
by Vincent Siles 24 May '16

24 May '16

In order to activate the TZASC for the LS1021a board, one need to correctly configure the SMMU, by setting ICID for each peripherals in the SCFG ICID registers. The computation of the addresses of such registers is invalid due to wrong pointer arithmetic. Also please note that there is no mention of the following entry in the Reference manual of the LS1021A board. arch/arm/cpu/armv7/ls102xa/soc.c:138 struct smmu_stream_id dev_stream_id[] = { ... { 0x114, 0x06, "qDMA" }, ... Vincent Siles (1): arm: Fix SCFG ICID reg addresses board/freescale/common/ls102xa_stream_id.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] armv8: fsl-layerscape: Remove unnecessary flushing dcache
by Alison Wang 24 May '16

24 May '16

As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b06425ad6e1e90931333a704a600941cfff, the workaround to flush dcache is unnecessary and will be removed. Signed-off-by: Alison Wang <alison.wang(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d939900..9a5a6b5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -396,9 +396,6 @@ static inline void final_mmu_setup(void) flush_dcache_range((ulong)level0_table, (ulong)level0_table + gd->arch.tlb_size); -#ifdef CONFIG_SYS_DPAA_FMAN - flush_dcache_all(); -#endif /* point TTBR to the new table */ set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, MEMORY_ATTRIBUTES); -- 2.1.0.27.g96db324

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