April 2016 - U-Boot

[U-Boot] [PATCH 1/3] musb: sunxi: Do not allocate musb struct multiple times
by Hans de Goede 06 Apr '16

06 Apr '16

The probe function of the musb host driver can be called multiple times. The code assumes that it can safe the pointer to the allocated musb struct in the driver model priv_auto_alloc data, but this data gets free-ed on a probe failure or on removal, so we must safe the pointer elsewhere. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- drivers/usb/musb-new/sunxi.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index be1d2ec..3081afc 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -201,6 +201,7 @@ static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) /* musb_core does not call enable / disable in a balanced manner <sigh> */ static bool enabled = false; +static struct musb *sunxi_musb; static int sunxi_musb_enable(struct musb *musb) { @@ -320,13 +321,15 @@ int musb_usb_probe(struct udevice *dev) priv->desc_before_addr = true; - if (!host->host) { - host->host = musb_init_controller(&musb_plat, NULL, + if (!sunxi_musb) { + sunxi_musb = musb_init_controller(&musb_plat, NULL, (void *)SUNXI_USB0_BASE); - if (!host->host) - return -EIO; } + host->host = sunxi_musb; + if (!host->host) + return -EIO; + ret = musb_lowlevel_init(host); if (ret == 0) printf("MUSB OTG\n"); -- 2.7.2

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[U-Boot] [PATCH v2] spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU
by Stefan Roese 06 Apr '16

06 Apr '16

Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU. The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Jagan Teki <jteki(a)openedev.com> --- v2: - Introduce clain_bus() function and move the CS configuration into it. As it only needs to be done once for the active bus. arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++----- drivers/spi/kirkwood_spi.c | 16 ++++++++++++++++ 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h index 526fea6..78869a2 100644 --- a/arch/arm/include/asm/arch-mvebu/spi.h +++ b/arch/arm/include/asm/arch-mvebu/spi.h @@ -35,13 +35,15 @@ struct kwspi_registers { #define SCK_MPP10 (1 << 1) #define MISO_MPP11 (1 << 2) +/* Control Register */ +#define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */ +#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ +#define KWSPI_CS_SHIFT 2 /* chip select shift */ +#define KWSPI_CS_MASK 0x7 /* chip select mask */ + +/* Configuration Register */ #define KWSPI_CLKPRESCL_MASK 0x1f #define KWSPI_CLKPRESCL_MIN 0x12 -#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ -#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ -#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ -#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ -#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ #define KWSPI_XFERLEN_1BYTE 0 #define KWSPI_XFERLEN_2BYTE (1 << 5) #define KWSPI_XFERLEN_MASK (1 << 5) @@ -50,6 +52,11 @@ struct kwspi_registers { #define KWSPI_ADRLEN_3BYTE (2 << 8) #define KWSPI_ADRLEN_4BYTE (3 << 8) #define KWSPI_ADRLEN_MASK (3 << 8) + +#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ +#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ +#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ + #define KWSPI_TIMEOUT 10000 #endif /* __KW_SPI_H__ */ diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 80cdbd0..969abb7 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -283,6 +283,21 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, return _spi_xfer(plat->spireg, bitlen, dout, din, flags); } +static int mvebu_spi_claim_bus(struct udevice *dev) +{ +#ifdef CONFIG_ARCH_MVEBU + struct udevice *bus = dev->parent; + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + + /* Configure the chip-select in the CTRL register */ + clrsetbits_le32(&plat->spireg->ctrl, + KWSPI_CS_MASK << KWSPI_CS_SHIFT, + spi_chip_select(dev) << KWSPI_CS_SHIFT); +#endif + + return 0; +} + static int mvebu_spi_probe(struct udevice *bus) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); @@ -305,6 +320,7 @@ static int mvebu_spi_ofdata_to_platdata(struct udevice *bus) } static const struct dm_spi_ops mvebu_spi_ops = { + .claim_bus = mvebu_spi_claim_bus, .xfer = mvebu_spi_xfer, .set_speed = mvebu_spi_set_speed, .set_mode = mvebu_spi_set_mode, -- 2.8.1

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[U-Boot] [PATCH] spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU
by Stefan Roese 06 Apr '16

06 Apr '16

Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU. The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Jagan Teki <jteki(a)openedev.com> --- arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++----- drivers/spi/kirkwood_spi.c | 6 ++++++ 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h index e512dce..4b66499 100644 --- a/arch/arm/include/asm/arch-mvebu/spi.h +++ b/arch/arm/include/asm/arch-mvebu/spi.h @@ -32,13 +32,15 @@ struct kwspi_registers { #define SCK_MPP10 (1 << 1) #define MISO_MPP11 (1 << 2) +/* Control Register */ +#define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */ +#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ +#define KWSPI_CS_SHIFT 2 /* chip select shift */ +#define KWSPI_CS_MASK 0x7 /* chip select mask */ + +/* Configuration Register */ #define KWSPI_CLKPRESCL_MASK 0x1f #define KWSPI_CLKPRESCL_MIN 0x12 -#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ -#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ -#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ -#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ -#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ #define KWSPI_XFERLEN_1BYTE 0 #define KWSPI_XFERLEN_2BYTE (1 << 5) #define KWSPI_XFERLEN_MASK (1 << 5) @@ -47,6 +49,11 @@ struct kwspi_registers { #define KWSPI_ADRLEN_3BYTE (2 << 8) #define KWSPI_ADRLEN_4BYTE (3 << 8) #define KWSPI_ADRLEN_MASK (3 << 8) + +#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ +#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ +#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ + #define KWSPI_TIMEOUT 10000 #endif /* __KW_SPI_H__ */ diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 7890796..fa30be4 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -280,6 +280,12 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, struct udevice *bus = dev->parent; struct mvebu_spi_platdata *plat = dev_get_platdata(bus); +#ifdef CONFIG_ARCH_MVEBU + clrsetbits_le32(&plat->spireg->ctrl, + KWSPI_CS_MASK << KWSPI_CS_SHIFT, + spi_chip_select(dev) << KWSPI_CS_SHIFT); +#endif + return _spi_xfer(plat->spireg, bitlen, dout, din, flags); } -- 2.7.1

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[U-Boot] imx6 nand support in u-boot
by Maxim Podbereznyy 06 Apr '16

06 Apr '16

Hi! I have a custom imx6q board with NAND сhip (MT29F2G08ABAEA). I've already compiled a few u-boot versions from different vendors and repositories including Freescale, Boundary and Denx mainline. I have to mention that in all repositories I use nitrogen6x board as reference because it has similar design and very convenient set of files to fill in DDR3 registers. I need to modify DDR settings because DDR3 calibration tools shows different values. So what I achieved so far: 1) Freescale uboot-imx->imx_v2013.04_3.10.17_1.0.0_ga boots fine, NAND detected, NAND erase hangs: U-Boot 2013.04-04989-g6bb0820-dirty (Apr 06 2016 - 09:46:52) CPU: Freescale i.MX6Q rev1.5 at 792 MHz CPU: Temperature 37 C, calibration data: 0x5824ec69 Reset cause: POR Board: Nitrogen6X I2C: ready DRAM: 1 GiB NAND: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 MMC: no card present MMC init failed Using default environment No panel detected: default to HDMI unsupported panel HDMI In: serial Out: serial Err: serial Net: Phy not found using phy at 4 PHY reset timed out FEC [PRIME] Warning: failed to set MAC address Boot from USB for mfgtools Use default environment for mfgtools Run bootcmd_mfg: run mfgtool_args;bootm ${loadaddr} ${initrd_addr} ${fdt_addr}; Hit any key to stop autoboot: 0 Wrong Image Format for bootm command ERROR: can't get kernel image! U-Boot > nand info Device 0: nand0, sector size 128 KiB Page size 2048 b OOB size 64 b Erase size 131072 b U-Boot > nand erase.chip NAND erase.chip: device 0 whole chip <<<here nothing happens and the board hangs 2) Denx u-boot mainline, branch v2016.03 git clone https://github.com/u-boot/u-boot cd u-boot/ git checkout v2016.03 -b tmp Results: boots fine, NAND detected, NAND erase hangs with lots of DMA errors: U-Boot 2016.03-dirty (Apr 06 2016 - 10:07:27 +0300) CPU: Freescale i.MX6Q rev1.5 at 792 MHz Reset cause: POR Board: Nitrogen6X I2C: ready DRAM: 1 GiB NAND: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 SF: Unsupported flash IDs: manuf 00, jedec 0000, ext_jedec 0000 *** Warning - spi_flash_probe() failed, using default environment No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: Board Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 => nand info Device 0: nand0, sector size 128 KiB Page size 2048 b OOB size 64 b Erase size 131072 b subpagesize 2048 b options 0x 200 bbt options 0x 8000 => nand erase.chip NAND erase.chip: device 0 whole chip MXS NAND: DMA read error MXS NAND: Error sending command MXS NAND: Error sending command MXS NAND: DMA read error MXS NAND: Error sending command MXS NAND: Error sending command MXS NAND: DMA read error Here is the patch: diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg index 8bddb91..52e3c8d 100644 --- a/board/boundary/nitrogen6x/clocks.cfg +++ b/board/boundary/nitrogen6x/clocks.cfg @@ -19,8 +19,8 @@ DATA 4, CCM_CCGR0, 0x00C03F3F DATA 4, CCM_CCGR1, 0x0030FC03 DATA 4, CCM_CCGR2, 0x0FFFC000 DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR4, 0xFFFFF300 +DATA 4, CCM_CCGR5, 0x0F0000F3 DATA 4, CCM_CCGR6, 0x000003FF /* enable AXI cache for VDOA/VPU/IPU */ diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 104d71f..ddbbf8a 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -65,6 +65,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) int dram_init(void) @@ -75,8 +80,8 @@ int dram_init(void) } static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const uart2_pads[] = { @@ -358,6 +363,42 @@ static void setup_spi(void) } #endif +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + int board_phy_config(struct phy_device *phydev) { /* min rx data delay */ @@ -865,6 +906,9 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); setup_buttons(); +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif #if defined(CONFIG_VIDEO_IPUV3) setup_display(); diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 3416ce3..d7bb74d 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -27,7 +27,7 @@ #define CONFIG_NETCONSOLE #define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CMD_SF #ifdef CONFIG_CMD_SF @@ -347,4 +347,20 @@ #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 +/* NAND flash command */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + #endif /* __CONFIG_H */

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[U-Boot] [PATCH 0/2] i.MX6 LPDDR2 fixes
by Tom Rini 06 Apr '16

06 Apr '16

Hey all, The following two patches fix JEDEC violations that were observed when I was working on a board similar to the MX6SL EVK. Based on talking with Micron and reading up on what the code here is (and isn't) doing, I'm certain these issues exist on the reference platforms here. I'm publishing these for correctness. I'm also not updating the the SPL code as I haven't tested that (and only could for EVK anyhow) but would suggest it's worth a follow-up from tha maintainers. -- Tom

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[U-Boot] [PATCH] dm: core: device: set pinctrl state for pinctrl device
by Peng Fan 06 Apr '16

06 Apr '16

We may have pinmux settings for pinctrl device, like the following example: " &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; imx6ul-evk { pinctrl_hog_1: hoggrp-1 { fsl,pins = < MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 >; }; [......] }; " We should not only select pinctrl state for non pinctrl devices, we need also to handle pin mux settings such as pinctrl_log for pinctrl devices. So at the end of probing process of pinctrl device, select the default state of pinctrl device. Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/core/device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/core/device.c b/drivers/core/device.c index cb24a61..6b1ba22 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -332,6 +332,9 @@ int device_probe(struct udevice *dev) if (ret) goto fail_uclass; + if (dev->parent && device_get_uclass_id(dev) == UCLASS_PINCTRL) + pinctrl_select_state(dev, "default"); + return 0; fail_uclass: if (device_remove(dev)) { -- 2.6.2

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[U-Boot] [PATCH v1] tpm: Fix uclass_first_device error handling
by Mario Six 05 Apr '16

05 Apr '16

uclass_first_device might return NULL for the device despite a zero return code. Currently, this might lead to null pointer dereferencing, since the returned device is not properly checked. Hence, always check if the device returned from uclass_first_device is NULL and return -ENODEV if it is. Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- lib/tpm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/tpm.c b/lib/tpm.c index f428d45..42aea0a 100644 --- a/lib/tpm.c +++ b/lib/tpm.c @@ -245,6 +245,8 @@ static uint32_t tpm_sendrecv_command(const void *command, ret = uclass_first_device(UCLASS_TPM, &dev); if (ret) return ret; + if (!dev) + return -ENODEV; err = tpm_xfer(dev, command, tpm_command_size(command), response, &response_length); @@ -262,8 +264,10 @@ int tpm_init(void) struct udevice *dev; err = uclass_first_device(UCLASS_TPM, &dev); - if (err || !dev) + if (err) return err; + if (!dev) + return -ENODEV; return tpm_open(dev); } -- 2.7.0.GIT

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[U-Boot] [uboot] [PATCH 1/2] net: phy: dp83867: Add device tree bindings and documentation
by Dan Murphy 05 Apr '16

05 Apr '16

Add the device tree bindings and the accompanying documentation for the TI DP83867 Giga bit ethernet phy driver. The original document was from: [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel] Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- RFC->v1 - Separated out bindings to a different patch and added the bindings documentation - https://patchwork.ozlabs.org/patch/604113/ doc/device-tree-bindings/net/ti,dp83867.txt | 28 +++++++++++++++++++++++ include/dt-bindings/net/ti-dp83867.h | 35 +++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 doc/device-tree-bindings/net/ti,dp83867.txt create mode 100644 include/dt-bindings/net/ti-dp83867.h diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt new file mode 100644 index 0000000..2516b45 --- /dev/null +++ b/doc/device-tree-bindings/net/ti,dp83867.txt @@ -0,0 +1,28 @@ +* Texas Instruments - dp83867 Giga bit ethernet phy + +Required properties: + - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h + for applicable values + +Default child nodes are standard Ethernet PHY device +nodes as described in doc/devicetree/bindings/net/ethernet.txt + +Example: + +&mac { + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; + + ti,rx_int_delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx_int_delay = <DP83867_RGMIIDCTL_2_50_NS>; + ti,fifo_depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + +}; + +Datasheet can be found: +http://www.ti.com/product/DP83867IR/datasheet diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h new file mode 100644 index 0000000..5c592fb --- /dev/null +++ b/include/dt-bindings/net/ti-dp83867.h @@ -0,0 +1,35 @@ +/* + * TI DP83867 PHY drivers + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#ifndef _DT_BINDINGS_TI_DP83867_H +#define _DT_BINDINGS_TI_DP83867_H + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xa +#define DP83867_RGMIIDCTL_3_00_NS 0xb +#define DP83867_RGMIIDCTL_3_25_NS 0xc +#define DP83867_RGMIIDCTL_3_50_NS 0xd +#define DP83867_RGMIIDCTL_3_75_NS 0xe +#define DP83867_RGMIIDCTL_4_00_NS 0xf + +#endif -- 2.8.0.rc3

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[U-Boot] [uboot] [PATCH v2 1/2] net: phy: dp83867: Add device tree bindings and documentation
by Dan Murphy 05 Apr '16

05 Apr '16

Add the device tree bindings and the accompanying documentation for the TI DP83867 Giga bit ethernet phy driver. The original document was from: [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel] Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- v2 - Align the documentation with the actual bindings - https://patchwork.ozlabs.org/patch/606502/ doc/device-tree-bindings/net/ti,dp83867.txt | 28 +++++++++++++++++++++++ include/dt-bindings/net/ti-dp83867.h | 35 +++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 doc/device-tree-bindings/net/ti,dp83867.txt create mode 100644 include/dt-bindings/net/ti-dp83867.h diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt new file mode 100644 index 0000000..34b1c35 --- /dev/null +++ b/doc/device-tree-bindings/net/ti,dp83867.txt @@ -0,0 +1,28 @@ +* Texas Instruments - dp83867 Giga bit ethernet phy + +Required properties: + - ti,rx_int_delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,tx_int_delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h + for applicable values + +Default child nodes are standard Ethernet PHY device +nodes as described in doc/devicetree/bindings/net/ethernet.txt + +Example: + +&mac { + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; + + ti,rx_int_delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx_int_delay = <DP83867_RGMIIDCTL_2_50_NS>; + ti,fifo_depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + +}; + +Datasheet can be found: +http://www.ti.com/product/DP83867IR/datasheet diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h new file mode 100644 index 0000000..5c592fb --- /dev/null +++ b/include/dt-bindings/net/ti-dp83867.h @@ -0,0 +1,35 @@ +/* + * TI DP83867 PHY drivers + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#ifndef _DT_BINDINGS_TI_DP83867_H +#define _DT_BINDINGS_TI_DP83867_H + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xa +#define DP83867_RGMIIDCTL_3_00_NS 0xb +#define DP83867_RGMIIDCTL_3_25_NS 0xc +#define DP83867_RGMIIDCTL_3_50_NS 0xd +#define DP83867_RGMIIDCTL_3_75_NS 0xe +#define DP83867_RGMIIDCTL_4_00_NS 0xf + +#endif -- 2.8.0.rc3

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[U-Boot] [PATCH v1] Revert "fastboot: OUT transaction length must be aligned to wMaxPacketSize"
by Steve Rae 05 Apr '16

05 Apr '16

This reverts commit 9e4b510d40310bf46e09f4edd0a0b6356213df47. Signed-off-by: Steve Rae <srae(a)broadcom.com> --- As discussed on the mailing list, this change breaks the download portion of fastboot by causing the server (the device running U-Boot) to wait forever for bytes which are never sent by the client (the host connected via USB). Does anyone know how to contact: Dileep Katta <dileep.katta(a)linaro.org> (this email bounces) ? drivers/usb/gadget/f_fastboot.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index a54b4ee..887cf4f 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -57,7 +57,6 @@ static struct f_fastboot *fastboot_func; static unsigned int fastboot_flash_session_id; static unsigned int download_size; static unsigned int download_bytes; -static bool is_high_speed; static struct usb_endpoint_descriptor fs_ep_in = { .bLength = USB_DT_ENDPOINT_SIZE, @@ -241,13 +240,10 @@ static int fastboot_set_alt(struct usb_function *f, __func__, f->name, interface, alt); /* make sure we don't enable the ep twice */ - if (gadget->speed == USB_SPEED_HIGH) { + if (gadget->speed == USB_SPEED_HIGH) ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out); - is_high_speed = true; - } else { + else ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out); - is_high_speed = false; - } if (ret) { puts("failed to enable out ep\n"); return ret; @@ -419,20 +415,13 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) fastboot_tx_write_str(response); } -static unsigned int rx_bytes_expected(unsigned int maxpacket) +static unsigned int rx_bytes_expected(void) { int rx_remain = download_size - download_bytes; - int rem = 0; if (rx_remain < 0) return 0; if (rx_remain > EP_BUFFER_SIZE) return EP_BUFFER_SIZE; - if (rx_remain < maxpacket) { - rx_remain = maxpacket; - } else if (rx_remain % maxpacket != 0) { - rem = rx_remain % maxpacket; - rx_remain = rx_remain + (maxpacket - rem); - } return rx_remain; } @@ -444,7 +433,6 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) const unsigned char *buffer = req->buf; unsigned int buffer_size = req->actual; unsigned int pre_dot_num, now_dot_num; - unsigned int max; if (req->status != 0) { printf("Bad status: %d\n", req->status); @@ -482,9 +470,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) printf("\ndownloading of %d bytes finished\n", download_bytes); } else { - max = is_high_speed ? hs_ep_out.wMaxPacketSize : - fs_ep_out.wMaxPacketSize; - req->length = rx_bytes_expected(max); + req->length = rx_bytes_expected(); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } @@ -497,7 +483,6 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; char response[FASTBOOT_RESPONSE_LEN]; - unsigned int max; strsep(&cmd, ":"); download_size = simple_strtoul(cmd, NULL, 16); @@ -513,9 +498,7 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) } else { sprintf(response, "DATA%08x", download_size); req->complete = rx_handler_dl_image; - max = is_high_speed ? hs_ep_out.wMaxPacketSize : - fs_ep_out.wMaxPacketSize; - req->length = rx_bytes_expected(max); + req->length = rx_bytes_expected(); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } -- 1.8.5

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