April 2016 - U-Boot

[U-Boot] [uboot][PATCH v3 1/2] net: phy: dp83867: Add device tree bindings and documentation
by Dan Murphy 08 Apr '16

08 Apr '16

Add the device tree bindings and the accompanying documentation for the TI DP83867 Giga bit ethernet phy driver. The original document was from: [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel] Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- v3 - Modify the binding to the kernel changed int -> internal for the delay - https://patchwork.ozlabs.org/patch/606595/ doc/device-tree-bindings/net/ti,dp83867.txt | 29 ++++++++++++++++++++++++ include/dt-bindings/net/ti-dp83867.h | 35 +++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 doc/device-tree-bindings/net/ti,dp83867.txt create mode 100644 include/dt-bindings/net/ti-dp83867.h diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt new file mode 100644 index 0000000..0ec009c --- /dev/null +++ b/doc/device-tree-bindings/net/ti,dp83867.txt @@ -0,0 +1,29 @@ +* Texas Instruments - dp83867 Giga bit ethernet phy + +Required properties: + - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h + for applicable values + +Default child nodes are standard Ethernet PHY device +nodes as described in doc/devicetree/bindings/net/ethernet.txt + +Example: + +&mac { + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; + + ti,rx_internal_delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx_internal_delay = <DP83867_RGMIIDCTL_2_50_NS>; + ti,fifo_depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + +}; + + +Datasheet can be found: +http://www.ti.com/product/DP83867IR/datasheet diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h new file mode 100644 index 0000000..5c592fb --- /dev/null +++ b/include/dt-bindings/net/ti-dp83867.h @@ -0,0 +1,35 @@ +/* + * TI DP83867 PHY drivers + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#ifndef _DT_BINDINGS_TI_DP83867_H +#define _DT_BINDINGS_TI_DP83867_H + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xa +#define DP83867_RGMIIDCTL_3_00_NS 0xb +#define DP83867_RGMIIDCTL_3_25_NS 0xc +#define DP83867_RGMIIDCTL_3_50_NS 0xd +#define DP83867_RGMIIDCTL_3_75_NS 0xe +#define DP83867_RGMIIDCTL_4_00_NS 0xf + +#endif -- 2.8.0.rc3

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[U-Boot] [PATCH] gpio: mvebu_gpio: Add missing out value set to gpio_direction_output()
by Stefan Roese 08 Apr '16

08 Apr '16

This patch adds the missing configuration of the output value to the gpio_direction_output() function. Without this, calling gpio_direction_output() does not set the out-value at all and only configures the gpio as output. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Kevin Smith <kevin.smith(a)elecsyscorp.com> --- drivers/gpio/mvebu_gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpio/mvebu_gpio.c b/drivers/gpio/mvebu_gpio.c index 9564ce2..75dc73e 100644 --- a/drivers/gpio/mvebu_gpio.c +++ b/drivers/gpio/mvebu_gpio.c @@ -43,6 +43,10 @@ static int mvebu_gpio_direction_output(struct udevice *dev, unsigned gpio, struct mvebu_gpio_priv *priv = dev_get_priv(dev); struct mvebu_gpio_regs *regs = priv->regs; + if (value) + setbits_le32(&regs->data_out, BIT(gpio)); + else + clrbits_le32(&regs->data_out, BIT(gpio)); clrbits_le32(&regs->io_conf, BIT(gpio)); return 0; -- 2.8.1

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[U-Boot] [PATCH] arm: mvebu: theadorable: Remove Board name output in checkboard
by Stefan Roese 08 Apr '16

08 Apr '16

This line is not needed, as the board supports DT based probing. And here the "Model:" is already printed: Model: Marvell Armada XP theadorable Board: theadorable One line for the board name is enough. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/theadorable/theadorable.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index 5836bf7..9c0f120 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -193,8 +193,6 @@ int board_init(void) int checkboard(void) { - puts("Board: theadorable\n"); - board_fpga_add(); -- 2.8.1

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[U-Boot] [PATCH 1/3] arm: mvebu: Add base address for 2nd I2C controller
by Stefan Roese 08 Apr '16

08 Apr '16

Add MVEBU_TWSI1_BASE define so that the 2nd I2C controller on e.g. AXP can be used. Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/arm/mach-mvebu/include/mach/soc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index a12be2a..13c9f29 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -55,6 +55,7 @@ #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) #define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) +#define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100)) #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) -- 2.8.1

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[U-Boot] [PATCH] keystone2: move platform specific NAND configs to platform specific header
by Lokesh Vutla 08 Apr '16

08 Apr '16

From: Roger Quadros <rogerq(a)ti.com> Not all keystone 2 devices use Davinci NAND controller. Move the platform specific NAND configurations into platform specific headers. Reported-by: Nishanth Menon <nm(a)ti.com> Signed-off-by: Roger Quadros <rogerq(a)ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm(a)ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- - This fixes the asynchronous abort generated in kernel. Without this patch: http://pastebin.ubuntu.com/15683902/ With this patch: http://pastebin.ubuntu.com/15683889/ board/ti/ks2_evm/board.c | 5 +++++ include/configs/k2e_evm.h | 21 ++++++++++++++++++--- include/configs/k2hk_evm.h | 21 ++++++++++++++++++--- include/configs/k2l_evm.h | 21 ++++++++++++++++++--- include/configs/ti_armv7_keystone2.h | 16 ---------------- 5 files changed, 59 insertions(+), 25 deletions(-) diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index e16669d..9e8ad93 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -20,6 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_TI_AEMIF) static struct aemif_config aemif_configs[] = { { /* CS0 */ .mode = AEMIF_MODE_NAND, @@ -33,6 +34,7 @@ static struct aemif_config aemif_configs[] = { .width = AEMIF_WIDTH_8, }, }; +#endif int dram_init(void) { @@ -42,7 +44,10 @@ int dram_init(void) gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); +#if defined(CONFIG_TI_AEMIF) aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); +#endif + if (ddr3_size) ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); return 0; diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 07f975b..8c0f20e 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -27,14 +27,29 @@ "name_uboot=u-boot-spi-k2e-evm.gph\0" \ "name_fs=arago-console-image-k2e-evm.cpio.gz\0" +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_NAND_DAVINCI +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* AEMIF */ +#define CONFIG_TI_AEMIF +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + #include <configs/ti_armv7_keystone2.h> /* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c100000 -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 9 diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index a268a86..a23e41d 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -27,14 +27,29 @@ "name_uboot=u-boot-spi-k2hk-evm.gph\0" \ "name_fs=arago-console-image-k2hk-evm.cpio.gz\0" +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_NAND_DAVINCI +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* AEMIF */ +#define CONFIG_TI_AEMIF +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + #include <configs/ti_armv7_keystone2.h> /* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c200000 -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index f366e67..c1100a1 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -27,14 +27,29 @@ "name_uboot=u-boot-spi-k2l-evm.gph\0" \ "name_fs=arago-console-image-k2l-evm.cpio.gz\0" +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_4K +#define CONFIG_NAND_DAVINCI +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* AEMIF */ +#define CONFIG_TI_AEMIF +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + #include <configs/ti_armv7_keystone2.h> /* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c100000 -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_4K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 41185a1..84e02b8 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -145,10 +145,6 @@ /* SerDes */ #define CONFIG_TI_KEYSTONE_SERDES -/* AEMIF */ -#define CONFIG_TI_AEMIF -#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE - /* I2C Configuration */ #define CONFIG_SYS_I2C_DAVINCI #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 @@ -167,16 +163,7 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C /* NAND Configuration */ -#define CONFIG_NAND_DAVINCI -#define CONFIG_KEYSTONE_RBL_NAND -#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET -#define CONFIG_SYS_NAND_MASK_CLE 0x4000 -#define CONFIG_SYS_NAND_MASK_ALE 0x2000 -#define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST - -#define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 @@ -210,9 +197,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES -#define CONFIG_CMD_NAND -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS #define CONFIG_CMD_SF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_USB -- 2.1.4

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[U-Boot] [PATCH v2 00/11] ARMv7: PSCI: add PSCI v1.0 support
by macro.wave.z＠gmail.com 08 Apr '16

08 Apr '16

From: Hongbo Zhang <hongbo.zhang(a)nxp.com> This patch set contains two parts: ARMv7 PSCI common framework: fix some issues and add v1.0 support NXP (was Freescale) LS102XA: codes enhancement and add v1.0 implementation Changes since v1: - re-organize psci_cpu_on_common, this code should be called by each platform's psci_cpu_on, should not be a function calling each psci_cpu_on, all related functions are updated due to this change - update some registers usage, e.g. if r10 is used without push/pop, u-boot cannot launch rt-kernel - update some comments to be clearer, re-organize all patches for easier review - add patch to check already_on or on_pending for LS102XA Hongbo Zhang: Wang Dongsheng: ARMv7: PSCI: update function psci_get_cpu_stack_top ARMv7: PSCI: update the place of saving target PC ARMv7: PSCI: add codes to save context ID for CPU_ON ARMv7: PSCI: factor out reusable psci_cpu_on_common ARMv7: PSCI: add PSCI v1.0 functions skeleton ARMv7: PSCI: ls102xa: check target CPU ID before further operations ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention ARMv7: PSCI: ls102xa: move secure text section into OCRAM ARM: PSCI: change PSCI function IDs base and offsets ARM: PSCI: change PSCI related macros definition style arch/arm/cpu/armv7/ls102xa/psci.S | 177 +++++++++++++++++++++++++++-- arch/arm/cpu/armv7/mx7/psci.S | 7 +- arch/arm/cpu/armv7/nonsec_virt.S | 7 ++ arch/arm/cpu/armv7/psci.S | 113 +++++++++++++++--- arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 8 +- arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 8 +- arch/arm/cpu/armv7/virt-dt.c | 54 ++++++--- arch/arm/include/asm/arch-ls102xa/config.h | 3 +- arch/arm/include/asm/psci.h | 62 +++++++--- arch/arm/mach-tegra/psci.S | 7 +- board/freescale/ls1021aqds/Makefile | 1 + board/freescale/ls1021aqds/psci.S | 36 ++++++ board/freescale/ls1021atwr/Makefile | 1 + board/freescale/ls1021atwr/psci.S | 28 +++++ include/configs/ls1021aqds.h | 3 + include/configs/ls1021atwr.h | 3 + 16 files changed, 449 insertions(+), 69 deletions(-) create mode 100644 board/freescale/ls1021aqds/psci.S create mode 100644 board/freescale/ls1021atwr/psci.S -- 2.1.4

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[U-Boot] [PATCH 01/16] ARM: zynq: Add interrupt-controller property to gpio nodes
by Michal Simek 08 Apr '16

08 Apr '16

GPIO driver supports an input interrupt that's why gpio node itself can be labeled as interrupt controller. Reported-by: John Linn <linnj(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynq-7000.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 2d786f0fd15d..a352bc87114e 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -96,8 +96,10 @@ gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; + #interrupt-cells = <2>; clocks = <&clkc 42>; gpio-controller; + interrupt-controller; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; -- 1.9.1

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[U-Boot] [PATCH 01/33] ARM64: zynqmp: Move kernel and fdt offsets and sizes to board config file
by Michal Simek 07 Apr '16

07 Apr '16

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Move kernel and fdt offsets and sizes to board config file as the flash size varies across boards Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/configs/xilinx_zynqmp.h | 3 +-- include/configs/xilinx_zynqmp_ep.h | 7 +++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8cea61080d49..a60325517647 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -165,8 +165,7 @@ "kernel_addr=0x80000\0" \ "fdt_addr=0x7000000\0" \ "fdt_high=0x10000000\0" \ - "kernel_size=0x2000000\0" \ - "fdt_size=0x80000\0" \ + CONFIG_KERNEL_FDT_OFST_SIZE \ "sdbootdev=0\0"\ "sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \ "load mmc $sdbootdev:$partid $kernel_addr Image && " \ diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index aa58b62531d4..4a83eee6d0b8 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -24,6 +24,13 @@ #define COUNTER_FREQUENCY 4000000 +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=ep108\0" + #include <configs/xilinx_zynqmp.h> #endif /* __CONFIG_ZYNQMP_EP_H */ -- 1.9.1

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[U-Boot] [PATCH] arm: sleep: Get the entry point of kernel from SPARE4 register
by Alison Wang 07 Apr '16

07 Apr '16

For LS1021A Secure Boot, SPARE2 register is used and modified by the IBR. To avoid the conflict, SPARE4 is used instead of SPARE2 to store the entry point of kernel. This patch is to get the entry point of kernel from SPARE4 instead of SPARE2. Signed-off-by: Alison Wang <alison.wang(a)nxp.com> --- board/freescale/common/arm_sleep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index 71ed15e..6d967f0 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -88,7 +88,7 @@ int fsl_dp_resume(void) dp_resume_prepare(); /* Get the entry address and jump to kernel */ - start_addr = in_le32(&scfg->sparecr[1]); + start_addr = in_le32(&scfg->sparecr[3]); debug("Entry address is 0x%08x\n", start_addr); kernel_resume = (void (*)(void))start_addr; secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); -- 2.1.0.27.g96db324

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[U-Boot] Mainline u-boot installation on Odroid-UX4
by Shawn Guo 07 Apr '16

07 Apr '16

Hi Przemyslaw, Anand, I just got a Odroid-UX4 board to play. I installed firmware (bl1, bl2, tzsw, u-boot) from hardkernel using sd_fusing.sh, and the board boots fine. But when I install mainline u-boot v2016.03 by following doc/README.odroid, the board refuses to boot with nothing appearing on serial console. Here is what I did: - make odroid-xu3_defconfig - make (using arm-linux-gnueabi-gcc 4.7.3) - copy u-boot.bin (which is same as u-boot-dtb.bin in v2016.03 release) to sd_fuse/hardkernel folder, and modify sd_fusing.sh to get it point to this new U-Boot - ./sd_fusing.sh /dev/sdX to flash the SD card One thing I'm not sure is the offset that firmware should be installed to SD card. The doc/README.odroid and hardkernel sd_fusing.sh tells different ones. doc/README.odroid: ------------------------------------- | Binary | Block offset| part type | | name | SD | eMMC |(eMMC only)| ------------------------------------- | Bl1 | 1 | 0 | 1 (boot) | | Bl2 | 31 | 30 | 1 (boot) | | U-Boot | 63 | 62 | 1 (boot) | | Tzsw | 2111 | 2110 | 1 (boot) | | Uboot Env | 2560 | 2560 | 0 (user) | ------------------------------------- sd_fusing.sh: signed_bl1_position=1 bl2_position=31 uboot_position=63 tzsw_position=719 env_position=1231 I tried both sets, and neither works for me. I know Odroid-UX4 is supported by mainline U-Boot today, so there must be something missing from my setup. Could you please help me here? Thanks. Shawn

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