December 2016 - U-Boot

[U-Boot] [v2, 1/3] mmc: fsl_esdhc: move 'status' property fixup into a weak function
by Yangbo Lu 08 Dec '16

08 Dec '16

Move fdt fixup of 'status' property into a weak function. This allows board to define 'status' fdt fixup by themselves. Signed-off-by: Yangbo Lu <yangbo.lu(a)nxp.com> --- Changes for v2: - None --- drivers/mmc/fsl_esdhc.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 9796d39..68de04e 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -908,17 +908,26 @@ void mmc_adapter_card_type_ident(void) #endif #ifdef CONFIG_OF_LIBFDT -void fdt_fixup_esdhc(void *blob, bd_t *bd) +__weak int esdhc_status_fixup(void *blob, const char *compat) { - const char *compat = "fsl,esdhc"; - #ifdef CONFIG_FSL_ESDHC_PIN_MUX if (!hwconfig("esdhc")) { do_fixup_by_compat(blob, compat, "status", "disabled", - 8 + 1, 1); - return; + sizeof("disabled"), 1); + return 1; } #endif + do_fixup_by_compat(blob, compat, "status", "okay", + sizeof("okay"), 1); + return 0; +} + +void fdt_fixup_esdhc(void *blob, bd_t *bd) +{ + const char *compat = "fsl,esdhc"; + + if (esdhc_status_fixup(blob, compat)) + return; #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", @@ -931,8 +940,6 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, compat, "adapter-type", (u32)(gd->arch.sdhc_adapter), 1); #endif - do_fixup_by_compat(blob, compat, "status", "okay", - 4 + 1, 1); } #endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] bootm: relocate ramdisk if CONFIG_SYS_BOOT_RAMDISK_HIGH set
by Rick Altherr 08 Dec '16

08 Dec '16

In 35fc84f, bootm was refactored so plain 'bootm' and 'bootm <subcommand>' shared a common implementation. The 'bootm ramdisk' command implementation is now part of the common implementation but not invoke by plain 'bootm' since the original implementation never did ramdisk relocation. Instead, ramdisk relocation happened in image_setup_linux() which is typically called during the OS portion of 'bootm'. On ARM, parameters to the Linux kernel can either be passed by FDT or ATAGS. When using FDT, image_setup_linux() is called which also triggers ramdisk relocation. When using ATAGS, image_setup_linux() is _not_ called because it mostly does FDT setup. Instead of calling image_setup_linux() in both FDT and ATAGS cases, include BOOTM_STATE_RAMDISK in the requested states during a plain 'bootm' if CONFIG_SYS_BOOT_RAMDISK_HIGH is set and remove the ramdisk relocation from image_setup_linux(). This causes ramdisk relocation to happen on any system where CONFIG_SYS_BOOT_RAMDISK_HIGH regardless of the OS being booted. Also remove IMAGE_ENABLE_RAMDISK_HIGH as it was only used by the now-removed code from image_setup_linux(). Signed-off-by: Rick Altherr <raltherr(a)google.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Joel Stanley <joel(a)jms.id.au> --- cmd/bootm.c | 3 +++ common/image.c | 10 ---------- include/image.h | 6 ------ 3 files changed, 3 insertions(+), 16 deletions(-) diff --git a/cmd/bootm.c b/cmd/bootm.c index 083f3d1..a7e181d 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -126,6 +126,9 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START | BOOTM_STATE_FINDOS | BOOTM_STATE_FINDOTHER | BOOTM_STATE_LOADOS | +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH + BOOTM_STATE_RAMDISK | +#endif #if defined(CONFIG_PPC) || defined(CONFIG_MIPS) BOOTM_STATE_OS_CMDLINE | #endif diff --git a/common/image.c b/common/image.c index bd07e86..b4a6839 100644 --- a/common/image.c +++ b/common/image.c @@ -1571,10 +1571,7 @@ int image_setup_linux(bootm_headers_t *images) { ulong of_size = images->ft_len; char **of_flat_tree = &images->ft_addr; - ulong *initrd_start = &images->initrd_start; - ulong *initrd_end = &images->initrd_end; struct lmb *lmb = &images->lmb; - ulong rd_len; int ret; if (IMAGE_ENABLE_OF_LIBFDT) @@ -1588,13 +1585,6 @@ int image_setup_linux(bootm_headers_t *images) return ret; } } - if (IMAGE_ENABLE_RAMDISK_HIGH) { - rd_len = images->rd_end - images->rd_start; - ret = boot_ramdisk_high(lmb, images->rd_start, rd_len, - initrd_start, initrd_end); - if (ret) - return ret; - } if (IMAGE_ENABLE_OF_LIBFDT) { ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); diff --git a/include/image.h b/include/image.h index 575f592..4c39bd7 100644 --- a/include/image.h +++ b/include/image.h @@ -99,12 +99,6 @@ struct lmb; #endif /* IMAGE_ENABLE_FIT */ -#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH -# define IMAGE_ENABLE_RAMDISK_HIGH 1 -#else -# define IMAGE_ENABLE_RAMDISK_HIGH 0 -#endif - #ifdef CONFIG_SYS_BOOT_GET_CMDLINE # define IMAGE_BOOT_GET_CMDLINE 1 #else -- 2.8.0.rc3.226.g39d4020

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[U-Boot] How to take value of an environmental variable of uboot in linux
by Haris Papadopoulos 07 Dec '16

07 Dec '16

Hi, I type fw_printenv variable_name to take the name of a uboot variable from linux. I get variable_name=10 for example How can I use the value 10 in the continuation of my script? I have tried string = fw_printenv flag_boot_error IFS="=" read name value <<< $string but it does not work Thank you -- Haris Papadopoulos| AmberBox | Software Engineer haris(a)amberbox.com <tomas(a)amberbox.com> | + 1 650-686-0230

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[U-Boot] [PATCH 0/1] Adding MSCC PHY-VSC8530-VSC8531-VSC8540-VSC8541
by John Haechten 07 Dec '16

07 Dec '16

>From 127c5fb9ef390cad5cf58e446110a696cf111345 Mon Sep 17 00:00:00 2001 From: John Haechten <john.haechten(a)microsemi.com> Date: Wed, 7 Dec 2016 08:42:51 -0800 Subject: [PATCH 0/1] Adding MSCC PHY-VSC8530-VSC8531-VSC8540-VSC8541 Tested using BeagleBoneBlack,bb.org-overlays, v2016.11-rc3, with 0001-am335x_evm-uEnv.txt-bootz-n-fixes.patch applied John Haechten (1): Adding MSCC PHY-VSC8530-VSC8531-VSC8540-VSC8541 drivers/net/phy/Makefile | 1 + drivers/net/phy/mscc.c | 480 ++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 + include/config_phylib_all_drivers.h | 1 + include/configs/am335x_evm.h | 3 + include/phy.h | 1 + 6 files changed, 489 insertions(+) create mode 100644 drivers/net/phy/mscc.c -- 1.9.1

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[U-Boot] [PATCH v2 0/2] ARM: imx6ul: Support liteSOM and liteBoard
by Marcin Niestroj 07 Dec '16

07 Dec '16

Hi, These patches add support for liteSOM (http://grinn-global.com/litesom/), and liteBoard (which uses liteSOM as it's base). liteSOM consists of processor (NXP i.MX6UL), RAM memory (up to 512M DDR3) and flash (eMMC card). The idea is that every board vendor can use liteSOM as it's base for designed board. Hence, we need a way to reuse common code between those board. liteBoard is a development kit (and reference platform for liteSOM), that mainly shows possibilities and use cases of liteSOM. Patches were rebased and tested on 2017.01-rc1. Changes v1 -> v2 (only liteBoard related): * fix boot_mode values for proper bmode command usage * override default board_boot_order() and check inside it from which device (SD or eMMC) we have booted * add CONFIG_SUPPORT_EMMC_BOOT to support boot from eMMC boot partitions * move new CONFIG_* options from include/configs/liteboard.h to configs/liteboard_defconfig Marcin Niestroj (2): ARM: imx6ul: Add support for liteSOM board/liteboard: Add support for liteBoard arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/cpu/armv7/mx6/Kconfig | 5 + arch/arm/mach-litesom/Kconfig | 6 + arch/arm/mach-litesom/Makefile | 6 + arch/arm/mach-litesom/include/mach/litesom.h | 16 ++ arch/arm/mach-litesom/litesom.c | 200 +++++++++++++++++++ board/grinn/liteboard/Kconfig | 12 ++ board/grinn/liteboard/MAINTAINERS | 6 + board/grinn/liteboard/Makefile | 6 + board/grinn/liteboard/README | 31 +++ board/grinn/liteboard/board.c | 287 +++++++++++++++++++++++++++ configs/liteboard_defconfig | 29 +++ include/configs/liteboard.h | 171 ++++++++++++++++ 14 files changed, 778 insertions(+) create mode 100644 arch/arm/mach-litesom/Kconfig create mode 100644 arch/arm/mach-litesom/Makefile create mode 100644 arch/arm/mach-litesom/include/mach/litesom.h create mode 100644 arch/arm/mach-litesom/litesom.c create mode 100644 board/grinn/liteboard/Kconfig create mode 100644 board/grinn/liteboard/MAINTAINERS create mode 100644 board/grinn/liteboard/Makefile create mode 100644 board/grinn/liteboard/README create mode 100644 board/grinn/liteboard/board.c create mode 100644 configs/liteboard_defconfig create mode 100644 include/configs/liteboard.h -- 2.10.2

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[U-Boot] [PATCH 07/10] arm: socfpga: arria10: Added miscellaneous drivers for Arria10
by Chee Tien Fong 07 Dec '16

07 Dec '16

From: Tien Fong Chee <tien.fong.chee(a)intel.com> The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 respectively. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Tien Fong <skywindctf(a)gmail.com> --- arch/arm/mach-socfpga/Makefile | 4 +- arch/arm/mach-socfpga/include/mach/misc.h | 25 ++ arch/arm/mach-socfpga/misc.c | 429 +--------------------------- arch/arm/mach-socfpga/misc_arria10.c | 111 ++++++++ arch/arm/mach-socfpga/misc_gen5.c | 363 ++++++++++++++++++++++++ 5 files changed, 517 insertions(+), 415 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h create mode 100644 arch/arm/mach-socfpga/misc_arria10.c create mode 100644 arch/arm/mach-socfpga/misc_gen5.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index b8fcf6e..f8b529e 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,9 +9,9 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o board.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ - reset_manager_gen5.o + reset_manager_gen5.o misc_gen5.o ifdef CONFIG_SPL_BUILD obj-y += spl.o diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h new file mode 100644 index 0000000..1bf1783 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016, Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MISC_H_ +#define _MISC_H_ + +extern void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode); + +struct bsel{ + const char *mode; + const char *name; +}; + +extern struct bsel bsel_str[]; + +#ifdef CONFIG_FPGA +extern void socfpga_fpga_add(void); +#else +inline void socfpga_fpga_add(void) {} +#endif +#endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 00e385f..f44233d 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,51 +1,39 @@ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2016 Altera Corporation <www.altera.com> * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> #include <asm/io.h> #include <errno.h> -#include <fdtdec.h> -#include <libfdt.h> #include <altera.h> #include <miiphy.h> #include <netdev.h> #include <watchdog.h> +#include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> -#include <asm/arch/scan_manager.h> #include <asm/arch/sdram_a10.h> #include <asm/arch/system_manager.h> #include <asm/arch/nic301.h> #include <asm/arch/scu.h> #include <asm/pl310.h> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#include <dt-bindings/reset/altr,rst-mgr.h> -#else -#include <dt-bindings/reset/altr,rst-mgr-a10.h> -#endif - DECLARE_GLOBAL_DATA_PTR; -static struct pl310_regs *const pl310 = +static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_reset_manager *reset_manager_base = - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -static struct nic301_registers *nic301_regs = - (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -#else -static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = - (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; -static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = - (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; -#endif -static struct scu_registers *scu_regs = - (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; + +struct bsel bsel_str[] = { + { "rsvd", "Reserved", }, + { "fpga", "FPGA (HPS2FPGA Bridge)", }, + { "nand", "NAND Flash (1.8V)", }, + { "nand", "NAND Flash (3.0V)", }, + { "sd", "SD/MMC External Transceiver (1.8V)", }, + { "sd", "SD/MMC Internal Transceiver (3.0V)", }, + { "qspi", "QSPI Flash (1.8V)", }, + { "qspi", "QSPI Flash (3.0V)", }, +}; int dram_init(void) { @@ -84,219 +72,6 @@ void v7_outer_cache_disable(void) clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } -/* - * DesignWare Ethernet initialization - */ -#ifdef CONFIG_ETH_DESIGNWARE -static void dwmac_deassert_reset(const unsigned int of_reset_id, - const u32 phymode) -{ - u32 physhift, reset; - - if (of_reset_id == EMAC0_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; - reset = SOCFPGA_RESET(EMAC0); - } else if (of_reset_id == EMAC1_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; - reset = SOCFPGA_RESET(EMAC1); -#ifndef CONFIG_TARGET_SOCFPGA_GEN5 - } else if (of_reset_id == EMAC2_RESET) { - reset = SOCFPGA_RESET(EMAC2); -#endif - } else { - printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); - return; - } - -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) - /* configure to PHY interface select choosed */ - clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, - phymode << physhift); -#else - clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET], - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, - phymode); -#endif - - /* Release the EMAC controller from reset */ - socfpga_per_reset(reset, 0); -} - -static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) -{ - if (!phymode) - return -EINVAL; - - if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - return 0; - } - - if (!strcmp(phymode, "rgmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - return 0; - } - - if (!strcmp(phymode, "rmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - return 0; - } - - return -EINVAL; -} - -static int socfpga_eth_reset(void) -{ - const void *fdt = gd->fdt_blob; - struct fdtdec_phandle_args args; - const char *phy_mode; - u32 phy_modereg; - int nodes[2]; /* Max. two GMACs */ - int ret, count; - int i, node; - - /* Put both GMACs into RESET state. */ - socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); - socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); - - count = fdtdec_find_aliases_for_id(fdt, "ethernet", - COMPAT_ALTERA_SOCFPGA_DWMAC, - nodes, ARRAY_SIZE(nodes)); - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", - "#reset-cells", 1, 0, - &args); - if (ret || (args.args_count != 1)) { - debug("GMAC%i: Failed to parse DT 'resets'!\n", i); - continue; - } - - phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); - ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); - if (ret) { - debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); - continue; - } - - dwmac_deassert_reset(args.args[0], phy_modereg); - } - - return 0; -} -#else -static int socfpga_eth_reset(void) -{ - return 0; -}; -#endif - -struct { - const char *mode; - const char *name; -} bsel_str[] = { - { "rsvd", "Reserved", }, - { "fpga", "FPGA (HPS2FPGA Bridge)", }, - { "nand", "NAND Flash (1.8V)", }, - { "nand", "NAND Flash (3.0V)", }, - { "sd", "SD/MMC External Transceiver (1.8V)", }, - { "sd", "SD/MMC Internal Transceiver (3.0V)", }, - { "qspi", "QSPI Flash (1.8V)", }, - { "qspi", "QSPI Flash (3.0V)", }, -}; - -static const struct { - const u16 pn; - const char *name; - const char *var; -} const socfpga_fpga_model[] = { - /* Cyclone V E */ - { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, - { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, - { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, - { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, - { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, - /* Cyclone V GX/GT */ - { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, - { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, - { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, - { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, - { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, - /* Cyclone V SE/SX/ST */ - { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, - { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, - { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, - { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, - /* Arria V */ - { 0x2d03, "Arria V, D5", "av_d5" }, -}; - -static int socfpga_fpga_id(const bool print_id) -{ - const u32 altera_mi = 0x6e; - const u32 id = scan_mgr_get_fpga_id(); - - const u32 lsb = id & 0x00000001; - const u32 mi = (id >> 1) & 0x000007ff; - const u32 pn = (id >> 12) & 0x0000ffff; - const u32 version = (id >> 28) & 0x0000000f; - int i; - - if ((mi != altera_mi) || (lsb != 1)) { - printf("FPGA: Not Altera chip ID\n"); - return -EINVAL; - } - - for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) - if (pn == socfpga_fpga_model[i].pn) - break; - - if (i == ARRAY_SIZE(socfpga_fpga_model)) { - printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); - return -EINVAL; - } - - if (print_id) - printf("FPGA: Altera %s, version 0x%01x\n", - socfpga_fpga_model[i].name, version); - return i; -} - -/* - * Print CPU information - */ -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> - SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7; -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) - puts("CPU: Altera SoCFPGA Platform\n"); - socfpga_fpga_id(1); -#else - puts("CPU: Altera SoCFPGA Arria 10\n"); -#endif - printf("BOOT: %s\n", bsel_str[bsel].name); - return 0; -} -#endif - -#ifdef CONFIG_ARCH_MISC_INIT -int arch_misc_init(void) -{ - const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; - const int fpga_id = socfpga_fpga_id(0); - setenv("bootmode", bsel_str[bsel].mode); - if (fpga_id >= 0) - setenv("fpgatype", socfpga_fpga_model[fpga_id].var); - return socfpga_eth_reset(); -} -#endif - #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) int overwrite_console(void) @@ -327,15 +102,13 @@ static Altera_desc altera_fpga[] = { }; /* add device descriptor to FPGA device table */ -static void socfpga_fpga_add(void) +void socfpga_fpga_add(void) { int i; fpga_init(); for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) fpga_add(fpga_altera, &altera_fpga[i]); } -#else -static inline void socfpga_fpga_add(void) {} #endif int arch_cpu_init(void) @@ -361,173 +134,3 @@ int arch_cpu_init(void) return 0; } - -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -/* - * Convert all NIC-301 AMBA slaves from secure to non-secure - */ -static void socfpga_nic301_slave_ns(void) -{ - writel(0x1, &nic301_regs->lwhps2fpgaregs); - writel(0x1, &nic301_regs->hps2fpgaregs); - writel(0x1, &nic301_regs->acp); - writel(0x1, &nic301_regs->rom); - writel(0x1, &nic301_regs->ocram); - writel(0x1, &nic301_regs->sdrdata); -} - -static uint32_t iswgrp_handoff[8]; - -int arch_early_init_r(void) -{ - int i; - - /* - * Write magic value into magic register to unlock support for - * issuing warm reset. The ancient kernel code expects this - * value to be written into the register by the bootloader, so - * to support that old code, we write it here instead of in the - * reset_cpu() function just before reseting the CPU. - */ - writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); - - for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ - iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); - - socfpga_bridges_reset(1); - socfpga_nic301_slave_ns(); - - /* - * Private components security: - * U-Boot : configure private timer, global timer and cpu component - * access as non secure for kernel stage (as required by Linux) - */ - setbits_le32(&scu_regs->sacr, 0xfff); - - /* Configure the L2 controller to make SDRAM start at 0 */ -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET - writel(0x2, &nic301_regs->remap); -#else - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ - writel(0x1, &pl310->pl310_addr_filter_start); -#endif - - /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); - -#ifdef CONFIG_DESIGNWARE_SPI - /* Get Designware SPI controller out of reset */ - socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); - socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); -#endif - -#ifdef CONFIG_NAND_DENALI - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); -#endif - - return 0; -} - -static void socfpga_sdram_apply_static_cfg(void) -{ - const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; - const uint32_t applymask = 0x8; - uint32_t val = readl(staticcfg) | applymask; - - /* - * SDRAM staticcfg register specific: - * When applying the register setting, the CPU must not access - * SDRAM. Luckily for us, we can abuse i-cache here to help us - * circumvent the SDRAM access issue. The idea is to make sure - * that the code is in one full i-cache line by branching past - * it and back. Once it is in the i-cache, we execute the core - * of the code and apply the register settings. - * - * The code below uses 7 instructions, while the Cortex-A9 has - * 32-byte cachelines, thus the limit is 8 instructions total. - */ - asm volatile( - ".align 5 \n" - " b 2f \n" - "1: str %0, [%1] \n" - " dsb \n" - " isb \n" - " b 3f \n" - "2: b 1b \n" - "3: nop \n" - : : "r"(val), "r"(staticcfg) : "memory", "cc"); -} - -int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 2) - return CMD_RET_USAGE; - - argv++; - - switch (*argv[0]) { - case 'e': /* Enable */ - writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); - socfpga_sdram_apply_static_cfg(); - writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); - writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); - writel(iswgrp_handoff[1], &nic301_regs->remap); - break; - case 'd': /* Disable */ - writel(0, &sysmgr_regs->fpgaintfgrp_module); - writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); - socfpga_sdram_apply_static_cfg(); - writel(0, &reset_manager_base->brg_mod_reset); - writel(1, &nic301_regs->remap); - break; - default: - return CMD_RET_USAGE; - } - - return 0; -} -#else -/* -+ * This function initializes security policies to be consistent across -+ * all logic units in the Arria 10. -+ * -+ * The idea is to set all security policies to be normal, nonsecure -+ * for all units. -+ */ -static void initialize_security_policies(void) -{ - /* Put OCRAM in non-secure */ - writel(0x003f0000, &noc_fw_ocram_base->region0); - writel(0x1, &noc_fw_ocram_base->enable); - - /* Put DDR in non-secure */ - writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr); - writel(0x1, &noc_fw_ddr_l3_base->enable); -} - -int arch_early_init_r(void) -{ - initialize_security_policies(); - - /* Configure the L2 controller to make SDRAM start at 0 */ - writel(0x1, &pl310->pl310_addr_filter_start); - - /* assert reset to all except L4WD0 and L4TIMER0 */ - socfpga_per_reset_all(); - - /* configuring the clock based on handoff */ - /* TODO: Add call to cm_basic_init() */ - - /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); - return 0; -} -#endif - -U_BOOT_CMD( - bridge, 2, 1, do_bridge, - "SoCFPGA HPS FPGA bridge control", - "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "" -); diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c new file mode 100644 index 0000000..b0bc51c --- /dev/null +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2016, Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <altera.h> +#include <miiphy.h> +#include <netdev.h> +#include <watchdog.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/sdram_a10.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/nic301.h> +#include <asm/pl310.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = + (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; + +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_ETH_DESIGNWARE +void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode) +{ + u32 reset; + + if (of_reset_id == EMAC0_RESET) { + reset = SOCFPGA_RESET(EMAC0); + } else if (of_reset_id == EMAC1_RESET) { + reset = SOCFPGA_RESET(EMAC1); + } else if (of_reset_id == EMAC2_RESET) { + reset = SOCFPGA_RESET(EMAC2); + } else { + printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); + return; + } + + clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET], + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + phymode); + + /* Release the EMAC controller from reset */ + socfpga_per_reset(reset, 0); +} +#endif + +/* ++ * This function initializes security policies to be consistent across ++ * all logic units in the Arria 10. ++ * ++ * The idea is to set all security policies to be normal, nonsecure ++ * for all units. ++ */ +static void initialize_security_policies(void) +{ + /* Put OCRAM in non-secure */ + writel(0x003f0000, &noc_fw_ocram_base->region0); + writel(0x1, &noc_fw_ocram_base->enable); + + /* Put DDR in non-secure */ + writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr); + writel(0x1, &noc_fw_ddr_l3_base->enable); +} + +int arch_early_init_r(void) +{ + initialize_security_policies(); + + /* Configure the L2 controller to make SDRAM start at 0 */ + writel(0x1, &pl310->pl310_addr_filter_start); + + /* assert reset to all except L4WD0 and L4TIMER0 */ + socfpga_per_reset_all(); + + /* configuring the clock based on handoff */ + /* TODO: Add call to cm_basic_init() */ + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + return 0; +} + +/* + * Print CPU information + */ +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> + SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7; + + puts("CPU: Altera SoCFPGA Arria 10\n"); + + printf("BOOT: %s\n", bsel_str[bsel].name); + return 0; +} +#endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c new file mode 100644 index 0000000..b91aeb1 --- /dev/null +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2016, Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <altera.h> +#include <miiphy.h> +#include <netdev.h> +#include <watchdog.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/scan_manager.h> +#include <asm/arch/sdram_a10.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/nic301.h> +#include <asm/arch/scu.h> +#include <asm/pl310.h> +#include <dt-bindings/reset/altr,rst-mgr.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static struct socfpga_reset_manager *reset_manager_base = + (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; +static struct nic301_registers *nic301_regs = + (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; +static struct scu_registers *scu_regs = + (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; + +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_ETH_DESIGNWARE +void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode) +{ + u32 physhift; + u32 reset; + + if (of_reset_id == EMAC0_RESET) { + physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; + + reset = SOCFPGA_RESET(EMAC0); + } else if (of_reset_id == EMAC1_RESET) { + physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; + + reset = SOCFPGA_RESET(EMAC1); + } + else { + printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); + return; + } + + /* configure to PHY interface select choosed */ + clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, + phymode << physhift); + + /* Release the EMAC controller from reset */ + socfpga_per_reset(reset, 0); +} + +/* + * DesignWare Ethernet initialization + */ +static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) +{ + if (!phymode) + return -EINVAL; + + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + return 0; + } + + if (!strcmp(phymode, "rgmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + return 0; + } + + if (!strcmp(phymode, "rmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + return 0; + } + + return -EINVAL; +} + +static int socfpga_eth_reset(void) +{ + const void *fdt = gd->fdt_blob; + struct fdtdec_phandle_args args; + const char *phy_mode; + u32 phy_modereg; + int nodes[2]; /* Max. two GMACs */ + int ret, count; + int i, node; + + /* Put both GMACs into RESET state. */ + socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); + socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); + + count = fdtdec_find_aliases_for_id(fdt, "ethernet", + COMPAT_ALTERA_SOCFPGA_DWMAC, + nodes, ARRAY_SIZE(nodes)); + for (i = 0; i < count; i++) { + node = nodes[i]; + if (node <= 0) + continue; + + ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", + "#reset-cells", 1, 0, + &args); + if (ret || (args.args_count != 1)) { + debug("GMAC%i: Failed to parse DT 'resets'!\n", i); + continue; + } + + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); + ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); + if (ret) { + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); + continue; + } + + dwmac_deassert_reset(args.args[0], phy_modereg); + } + + return 0; +} +#else +static int socfpga_eth_reset(void) +{ + return 0; +}; +#endif + +static const struct { + const u16 pn; + const char *name; + const char *var; +} const socfpga_fpga_model[] = { + /* Cyclone V E */ + { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, + { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, + { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, + { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, + { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, + /* Cyclone V GX/GT */ + { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, + { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, + { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, + { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, + { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, + /* Cyclone V SE/SX/ST */ + { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, + { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, + { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, + { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, + /* Arria V */ + { 0x2d03, "Arria V, D5", "av_d5" }, +}; + +static int socfpga_fpga_id(const bool print_id) +{ + const u32 altera_mi = 0x6e; + const u32 id = scan_mgr_get_fpga_id(); + + const u32 lsb = id & 0x00000001; + const u32 mi = (id >> 1) & 0x000007ff; + const u32 pn = (id >> 12) & 0x0000ffff; + const u32 version = (id >> 28) & 0x0000000f; + int i; + + if ((mi != altera_mi) || (lsb != 1)) { + printf("FPGA: Not Altera chip ID\n"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) + if (pn == socfpga_fpga_model[i].pn) + break; + + if (i == ARRAY_SIZE(socfpga_fpga_model)) { + printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); + return -EINVAL; + } + + if (print_id) + printf("FPGA: Altera %s, version 0x%01x\n", + socfpga_fpga_model[i].name, version); + return i; +} + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; + const int fpga_id = socfpga_fpga_id(0); + setenv("bootmode", bsel_str[bsel].mode); + if (fpga_id >= 0) + setenv("fpgatype", socfpga_fpga_model[fpga_id].var); + return socfpga_eth_reset(); +} +#endif + +/* + * Convert all NIC-301 AMBA slaves from secure to non-secure + */ +static void socfpga_nic301_slave_ns(void) +{ + writel(0x1, &nic301_regs->lwhps2fpgaregs); + writel(0x1, &nic301_regs->hps2fpgaregs); + writel(0x1, &nic301_regs->acp); + writel(0x1, &nic301_regs->rom); + writel(0x1, &nic301_regs->ocram); + writel(0x1, &nic301_regs->sdrdata); +} + +static uint32_t iswgrp_handoff[8]; + +int arch_early_init_r(void) +{ + int i; + + /* + * Write magic value into magic register to unlock support for + * issuing warm reset. The ancient kernel code expects this + * value to be written into the register by the bootloader, so + * to support that old code, we write it here instead of in the + * reset_cpu() function just before reseting the CPU. + */ + writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); + + for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ + iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); + + socfpga_bridges_reset(1); + socfpga_nic301_slave_ns(); + + /* + * Private components security: + * U-Boot : configure private timer, global timer and cpu component + * access as non secure for kernel stage (as required by Linux) + */ + setbits_le32(&scu_regs->sacr, 0xfff); + + /* Configure the L2 controller to make SDRAM start at 0 */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET + writel(0x2, &nic301_regs->remap); +#else + writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + writel(0x1, &pl310->pl310_addr_filter_start); +#endif + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + +#ifdef CONFIG_DESIGNWARE_SPI + /* Get Designware SPI controller out of reset */ + socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); + socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); +#endif + +#ifdef CONFIG_NAND_DENALI + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); +#endif + + return 0; +} + +static void socfpga_sdram_apply_static_cfg(void) +{ + const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; + const uint32_t applymask = 0x8; + uint32_t val = readl(staticcfg) | applymask; + + /* + * SDRAM staticcfg register specific: + * When applying the register setting, the CPU must not access + * SDRAM. Luckily for us, we can abuse i-cache here to help us + * circumvent the SDRAM access issue. The idea is to make sure + * that the code is in one full i-cache line by branching past + * it and back. Once it is in the i-cache, we execute the core + * of the code and apply the register settings. + * + * The code below uses 7 instructions, while the Cortex-A9 has + * 32-byte cachelines, thus the limit is 8 instructions total. + */ + asm volatile( + ".align 5 \n" + " b 2f \n" + "1: str %0, [%1] \n" + " dsb \n" + " isb \n" + " b 3f \n" + "2: b 1b \n" + "3: nop \n" + : : "r"(val), "r"(staticcfg) : "memory", "cc"); +} + +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + argv++; + + switch (*argv[0]) { + case 'e': /* Enable */ + writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); + socfpga_sdram_apply_static_cfg(); + writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); + writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); + writel(iswgrp_handoff[1], &nic301_regs->remap); + break; + case 'd': /* Disable */ + writel(0, &sysmgr_regs->fpgaintfgrp_module); + writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); + socfpga_sdram_apply_static_cfg(); + writel(0, &reset_manager_base->brg_mod_reset); + writel(1, &nic301_regs->remap); + break; + default: + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + bridge, 2, 1, do_bridge, + "SoCFPGA HPS FPGA bridge control", + "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "" +); + +/* + * Print CPU information + */ +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> + SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7; + + puts("CPU: Altera SoCFPGA Platform\n"); + socfpga_fpga_id(1); + + printf("BOOT: %s\n", bsel_str[bsel].name); + return 0; +} +#endif -- 1.7.7.4

5 6

[U-Boot] [PATCH 0/6] mmc: move some config options to Kconfig
by Masahiro Yamada 07 Dec '16

07 Dec '16

3 17

[U-Boot] [PATCH v4 0/6] Add ARMv8 PSCI framework
by Hongbo Zhang 07 Dec '16

07 Dec '16

v3-v4 changes: - Re-added the 1/6 from v2, and move the newly re-named macro into Kconfig - Add "Reviewed-by: Tom Rini <trini(a)konsulko.com>" for patch 4/6 ~ 6/6. v2-v3 changes: - Drop the previous 1/6, since the previous CONFIG_ARMV8_PSCI in common parts of codes also work for generic PSCI framework, so there are 5 patches in this iteration. - Add "Reviewed-by: Tom Rini <trini(a)konsulko.com>" for patches 1/5 and 2/5, which were 2/6 and 3/6. - Move config values for ls1043 from armv8/Kconfig to s1043ardb_defconfig. v1-v2 changes: - The new config options are introduced in Kconfig when used for first time - Introduce new config options in armv8/Kconfig instead of LS1043 platform - Move previous patch 5/6 to current 2/6 place v1 notes: This patch set introduces ARMv8 PSCI framework, all the PSCI functions are implemented a default dummy one, it is up to each platform to implement their own specific ones. The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. The last 6/6 adds a most simple implementation on NXP LS1043 platform, to verify this framework. This patch set mainly introduces ARMv8 PSCI framework, for easier review and merge, further PSCI implementation on LS1043 is coming later. Hongbo Zhang (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Enable SMC instruction ARMv8: Add secure sections for PSCI text and data ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and device tree ARMv8: LS1043A: Enable LS1043A default PSCI support arch/arm/config.mk | 3 +- arch/arm/cpu/armv8/Kconfig | 41 ++++ arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/cpu-dt.c | 11 +- arch/arm/cpu/armv8/cpu.c | 22 ++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 20 ++ arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 +- arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 ++ arch/arm/cpu/armv8/psci.S | 286 +++++++++++++++++++++++ arch/arm/cpu/armv8/sec_firmware.c | 2 +- arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- arch/arm/cpu/armv8/u-boot.lds | 57 +++++ arch/arm/include/asm/armv8/sec_firmware.h | 2 +- arch/arm/include/asm/macro.h | 2 +- arch/arm/include/asm/psci.h | 15 ++ arch/arm/include/asm/secure.h | 2 +- arch/arm/include/asm/system.h | 11 + arch/arm/lib/bootm-fdt.c | 3 +- arch/arm/lib/bootm.c | 3 + arch/arm/lib/psci-dt.c | 5 +- board/freescale/ls1043ardb/Kconfig | 9 + configs/ls1043ardb_defconfig | 3 + include/configs/ls1043ardb.h | 1 - 25 files changed, 515 insertions(+), 13 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S create mode 100644 arch/arm/cpu/armv8/psci.S -- 2.1.4

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[U-Boot] [PATCHv4 01/16] configs: ls1021a: enable DT and DM support
by Zhiqiang Hou 07 Dec '16

07 Dec '16

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Enable DT to support Driver Model. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- V4: - No change configs/ls1021aqds_nand_defconfig | 3 +++ configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_sdcard_ifc_defconfig | 3 +++ 5 files changed, 12 insertions(+) diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index e28aa48..5c52c3f 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_FSL_DDR3=y @@ -13,6 +14,7 @@ CONFIG_VIDEO=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_NAND_BOOT=y @@ -38,6 +40,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_PCI=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 8b869fa..16dc8bb 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -1,11 +1,13 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SYS_FSL_DDR3=y CONFIG_VIDEO=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SECURE_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 946945f..71681a6 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -1,11 +1,13 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_VIDEO=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_OF_CONTROL=y CONFIG_SECURE_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 5e74645..aa8c4f9 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y @@ -12,6 +13,7 @@ CONFIG_VIDEO=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_SECURE_BOOT=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 22be22c..1c79d58 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y @@ -11,6 +12,7 @@ CONFIG_VIDEO=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_SD_BOOT=y @@ -35,6 +37,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_PCI=y -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 00/17] arm: mvebu: Add gdsys ControlCenter-Compact board
by Mario Six 07 Dec '16

07 Dec '16

This patch series adds support for the Guntermann & Drunck ControlCenter-Compact board. To this extent, some bugs in the mvebu PCI driver are fixed, a GPIO driver is added, support for the Marvell 88E1680 is added, the TPM library is extended, the kwbimage generation is streamlined, a board function for manipulating the device tree is added, and secure boot for the mvebu architecture is implemented. Dirk Eibach (4): pci: mvebu: Fix Armada 38x support arm: mvebu: Add gpio support net: phy: Support Marvell 88E1680 arm: mvebu: Add gdsys ControlCenter-Compact board Mario Six (12): mvebu: Add board_pex_config() dm: Add callback to modify the device tree lib: tpm: Add command to flush resources tools: kwbimage: Fix dest addr tools: kwbimage: Fix style violations tools: kwbimage: Fix arithmetic with void pointers tools: kwbimage: Reduce scope of variables tools: kwbimage: Remove unused parameter tools: kwbimage: Factor out add_binary_header_v1 tools: kwbimage: Refactor line parsing and fix error arm: mvebu: Implement secure boot controlcenterdc: Make secure boot available Reinhard Pfau (1): arm: mvebu: spl.c: Remove useless gd declaration Makefile | 3 +- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/controlcenterdc.dts | 629 ++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 24 + arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/efuse.c | 293 ++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 2 + arch/arm/mach-mvebu/include/mach/efuse.h | 71 ++ arch/arm/mach-mvebu/include/mach/gpio.h | 41 +- arch/arm/mach-mvebu/include/mach/soc.h | 1 + arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 10 + arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 2 + arch/arm/mach-mvebu/spl.c | 2 - board/gdsys/38x/.gitignore | 1 + board/gdsys/38x/Kconfig | 51 ++ board/gdsys/38x/MAINTAINERS | 7 + board/gdsys/38x/Makefile | 45 ++ board/gdsys/38x/README | 18 + board/gdsys/38x/controlcenterdc.c | 717 ++++++++++++++++++ board/gdsys/38x/dt_helpers.c | 60 ++ board/gdsys/38x/dt_helpers.h | 16 + board/gdsys/38x/hre.c | 517 +++++++++++++ board/gdsys/38x/hre.h | 38 + board/gdsys/38x/keyprogram.c | 158 ++++ board/gdsys/38x/keyprogram.h | 14 + board/gdsys/38x/kwbimage.cfg.in | 40 + board/gdsys/38x/spl.c | 21 + board/gdsys/p1022/controlcenterd-id.c | 9 - common/board_f.c | 3 + configs/controlcenterdc_defconfig | 54 ++ drivers/net/phy/marvell.c | 51 ++ drivers/pci/pci_mvebu.c | 25 +- dts/Kconfig | 10 + include/asm-generic/global_data.h | 4 + include/common.h | 1 + include/configs/controlcenterdc.h | 244 +++++++ include/tpm.h | 45 ++ lib/tpm.c | 28 + tools/Makefile | 6 +- tools/kwbimage.c | 1091 ++++++++++++++++++++++++---- tools/kwbimage.h | 37 + 42 files changed, 4216 insertions(+), 178 deletions(-) create mode 100644 arch/arm/dts/controlcenterdc.dts create mode 100644 arch/arm/mach-mvebu/efuse.c create mode 100644 arch/arm/mach-mvebu/include/mach/efuse.h create mode 100644 board/gdsys/38x/.gitignore create mode 100644 board/gdsys/38x/Kconfig create mode 100644 board/gdsys/38x/MAINTAINERS create mode 100644 board/gdsys/38x/Makefile create mode 100644 board/gdsys/38x/README create mode 100644 board/gdsys/38x/controlcenterdc.c create mode 100644 board/gdsys/38x/dt_helpers.c create mode 100644 board/gdsys/38x/dt_helpers.h create mode 100644 board/gdsys/38x/hre.c create mode 100644 board/gdsys/38x/hre.h create mode 100644 board/gdsys/38x/keyprogram.c create mode 100644 board/gdsys/38x/keyprogram.h create mode 100644 board/gdsys/38x/kwbimage.cfg.in create mode 100644 board/gdsys/38x/spl.c create mode 100644 configs/controlcenterdc_defconfig create mode 100644 include/configs/controlcenterdc.h -- 2.9.0

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