December 2016 - U-Boot

[U-Boot] How to make I2C probe like commands working in u-boot
by lsunkara 08 Dec '16

08 Dec '16

Hi, Am trying to validate I2C peripheral on xilinx zynq zc702 evaluation board in u-boot. When am trying to run the command like i2c probe and i2c write am facing the issue like i2c commands are not known. Please can someone tell me how to enable these commands to use it in u-boot -- View this message in context: http://u-boot.10912.n7.nabble.com/How-to-make-I2C-probe-like-commands-worki… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 08 Dec '16

08 Dec '16

The following changes since commit 3cfb67d0419c645998b440592d8c2ce010134b8e: Prepare v2017.01-rc1 (2016-12-05 18:36:23 -0500) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to 555a347209000f8655ca637a5a04f7275a2fb999: usb: xhci-pci: Add DM support (2016-12-06 01:54:26 +0100) ---------------------------------------------------------------- Stefan Roese (1): usb: xhci-pci: Add DM support drivers/usb/host/xhci-pci.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+)

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[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 08 Dec '16

08 Dec '16

The following changes since commit 3cfb67d0419c645998b440592d8c2ce010134b8e: Prepare v2017.01-rc1 (2016-12-05 18:36:23 -0500) are available in the git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to f22dede20bb57195330ef11e148ca2b5f1280b2e: MAINTAINERS: Fix ALTERA SOCFPGA Files (2016-12-06 01:45:58 +0100) ---------------------------------------------------------------- Anatolij Gustschin (1): socfpga: add support for Terasic DE1-SoC board Bill Randle (1): qts-filter.sh: strip DOS line endings and handle continuation lines Dinh Nguyen (1): MAINTAINERS: socfpga: update email address for Dinh Nguyen Jagan Teki (1): MAINTAINERS: Fix ALTERA SOCFPGA Files Marek Vasut (1): ARM: socfpga: Add boot0 hook to prevent SPL corruption MAINTAINERS | 3 +- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 66 ++++++++++ arch/arm/mach-socfpga/Kconfig | 7 + arch/arm/mach-socfpga/include/mach/boot0.h | 28 ++++ arch/arm/mach-socfpga/qts-filter.sh | 47 ++++--- board/altera/arria5-socdk/MAINTAINERS | 2 +- board/altera/cyclone5-socdk/MAINTAINERS | 2 +- board/terasic/de0-nano-soc/MAINTAINERS | 2 +- board/terasic/de1-soc/MAINTAINERS | 5 + board/terasic/de1-soc/Makefile | 9 ++ board/terasic/de1-soc/qts/iocsr_config.h | 660 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/terasic/de1-soc/qts/pinmux_config.h | 219 +++++++++++++++++++++++++++++++ board/terasic/de1-soc/qts/pll_config.h | 91 +++++++++++++ board/terasic/de1-soc/qts/sdram_config.h | 344 +++++++++++++++++++++++++++++++++++++++++++++++++ board/terasic/de1-soc/socfpga.c | 19 +++ configs/socfpga_de1_soc_defconfig | 50 ++++++++ doc/git-mailrc | 3 +- include/configs/socfpga_de1_soc.h | 57 +++++++++ 20 files changed, 1595 insertions(+), 21 deletions(-) create mode 100644 arch/arm/dts/socfpga_cyclone5_de1_soc.dts create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h create mode 100644 board/terasic/de1-soc/MAINTAINERS create mode 100644 board/terasic/de1-soc/Makefile create mode 100644 board/terasic/de1-soc/qts/iocsr_config.h create mode 100644 board/terasic/de1-soc/qts/pinmux_config.h create mode 100644 board/terasic/de1-soc/qts/pll_config.h create mode 100644 board/terasic/de1-soc/qts/sdram_config.h create mode 100644 board/terasic/de1-soc/socfpga.c create mode 100644 configs/socfpga_de1_soc_defconfig create mode 100644 include/configs/socfpga_de1_soc.h

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[U-Boot] [PATCH v3 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D4
by Wenyou Yang 08 Dec '16

08 Dec '16

The purpose of the patchset is add the dts files for boards, sama5d4 Xplained board and sama5d4ek board. Changes in v3: - Fix the compatible of spi flash, use "spi-flash". - Fix the compatible of spi flash, use "spi-flash". Changes in v2: - Remove unneeded the pinctrl node for cs pin of spi0. - Remove unneeded the pinctrl node for cs pin of spi0. Wenyou Yang (2): ARM: dts: at91: add dts files for sama5d4 Xplained ARM: dts: at91: add dts file for sama5d4ek arch/arm/dts/Makefile | 6 + arch/arm/dts/at91-sama5d4_xplained.dts | 279 +++++ arch/arm/dts/at91-sama5d4ek.dts | 334 ++++++ arch/arm/dts/sama5d4.dtsi | 1910 ++++++++++++++++++++++++++++++++ 4 files changed, 2529 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d4_xplained.dts create mode 100644 arch/arm/dts/at91-sama5d4ek.dts create mode 100644 arch/arm/dts/sama5d4.dtsi -- 2.7.4

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[U-Boot] VAR-SOM-MX6 - Boot Count Limit support?
by brendan 08 Dec '16

08 Dec '16

Hello, I have a VAR-SOM-MX6 with the following details: Board: Variscite VAR_SOM_MX6 SOM-Solo SOC_FAMILY = "mx6:mx6q:mx6dl" PREFERRED_PROVIDER_virtual/kernel_var-som-mx6 ?= "linux-variscite" PREFERRED_VERSION_linux-imx_mx6 = "4.1.15" and the following u-boot details: U-Boot SPL 2013.10-00027-g58782ac (Mar 09 2015 - 13:33:44) i.MX6SOLO SOC DDR EEPROM configuration Part number: VSM-SOLO-102 Assembly: AS151004858 Date: 2016 Feb 08 Ram size 1024 Boot Device: NAND NAND: 512 MiB U-Boot 2013.10-00027-g58782ac (Mar 09 2015 - 13:33:44) CPU: Freescale i.MX6SOLO rev1.2 at 792 MHz CPU: Temperature 51 C, calibration data: 0x5744e269 Reset cause: POR Board: Variscite VAR_SOM_MX6 SOM-Solo I2C: ready DRAM: 1 GiB NAND: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Board: Variscite VAR_SOM_MX6 SOM-Solo Net: using phy at 7 I am using Yocto to create my images (.swu) to update my board through swupdate <https://sbabic.github.io/swupdate/swupdate.html> . The update process and loading process via NFS and NAND causes no issues. I am trying to implement a system whereby if the board fails to boot, it should boot to a recovery configuration where the user is presented with the swupdate landing page to allow for an image (.swu) upload to update or boot to a recovery .img (uImage, .dtb, rootfs stored on MMC or NAND). I have read about uboot's Boot Count Limit <http://www.denx.de/wiki/view/DULG/UBootBootCountLimit> which is along the lines of what I would like to implement i.e. after x failed boot attempts use an alternate boot action. However this functionality is not supported by my board. I am new to this and was wondering if anyone could shed any light on what I need to look at or how I can somehow implement the Boot Count Limit functionality or similar. Thanks for your help. -- View this message in context: http://u-boot.10912.n7.nabble.com/VAR-SOM-MX6-Boot-Count-Limit-support-tp27… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PATCH][v2] armv8: fsl-layerscape: Add support of GPIO structure
by Prabhakar Kushwaha 08 Dec '16

08 Dec '16

Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers.t rebase --continue Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Incorporated York's comments - Removed CONFIG_SYS_GPIO1_ADDR as bool - Renamed CONFIG_SYS_GPIO1_ADDR This structure is required while supporting ethernent in LS1012AFRDM. arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d684a07..f58be96 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -52,6 +52,11 @@ #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) +#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x300000) +#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x310000) +#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x320000) +#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x330000) + #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) @@ -588,6 +593,16 @@ struct ccsr_cci400 { u8 res_e004[0x10000 - 0xe004]; }; +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) #define SMMU_SCR1 (SMMU_BASE + 0x4) -- 2.7.4

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[U-Boot] Warm reset problems in U-Boot
by Oehen, Marcel 08 Dec '16

08 Dec '16

Dear sir or madam, We are using an Altera cyclone V SoC FPGA and have a problem on warm reset in the U-Boot environment. I would be very grateful if you could send this e-mail to a responsible person. It is possible to answer in English or German. Kind regards, Marcel Oehen Siemens Schweiz AG Mobility Hammerweg 1 8304 Wallisellen, Switzerland Tel.: +41 585 580930 mailto:marcel.oehen@siemens.com, www.siemens.ch<http://www.siemens.ch> www.siemens.com/ingenuityforlife<https://siemens.com/ingenuityforlife> Important notice: This e-mail and any attachment thereof contain corporate proprietary information. If you have received it by mistake, please notify us immediately by reply e-mail and delete this e-mail and its attachments from your system. Thank you. PROBLEM: After a warm reset, we can not reconfigurate the FPGA over a "Altera Remote Update IP Core" in the uboot environment. If we read or write data from/to the base address 0xc0060000 (0xc0000000 HPS2FPGA AXI Bridge + 0x60000 Remote Update IP Core) we get the message in the uboot console and it is doing a reset: ******************************************************************************** * Error Message ******************************************************************************** data abort MAYBE you should read doc/README.arm-unaligned-accesses pc : [<0ff9a570>] lr : [<0ff9a565>] sp : 0ff325f8 ip : 00000002 fp : 0ff33868 r10: 0ff33888 r9 : 00000001 r8 : 0ff32f60 r7 : 0ff32616 r6 : 00000000 r5 : 0ff32617 r4 : 00780000 r3 : c0000000 r2 : 00000076 r1 : 0000000a r0 : 00000014 Flags: nzcv IRQs on FIQs off Mode SVC_32 Resetting CPU ... resetting ... U-Boot SPL 2013.01.01-svn2322 (Dec 06 2016 - 12:04:55) BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 50000 KHz ...... ...... ******************************************************************************** GENERAL INFORMATION: We have all our software images stored in a QSPI flash (Preloader, DeviceTree, Uboot, SW-Image 0, SW-Image1, SW-Image2) except the fpga image is in the EPCQ flash (Addr: 0x0 FPGA-Image0, Addr: 0x780000 FPGA-Image1). After a cold resest the preloader will be loaded after the uboot. The uboot write into the RU_PAGE_SELECT register (base address: 0xc006000C) from the "Altera Remote Update IP Core" the address of the FPGA-Image0 (0x780000) and triggers a reconfiguration with writing "1" into the RU_RECONFIG register. The fpga reconfiguration is working and the kernel is booting one of these 3 software images. When we are doing a reboot (shutdown -r) the device is doing a warm reset. (side note: we had a problem to reboot the device with a 4Bit QSPI flash. We adapted our hardware and resets the QSPI flash with the nRST signal -> We changed the default value to 0x20000 (rstmgr, register counts, name nrstcnt = 0x20000). WHAT WE TRIED: We tried to reconfigure (cf. "Reconfig FPGA!...") the fpga with a *.rbf stored on the sd card + we disable and enable all bridges. This works fine on a warm and cold reset (cf. "fpga Status register: mode 0x4" -> FPGA in User Mode). After the console print ("START -------------") we are reading the register from a region global register and from the Altera Remote Update IP core the RU_PAGE_SELECT regsiter write 0x780000 into this register and triggers a reconfiguration. But this works only on a cold reset! ******************************************************************************** * Cold reset start up ******************************************************************************** U-Boot 2013.01.01 (Dec 07 2016 - 14:19:06) CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone V Board I2C: ready DRAM: 256 MiB MMC: ALTERA DWMMC: 0 SF: Read data capture delay calibrated to 4 (1 - 7) SF: Detected N25Q00 with page size 65536, total: 134217728 In: serial Out: serial Err: serial Skipped ethaddr assignment due to invalid EMAC address in EEPROM Net: mii0 Warning: failed to set MAC address Hit any key to stop autoboot: 0 set cycles tmp1: 0x200000a fpga Status register: 0x9c Reconfig FPGA!... ## Starting application at 0x0FF78550 ... ## Application terminated, rc = 0x0 reading output_file_128.rbf 4244820 bytes read in 236 ms (17.2 MiB/s) ## Starting application at 0x0FF78550 ... ## Application terminated, rc = 0x0 done! fpga Status register: mode 0x4 fpga Status register: msel 0x13 Cold reset detected! ENV_NAME_BOOT_MODE: 0 reconfiguration GW factory START ------------- (1xx) RegionGlobal: 0x0 (2xx) RU_PAGE_SELECT: 0x0 (1) epcqGatewareImageAddress: 0x780000 (2*) (2) (3) (4) (5) RU_RECONFIG_TRIGGER_CONDITIONS: 0x4 RU_PAGE_SELECT: 0x0 ********************************************** SND-Settings qspibootimageaddr: 0x400000 snd_statusSoftwareFactory: 0 snd_statusSoftwareUpdated0: 1 snd_statusSoftwareUpdated1: 1 snd_versionSoftwareFactory: - snd_versionSoftwareUpdated0: - snd_versionSoftwareUpdated1: - snd_watchdogOccurred: 0 ********************************************** ## Starting application at 0x0FF78550 ... ## Application terminated, rc = 0x0 SF: Detected N25Q00 with page size 65536, total: 134217728 ## Booting kernel from Legacy Image at 00007fc0 ... Image Name: Linux kernel Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 16114704 Bytes = 15.4 MiB Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... OK ## Flattened Device Tree blob at 00000100 Booting using the fdt blob at 0x00000100 XIP Kernel Image ... OK OK Loading Device Tree to 03ff6000, end 03fff058 ... OK Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 ******************************************************************************** After a warm reset we have no access to the fpga over the Altera Remote Update IP core, although its the same uboot softwarecode! ******************************************************************************** * WARM reset start up ******************************************************************************** U-Boot SPL 2013.01.01-svn2322 (Dec 06 2016 - 12:04:55) BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 50000 KHz CLOCK: EOSC2 clock 50000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 800 MHz CLOCK: DDR clock 400 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 50000 KHz CLOCK: QSPI clock 400000 KHz RESET: WARM SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 256 MiB SF: Read data capture delay calibrated to 4 (1 - 7) SF: Detected N25Q00 with page size 65536, total: 134217728 U-Boot 2013.01.01 (Dec 07 2016 - 14:19:06) CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone V Board I2C: ready DRAM: 256 MiB MMC: ALTERA DWMMC: 0 SF: Read data capture delay calibrated to 4 (1 - 7) SF: Detected N25Q00 with page size 65536, total: 134217728 In: serial Out: serial Err: serial Skipped ethaddr assignment due to invalid EMAC address in EEPROM Net: mii0 Warning: failed to set MAC address Hit any key to stop autoboot: 0 set cycles tmp1: 0x200000a fpga Status register: 0x9c Reconfig FPGA!... ## Starting application at 0x0FF78550 ... ## Application terminated, rc = 0x0 reading output_file_128.rbf 4244820 bytes read in 236 ms (17.2 MiB/s) ## Starting application at 0x0FF78550 ... ## Application terminated, rc = 0x0 done! fpga Status register: mode 0x4 fpga Status register: msel 0x13 Warm reset detected! ENV_NAME_BOOT_MODE: 0 do FPGA reset reconfiguration GW factory START ------------- data abort MAYBE you should read doc/README.arm-unaligned-accesses pc : [<0ff9a570>] lr : [<0ff9a565>] sp : 0ff325f8 ip : 00000002 fp : 0ff33868 r10: 0ff33888 r9 : 00000001 r8 : 0ff32f60 r7 : 0ff32616 r6 : 00000000 r5 : 0ff32617 r4 : 00780000 r3 : c0000000 r2 : 00000076 r1 : 0000000a r0 : 00000014 Flags: nzcv IRQs on FIQs off Mode SVC_32 Resetting CPU ... resetting ... U-Boot SPL 2013.01.01-svn2322 (Dec 06 2016 - 12:04:55) BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 50000 KHz CLOCK: EOSC2 clock 50000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 800 MHz CLOCK: DDR clock 400 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 50000 KHz CLOCK: QSPI clock 400000 KHz RESET: WARM SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 256 MiB SF: Read data capture delay calibrated to 4 (1 - 7) SF: Detected N25Q00 with page size 65536, total: 134217728 U-Boot 2013.01.01 (Dec 07 2016 - 14:19:06) CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone V Board I2C: ready DRAM: 256 MiB MMC: ALTERA DWMMC: 0 SF: Read data capture delay calibrated to 4 (1 - 7) SF: Detected N25Q00 with page size 65536, total: 134217728 In: serial Out: serial Err: serial Skipped ethaddr assignment due to invalid EMAC address in EEPROM Net: mii0 Warning: failed to set MAC address Hit any key to stop autoboot: 0 SOCFPGA_CYCLONE5 # ******************************************************************************** This is the code snippet where the error occurs. ******************************************************************************** * Imported code snippet ******************************************************************************** #define ARU_BASE_ADDRESS 0xc0060000 #define FPGA_BASE_ADDRESS 0xc0000000 printf("START -------------\n"); tmp32 = (uint32_t) ioread32(FPGA_BASEADDRESS); printf("(1xx) RegionGlobal: 0x%x\n", tmp32); printf("(2xx) RU_PAGE_SELECT: 0x%x\n", ioread32(ALTREMOTE_BASE_ADDRESS + RU_PAGE_SELECT)); ******************************************************************************** We have no idea why we have not access to the FPGA over the Altera Remote Update IP Core. Please let me know if you need more details.

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[U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
by Vignesh R 08 Dec '16

08 Dec '16

According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts. So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr(a)ti.com> --- v2: - Use bounce buffer - Link to v1: https://patchwork.ozlabs.org/patch/693069/ drivers/spi/cadence_qspi_apb.c | 26 ++++++++++++++++++++------ include/configs/k2g_evm.h | 1 + include/configs/socfpga_common.h | 1 + include/configs/stv0991.h | 1 + 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e285d3c1e761..6ce98acf747d 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -30,6 +30,7 @@ #include <linux/errno.h> #include <wait_bit.h> #include <spi.h> +#include <bouncebuf.h> #include "cadence_qspi.h" #define CQSPI_REG_POLL_US (1) /* 1us */ @@ -741,6 +742,17 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, unsigned int remaining = n_tx; unsigned int write_bytes; int ret; + struct bounce_buffer bb; + u8 *bb_txbuf; + + /* + * Handle non-4-byte aligned accesses via bounce buffer to + * avoid data abort. + */ + ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ); + if (ret) + return ret; + bb_txbuf = bb.bounce_buffer; /* Configure the indirect read transfer bytes */ writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); @@ -751,11 +763,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; - /* Handle non-4-byte aligned access to avoid data abort. */ - if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) - writesb(plat->ahbbase, txbuf, write_bytes); - else - writesl(plat->ahbbase, txbuf, write_bytes >> 2); + writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2); + if (write_bytes % 4) + writesb(plat->ahbbase, + bb_txbuf + rounddown(write_bytes, 4), + write_bytes % 4); ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, CQSPI_REG_SDRAMLEVEL_WR_MASK << @@ -765,7 +777,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, goto failwr; } - txbuf += write_bytes; + bb_txbuf += write_bytes; remaining -= write_bytes; } @@ -776,6 +788,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, printf("Indirect write completion error (%i)\n", ret); goto failwr; } + bounce_buffer_stop(&bb); /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE_MASK, @@ -786,6 +799,7 @@ failwr: /* Cancel the indirect write */ writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, plat->regbase + CQSPI_REG_INDIRECTWR); + bounce_buffer_stop(&bb); return ret; } diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index a14544526c71..1d603e0c002f 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -79,6 +79,7 @@ #define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_REF_CLK 384000000 #define CONFIG_CQSPI_DECODER 0x0 +#define CONFIG_BOUNCE_BUFFER #endif #endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d37e5958b586..2de57b063334 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -208,6 +208,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif #define CONFIG_CQSPI_DECODER 0 +#define CONFIG_BOUNCE_BUFFER /* * Designware SPI support diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index bfd1bd719285..09a3064bd6d6 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -74,6 +74,7 @@ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 +#define CONFIG_BOUNCE_BUFFER #endif -- 2.10.2

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[U-Boot] net: e1000: support for intel 82579
by Markus Valentin 08 Dec '16

08 Dec '16

Hi, did somebody already did some effort to support the intel 82579 Gigabit Ethernet PHY with the e1000 driver? In my naive try to add it i had no success yet. Regards Markus

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[U-Boot] [PATCH 1/2] mmc: fsl_esdhc: move 'status' property fixup into a weak function
by Yangbo Lu 08 Dec '16

08 Dec '16

Move fdt fixup of 'status' property into a weak function. This allows board to define 'status' fdt fixup by themselves. Signed-off-by: Yangbo Lu <yangbo.lu(a)nxp.com> --- drivers/mmc/fsl_esdhc.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0ae1cfd..7b7863f 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -911,17 +911,26 @@ void mmc_adapter_card_type_ident(void) #endif #ifdef CONFIG_OF_LIBFDT -void fdt_fixup_esdhc(void *blob, bd_t *bd) +__weak int esdhc_status_fixup(void *blob, const char *compat) { - const char *compat = "fsl,esdhc"; - #ifdef CONFIG_FSL_ESDHC_PIN_MUX if (!hwconfig("esdhc")) { do_fixup_by_compat(blob, compat, "status", "disabled", - 8 + 1, 1); - return; + sizeof("disabled"), 1); + return 1; } #endif + do_fixup_by_compat(blob, compat, "status", "okay", + sizeof("okay"), 1); + return 0; +} + +void fdt_fixup_esdhc(void *blob, bd_t *bd) +{ + const char *compat = "fsl,esdhc"; + + if (esdhc_status_fixup(blob, compat)) + return; #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", @@ -934,8 +943,6 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, compat, "adapter-type", (u32)(gd->arch.sdhc_adapter), 1); #endif - do_fixup_by_compat(blob, compat, "status", "okay", - 4 + 1, 1); } #endif -- 2.1.0.27.g96db324

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