December 2016 - U-Boot

[U-Boot] [PATCH v3] Kconfig: Move USE_ARCH_MEMCPY/MEMSET to Kconfig
by Fabio Estevam 17 Dec '16

17 Dec '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> Move USE_ARCH_MEMCPY/MEMSET options to Kconfig. Make it "default y" for the ARMv7 architecture and make it depend on !ARM64 && !SPL. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- Changes since v2: - Move it to arch/arm/Kconfig - Change default and depends logic arch/arm/Kconfig | 18 ++++++++++++++++++ include/configs/armadillo-800eva.h | 2 -- include/configs/blanche.h | 3 --- include/configs/colibri_imx7.h | 2 -- include/configs/colibri_vf.h | 2 -- include/configs/exynos-common.h | 3 --- include/configs/pcm052.h | 1 - include/configs/tegra-common.h | 6 ------ include/configs/uniphier.h | 5 ----- include/configs/vf610twr.h | 1 - 10 files changed, 18 insertions(+), 25 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 714dd8b..b15f13f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -126,6 +126,24 @@ config ENABLE_ARM_SOC_BOOT0_HOOK ARM_SOC_BOOT0_HOOK which contains the required assembler preprocessor code. +config USE_ARCH_MEMCPY + bool "Use an assembly optimized implementation of memcpy" + default y if CPU_V7 + depends on !ARM64 && !SPL + help + Enable the generation of an optimized version of memcpy. + Such implementation may be faster under some conditions + but may increase the binary size. + +config USE_ARCH_MEMSET + bool "Use an assembly optimized implementation of memset" + default y if CPU_V7 + depends on !ARM64 && !SPL + help + Enable the generation of an optimized version of memset. + Such implementation may be faster under some conditions + but may increase the binary size. + config ARCH_OMAP2 bool select CPU_V7 diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 2d24253..3775a49 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -28,8 +28,6 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_USE_ARCH_MEMSET -#define CONFIG_USE_ARCH_MEMCPY #define CONFIG_TMU_TIMER #define CONFIG_SYS_DCACHE_OFF diff --git a/include/configs/blanche.h b/include/configs/blanche.h index f094bbe..0deb350 100755 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -16,9 +16,6 @@ #include "rcar-gen2-common.h" -#define CONFIG_USE_ARCH_MEMSET -#define CONFIG_USE_ARCH_MEMCPY - /* STACK */ #define CONFIG_SYS_INIT_SP_ADDR 0xE817FFFC #define STACK_AREA_SIZE 0xC000 diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 5ce0a34..bc3b53b 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -15,8 +15,6 @@ #include "mx7_common.h" #define CONFIG_SYS_THUMB_BUILD -#define CONFIG_USE_ARCH_MEMCPY -#define CONFIG_USE_ARCH_MEMSET /*#define CONFIG_DBG_MONITOR*/ #define PHYS_SDRAM_SIZE SZ_512M diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index d58145e..47dea62 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -16,8 +16,6 @@ #define CONFIG_VF610 #define CONFIG_SYS_THUMB_BUILD -#define CONFIG_USE_ARCH_MEMCPY -#define CONFIG_USE_ARCH_MEMSET #define CONFIG_SYS_FSL_CLK #define CONFIG_ARCH_MISC_INIT diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 3b61a41..566f246 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -20,9 +20,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_USE_ARCH_MEMCPY -#define CONFIG_USE_ARCH_MEMSET - /* Keep L2 Cache Disabled */ /* input clock of PLL: 24MHz input clock */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index eb1944a..e70c3f0 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -35,7 +35,6 @@ #define CONFIG_SYS_NAND_ONFI_DETECTION #ifdef CONFIG_CMD_NAND -#define CONFIG_USE_ARCH_MEMCPY #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 63b711b..23a0e78 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -76,12 +76,6 @@ #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) -#ifndef CONFIG_ARM64 -#ifndef CONFIG_SPL_BUILD -#define CONFIG_USE_ARCH_MEMCPY -#endif -#endif - /*----------------------------------------------------------------------- * Physical Memory Map */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index f9c9f82..74f1373 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -63,11 +63,6 @@ /* serial console configuration */ #define CONFIG_BAUDRATE 115200 -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) -#define CONFIG_USE_ARCH_MEMSET -#define CONFIG_USE_ARCH_MEMCPY -#endif - #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* add command line history */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index af5ba61..6aeb078 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_NAND_ONFI_DETECTION #ifdef CONFIG_CMD_NAND -#define CONFIG_USE_ARCH_MEMCPY #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR -- 2.7.4

2 2

[U-Boot] Please pull u-boot-fsl-qoriq master
by york sun 17 Dec '16

17 Dec '16

Tom, The following changes since commit 53e8ca22538c2cec691fe74098684a359302688c: MAINTAINERS: DFU: Change e-mail address for DFU maintainer (2016-12-12 13:03:15 -0500) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git for you to fetch changes up to c151cb5b516e609a0846bd392d6207a77b66a7ff: ARMv8: LS1043A: Enable LS1043A default PSCI support (2016-12-15 11:57:56 -0800) ---------------------------------------------------------------- Hou Zhiqiang (2): armv8: ls1043ardb: dts: Fix the unit-address of some I2C device nodes armv8: ls1043a: dts: Fix the ranges table of IFC node Priyanka Jain (1): driver: fsl-mc: qbman: Add QBMAN 4.1 support Shengzhou Liu (2): fsl/ddr: Enable erratum-a009942 workaround for B/T-series fsl/board/ddr: optimize board-specific cpo for erratum A-009942 macro.wave.z(a)gmail.com (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Add secure sections for PSCI text and data ARMv8: Enable SMC instruction ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and device tree ARMv8: LS1043A: Enable LS1043A default PSCI support arch/arm/config.mk | 3 +- arch/arm/cpu/armv8/Kconfig | 41 ++++ arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/cpu-dt.c | 11 +- arch/arm/cpu/armv8/cpu.c | 22 ++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 21 ++ arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 +- arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 ++ arch/arm/cpu/armv8/psci.S | 286 +++++++++++++++++++++++ arch/arm/cpu/armv8/sec_firmware.c | 2 +- arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- arch/arm/cpu/armv8/u-boot.lds | 57 +++++ arch/arm/dts/fsl-ls1043a-qds.dtsi | 12 +- arch/arm/dts/fsl-ls1043a-rdb.dts | 8 +- arch/arm/include/asm/armv8/sec_firmware.h | 2 +- arch/arm/include/asm/macro.h | 8 +- arch/arm/include/asm/psci.h | 15 ++ arch/arm/include/asm/secure.h | 2 +- arch/arm/include/asm/system.h | 11 + arch/arm/lib/bootm-fdt.c | 3 +- arch/arm/lib/bootm.c | 3 + arch/arm/lib/psci-dt.c | 5 +- arch/powerpc/include/asm/config_mpc85xx.h | 5 + board/freescale/b4860qds/ddr.c | 3 + board/freescale/ls1043aqds/ddr.c | 3 + board/freescale/ls1043ardb/Kconfig | 9 + board/freescale/ls1043ardb/ddr.c | 3 + board/freescale/ls1046aqds/ddr.c | 3 + board/freescale/ls1046ardb/ddr.c | 3 + board/freescale/ls2080ardb/ddr.c | 3 + board/freescale/t102xqds/ddr.c | 3 + board/freescale/t102xrdb/ddr.c | 4 + board/freescale/t1040qds/ddr.c | 3 + board/freescale/t104xrdb/ddr.c | 2 + board/freescale/t208xqds/ddr.c | 3 + board/freescale/t208xrdb/ddr.c | 3 + board/freescale/t4qds/ddr.c | 3 + board/freescale/t4rdb/ddr.c | 3 + drivers/net/fsl-mc/dpio/qbman_portal.c | 19 +- drivers/net/fsl-mc/dpio/qbman_portal.h | 5 +- drivers/net/fsl-mc/dpio/qbman_private.h | 19 ++ drivers/net/fsl-mc/dpio/qbman_sys.h | 18 +- include/configs/ls1043ardb.h | 1 - 45 files changed, 624 insertions(+), 36 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S create mode 100644 arch/arm/cpu/armv8/psci.S Thanks. York

2 1

[U-Boot] Pull request v2: u-boot-spi/master
by Jagan Teki 17 Dec '16

17 Dec '16

Hi Tom, Please pull this PR. Changes for v2: - Skip "spi: Zap mpc52xx_spi.c and config" patch due to dependencies. thanks! Jagan. The following changes since commit 53e8ca22538c2cec691fe74098684a359302688c: MAINTAINERS: DFU: Change e-mail address for DFU maintainer (2016-12-12 13:03:15 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to db9225ba2686d6b7e249d00e1803bd07f71d6070: sf: Do not force the DT memory map size to exactly match the device (2016-12-15 16:57:28 +0100) ---------------------------------------------------------------- Fabien Parent (1): mtd: spi: don't return -1 when scan succeed Phil Edworthy (10): spi: cadence_qspi: Fix clearing of pol/pha bits spi: cadence_qspi: Fix baud rate calculation spi: cadence_qspi: Better debug information on the SPI clock rate spi: cadence_qspi: Use #define for bits instead of bit shifts spi: cadence_qspi: Clean up the #define names spi: cadence_qspi: Use spi mode at the point it is needed spi: cadence_qspi: Remove returns from end of void functions spi: cadence_qspi: Fix CS timings spi: cadence_qspi: Move DT prop code to match layout sf: Do not force the DT memory map size to exactly match the device Simon Glass (1): spi: Add error checking for invalid bus widths Vignesh R (1): ARM: dts: am437x-idk: Fix QSPI compatible string arch/arm/dts/am437x-idk-evm.dts | 2 +- drivers/mtd/spi/spi_flash.c | 6 +- drivers/spi/cadence_qspi.c | 6 +- drivers/spi/cadence_qspi.h | 3 +- drivers/spi/cadence_qspi_apb.c | 185 ++++++++++++++++++---------------------- drivers/spi/spi-uclass.c | 4 +- 6 files changed, 93 insertions(+), 113 deletions(-)

2 7

Re: [U-Boot] [PATCH] ARM: imx7s-warp: enable USB gadget ethernet
by Fabio Estevam 17 Dec '16

17 Dec '16

On Fri, Dec 16, 2016 at 7:04 PM, Kevin Hilman <khilman(a)baylibre.com> wrote: > Enable USB gadget ethernet by default to have networking capabilities. > > Tested using DHCP and TFTP to transfer kernel, DT, ramdisk. > > Cc: Fabio Estevam <festevam(a)gmail.com> > Signed-off-by: Kevin Hilman <khilman(a)baylibre.com> Thanks for the patch: Reviewed-by: Fabio Estevam <fabio.estevam(a)nxp.com>

1 0

[U-Boot] [PATCH v2 0/2] fs/fat: more bugfixes, cleanups
by Stefan Brüns 17 Dec '16

17 Dec '16

Fix a possible filesystem corruption if the FS is almost full, and remove some duplicate code. Stefan Brüns (2): fs/fat: Avoid corruption of sectors following the FAT fs/fat: merge readwrite get_fatent_value() with readonly get_fatent() fs/fat/fat.c | 26 +++++++++-- fs/fat/fat_write.c | 134 ++++++----------------------------------------------- 2 files changed, 37 insertions(+), 123 deletions(-) v2: fixed author tag encoding use consistent debut output formatting added rb: Benoît Thébaudeau <benoit.thebaudeau.dev(a)gmail.com> -- 2.11.0

1 0

[U-Boot] [PATCH v2] Revert "sf: Fix quad bit set for micron devices"
by Jagan Teki 16 Dec '16

16 Dec '16

From: Cyrille Pitchen <cyrille.pitchen(a)atmel.com> This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe. Once the 'Quad Enable' bit is cleared in their Enhanced Volatile Configuration Register (EVCR), Micron memories expect ALL commands to use the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer accepted. Within the reverted commit, the write_evcr() function is implemented using the spi_flash_write_common(), which is a shortcut for the [ spi_flash_cmd_write_enable(), spi_flash_cmd_write(), spi_flash_cmd_wait_ready() ] sequence. Since the internal state of the Micron memory has been changed when the spi_flash_cmd_write() function completes, the later call of the spi_flash_cmd_wait_ready() function fails. Indeed the SPI controller driver is not aware of the SPI protocol switch. Further patches will fix the support of Micron QSPI memories. Signed-off-by: Cyrille Pitchen <cyrille.pitchen(a)atmel.com> [Rebase on master, use JEDEC_MFR(info) in place of idcode0] Signed-off-by: Jagan Teki <jagan(a)openedev.com> --- Changes for v2: - Rebase and JEDEC_MFR(info) in place of idcode0 drivers/mtd/spi/sf_internal.h | 3 --- drivers/mtd/spi/spi_flash.c | 62 ++----------------------------------------- 2 files changed, 2 insertions(+), 63 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 2463686..839cdbe 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -49,7 +49,6 @@ enum spi_nor_option_flags { #define CMD_WRITE_DISABLE 0x04 #define CMD_WRITE_ENABLE 0x06 #define CMD_QUAD_PAGE_PROGRAM 0x32 -#define CMD_WRITE_EVCR 0x61 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -63,7 +62,6 @@ enum spi_nor_option_flags { #define CMD_READ_STATUS1 0x35 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 -#define CMD_READ_EVCR 0x65 /* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR @@ -78,7 +76,6 @@ enum spi_nor_option_flags { #define STATUS_QEB_WINSPAN BIT(1) #define STATUS_QEB_MXIC BIT(6) #define STATUS_PEC BIT(7) -#define STATUS_QEB_MICRON BIT(7) #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index b902540..2e378dc 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -112,37 +112,6 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif -#ifdef CONFIG_SPI_FLASH_STMICRO -static int read_evcr(struct spi_flash *flash, u8 *evcr) -{ - int ret; - const u8 cmd = CMD_READ_EVCR; - - ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1); - if (ret < 0) { - debug("SF: error reading EVCR\n"); - return ret; - } - - return 0; -} - -static int write_evcr(struct spi_flash *flash, u8 evcr) -{ - u8 cmd; - int ret; - - cmd = CMD_WRITE_EVCR; - ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1); - if (ret < 0) { - debug("SF: error while writing EVCR register\n"); - return ret; - } - - return 0; -} -#endif - #ifdef CONFIG_SPI_FLASH_BAR static int write_bar(struct spi_flash *flash, u32 offset) { @@ -894,34 +863,6 @@ static int spansion_quad_enable(struct spi_flash *flash) } #endif -#ifdef CONFIG_SPI_FLASH_STMICRO -static int micron_quad_enable(struct spi_flash *flash) -{ - u8 qeb_status; - int ret; - - ret = read_evcr(flash, &qeb_status); - if (ret < 0) - return ret; - - if (!(qeb_status & STATUS_QEB_MICRON)) - return 0; - - ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON); - if (ret < 0) - return ret; - - /* read EVCR and check it */ - ret = read_evcr(flash, &qeb_status); - if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) { - printf("SF: Micron EVCR Quad bit not clear\n"); - return -EINVAL; - } - - return ret; -} -#endif - static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash) { int tmp; @@ -962,7 +903,8 @@ static int set_quad_mode(struct spi_flash *flash, #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - return micron_quad_enable(flash); + debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info)); + return 0; #endif default: printf("SF: Need set QEB func for %02x flash\n", -- 1.9.1

1 1

[U-Boot] [PATCH] ARM: imx7s-warp: enable USB gadget ethernet
by Kevin Hilman 16 Dec '16

16 Dec '16

Enable USB gadget ethernet by default to have networking capabilities. Tested using DHCP and TFTP to transfer kernel, DT, ramdisk. Cc: Fabio Estevam <festevam(a)gmail.com> Signed-off-by: Kevin Hilman <khilman(a)baylibre.com> --- Applies to v2016.11 board/warp7/warp7.c | 14 ++++++++++++++ configs/warp7_defconfig | 5 +++++ include/configs/warp7.h | 7 +++++++ 3 files changed, 26 insertions(+) diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index da9afb4ccd86..df8e9da6f919 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -19,6 +19,7 @@ #include <mmc.h> #include <asm/arch/crm_regs.h> #include <usb.h> +#include <netdev.h> #include <power/pmic.h> #include <power/pfuze3000_pmic.h> #include "../freescale/common/pfuze.h" @@ -138,6 +139,19 @@ int power_init_board(void) } #endif +int board_eth_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_USB_ETHER + ret = usb_eth_initialize(bis); + if (ret < 0) + printf("Error %d registering USB ether.\n", ret); +#endif + + return ret; +} + int board_init(void) { /* address of boot parameters */ diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 0f0ec99e50ca..81acd8ff15c8 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -35,3 +35,8 @@ CONFIG_G_DNL_MANUFACTURER="FSL" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y + +CONFIG_CMD_NET=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CMD_DHCP=y + diff --git a/include/configs/warp7.h b/include/configs/warp7.h index d3b0c5e0d62c..f4a92319ebad 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -38,6 +38,7 @@ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ + "ethact=usb_ether\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=imx7s-warp.dtb\0" \ @@ -145,4 +146,10 @@ #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" +#define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01" + #endif -- 2.9.3

1 0

[U-Boot] [PATCH v5 0/6] Add ARMv8 PSCI framework
by Hongbo Zhang 16 Dec '16

16 Dec '16

v4-v5 changes: - rebased to latest u-boot version to ease conflict. - added mutually exclusive from FSL_PPA. v3-v4 changes: - Re-added the 1/6 from v2, and move the newly re-named macro into Kconfig - Add "Reviewed-by: Tom Rini <trini(a)konsulko.com>" for patch 4/6 ~ 6/6. v2-v3 changes: - Drop the previous 1/6, since the previous CONFIG_ARMV8_PSCI in common parts of codes also work for generic PSCI framework, so there are 5 patches in this iteration. - Add "Reviewed-by: Tom Rini <trini(a)konsulko.com>" for patches 1/5 and 2/5, which were 2/6 and 3/6. - Move config values for ls1043 from armv8/Kconfig to s1043ardb_defconfig. v1-v2 changes: - The new config options are introduced in Kconfig when used for first time - Introduce new config options in armv8/Kconfig instead of LS1043 platform - Move previous patch 5/6 to current 2/6 place v1 notes: This patch set introduces ARMv8 PSCI framework, all the PSCI functions are implemented a default dummy one, it is up to each platform to implement their own specific ones. The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. The last 6/6 adds a most simple implementation on NXP LS1043 platform, to verify this framework. This patch set mainly introduces ARMv8 PSCI framework, for easier review and merge, further PSCI implementation on LS1043 is coming later. Hongbo Zhang (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Add secure sections for PSCI text and data ARMv8: Enable SMC instruction ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and device tree ARMv8: LS1043A: Enable LS1043A default PSCI support arch/arm/config.mk | 3 +- arch/arm/cpu/armv8/Kconfig | 41 ++++ arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/cpu-dt.c | 11 +- arch/arm/cpu/armv8/cpu.c | 22 ++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 21 ++ arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 +- arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 ++ arch/arm/cpu/armv8/psci.S | 286 +++++++++++++++++++++++ arch/arm/cpu/armv8/sec_firmware.c | 2 +- arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- arch/arm/cpu/armv8/u-boot.lds | 57 +++++ arch/arm/include/asm/armv8/sec_firmware.h | 2 +- arch/arm/include/asm/macro.h | 8 +- arch/arm/include/asm/psci.h | 15 ++ arch/arm/include/asm/secure.h | 2 +- arch/arm/include/asm/system.h | 11 + arch/arm/lib/bootm-fdt.c | 3 +- arch/arm/lib/bootm.c | 3 + arch/arm/lib/psci-dt.c | 5 +- board/freescale/ls1043ardb/Kconfig | 9 + include/configs/ls1043ardb.h | 1 - 24 files changed, 519 insertions(+), 13 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S create mode 100644 arch/arm/cpu/armv8/psci.S -- 2.1.4

3 9

[U-Boot] [PATCH] driver: fsl-mc: qbman: Add QBMAN 4.1 support
by Priyanka Jain 16 Dec '16

16 Dec '16

LS2080A SoC family has QBMAN ver 4.0 whereas newer SoCs like LS2088A, LS1088A has QBMAN ver 4.1 QBMAN ver 4.0 and ver 4.1 supports dqrr size as 4 and 8 respectively. Add support of to check QBMAN version based on SoC SVR update dqrr_size accordingly update code to support larger dqrr_size Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- drivers/net/fsl-mc/dpio/qbman_portal.c | 19 ++++++++++++++++--- drivers/net/fsl-mc/dpio/qbman_portal.h | 5 +++-- drivers/net/fsl-mc/dpio/qbman_private.h | 19 +++++++++++++++++++ drivers/net/fsl-mc/dpio/qbman_sys.h | 18 ++++++++++-------- 4 files changed, 48 insertions(+), 13 deletions(-) diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.c b/drivers/net/fsl-mc/dpio/qbman_portal.c index 4b64c8a..86dc13d 100644 --- a/drivers/net/fsl-mc/dpio/qbman_portal.c +++ b/drivers/net/fsl-mc/dpio/qbman_portal.c @@ -25,7 +25,7 @@ #define QBMAN_CENA_SWP_VDQCR 0x780 /* Reverse mapping of QBMAN_CENA_SWP_DQRR() */ -#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0xff) >> 6) +#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0x1ff) >> 6) /*******************************/ /* Pre-defined attribute codes */ @@ -65,6 +65,7 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) { int ret; struct qbman_swp *p = malloc(sizeof(struct qbman_swp)); + u32 major = 0, minor = 0; if (!p) return NULL; @@ -80,8 +81,20 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) atomic_set(&p->vdq.busy, 1); p->vdq.valid_bit = QB_VALID_BIT; p->dqrr.next_idx = 0; + + qbman_version(&major, &minor); + if (!major) { + printf("invalid qbman version\n"); + return NULL; + } + + if (major >= 4 && minor >= 1) + p->dqrr.dqrr_size = QBMAN_VER_4_1_DQRR_SIZE; + else + p->dqrr.dqrr_size = QBMAN_VER_4_0_DQRR_SIZE; + p->dqrr.valid_bit = QB_VALID_BIT; - ret = qbman_swp_sys_init(&p->sys, d); + ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size); if (ret) { free(p); printf("qbman_swp_sys_init() failed %d\n", ret); @@ -380,7 +393,7 @@ const struct ldpaa_dq *qbman_swp_dqrr_next(struct qbman_swp *s) /* There's something there. Move "next_idx" attention to the next ring * entry (and prefetch it) before returning what we found. */ s->dqrr.next_idx++; - s->dqrr.next_idx &= QBMAN_DQRR_SIZE - 1; /* Wrap around at 4 */ + s->dqrr.next_idx &= s->dqrr.dqrr_size - 1;/* Wrap around at dqrr_size */ /* TODO: it's possible to do all this without conditionals, optimise it * later. */ if (!s->dqrr.next_idx) diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.h b/drivers/net/fsl-mc/dpio/qbman_portal.h index 86e2c3a..97a47aa 100644 --- a/drivers/net/fsl-mc/dpio/qbman_portal.h +++ b/drivers/net/fsl-mc/dpio/qbman_portal.h @@ -14,8 +14,8 @@ /* Management command result codes */ #define QBMAN_MC_RSLT_OK 0xf0 -/* TBD: as of QBMan 4.1, DQRR will be 8 rather than 4! */ -#define QBMAN_DQRR_SIZE 4 +#define QBMAN_VER_4_0_DQRR_SIZE 4 +#define QBMAN_VER_4_1_DQRR_SIZE 8 /* --------------------- */ @@ -71,6 +71,7 @@ struct qbman_swp { struct { uint32_t next_idx; uint32_t valid_bit; + uint8_t dqrr_size; } dqrr; }; diff --git a/drivers/net/fsl-mc/dpio/qbman_private.h b/drivers/net/fsl-mc/dpio/qbman_private.h index f1f16b8..73bbae3 100644 --- a/drivers/net/fsl-mc/dpio/qbman_private.h +++ b/drivers/net/fsl-mc/dpio/qbman_private.h @@ -11,6 +11,7 @@ #include <linux/types.h> #include <asm/atomic.h> #include <malloc.h> +#include <asm/arch/soc.h> #include <fsl-mc/fsl_qbman_base.h> #define QBMAN_CHECKING @@ -166,4 +167,22 @@ static inline void dcbz(void *ptr) #define lwsync() +void qbman_version(u32 *major, u32 *minor) +{ + u32 svr_dev_id; + + /* + * LS2080A SoC and its personalities has qbman cotroller version 4.0 + * New SoCs like LS2088A, LS1088A has qbman conroller version 4.1 + */ + svr_dev_id = get_svr() >> 16; + if (svr_dev_id == SVR_DEV_LS2080A) { + *major = 4; + *minor = 0; + } else { + *major = 4; + *minor = 1; + } +} + #include "qbman_sys.h" diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h b/drivers/net/fsl-mc/dpio/qbman_sys.h index 7a537fb..72d74c5 100644 --- a/drivers/net/fsl-mc/dpio/qbman_sys.h +++ b/drivers/net/fsl-mc/dpio/qbman_sys.h @@ -239,16 +239,18 @@ static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn, { uint32_t reg; - reg = e32_uint8_t(20, 3, max_fill) | e32_uint8_t(16, 3, est) | - e32_uint8_t(12, 2, rpm) | e32_uint8_t(10, 2, dcm) | - e32_uint8_t(8, 2, epm) | e32_int(5, 1, sd) | - e32_int(4, 1, sp) | e32_int(3, 1, se) | e32_int(2, 1, dp) | - e32_int(1, 1, de) | e32_int(0, 1, ep) | e32_uint8_t(14, 1, wn); + reg = e32_uint8_t(20, (uint32_t)(3 + (max_fill >> 3)), max_fill) | + e32_uint8_t(16, 3, est) | e32_uint8_t(12, 2, rpm) | + e32_uint8_t(10, 2, dcm) | e32_uint8_t(8, 2, epm) | + e32_int(5, 1, sd) | e32_int(4, 1, sp) | e32_int(3, 1, se) | + e32_int(2, 1, dp) | e32_int(1, 1, de) | e32_int(0, 1, ep) | + e32_uint8_t(14, 1, wn); return reg; } static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, - const struct qbman_swp_desc *d) + const struct qbman_swp_desc *d, + uint8_t dqrr_size) { uint32_t reg; @@ -270,9 +272,9 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, BUG_ON(reg); #endif #ifdef QBMAN_CINH_ONLY - reg = qbman_set_swp_cfg(4, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0); + reg = qbman_set_swp_cfg(dqrr_size, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0); #else - reg = qbman_set_swp_cfg(4, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0); + reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0); #endif qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg); reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); -- 1.7.4.1

2 1

[U-Boot] [PATCH 1/2] armv8: ls1043ardb: dts: Fix the unit-address of some I2C device nodes
by Zhiqiang Hou 16 Dec '16

16 Dec '16

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> The unit-address should be the same as the I2C address of the device. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- arch/arm/dts/fsl-ls1043a-rdb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts index 16c5c89..5744075 100644 --- a/arch/arm/dts/fsl-ls1043a-rdb.dts +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -47,12 +47,12 @@ compatible = "adi,adt7461a"; reg = <0x4c>; }; - eeprom@56 { + eeprom@52 { compatible = "at24,24c512"; reg = <0x52>; }; - eeprom@57 { + eeprom@53 { compatible = "at24,24c512"; reg = <0x53>; }; -- 2.1.0.27.g96db324

2 3