December 2016 - U-Boot

[U-Boot] [PATCH] regulator: fixed: Add support to handle enable-active-high DT property
by Vignesh R 27 Dec '16

27 Dec '16

Add support to handle enable-active-high DT property. This property is used to drive the gpio controlling fixed regulator as active high when claiming gpio line. Signed-off-by: Vignesh R <vigneshr(a)ti.com> --- doc/device-tree-bindings/regulator/fixed.txt | 4 ++++ drivers/power/regulator/fixed.c | 7 ++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/doc/device-tree-bindings/regulator/fixed.txt b/doc/device-tree-bindings/regulator/fixed.txt index 8a0d002688d8..5fd9033fea2d 100644 --- a/doc/device-tree-bindings/regulator/fixed.txt +++ b/doc/device-tree-bindings/regulator/fixed.txt @@ -12,6 +12,9 @@ Optional properties: - gpio: GPIO to use for enable control - startup-delay-us: startup time in microseconds - regulator constraints (binding info: regulator.txt) +- enable-active-high: Polarity of GPIO is Active high. If this property + is missing, the default assumed is Active low. + Other kernel-style properties, are currently not used. @@ -36,4 +39,5 @@ fixed_regulator@0 { regulator-max-microamp = <15000>; regulator-always-on; regulator-boot-on; + enable-active-high; }; diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index 62dc47f76985..3d2d9081c1b1 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -27,6 +27,8 @@ static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) struct dm_regulator_uclass_platdata *uc_pdata; struct fixed_regulator_platdata *dev_pdata; struct gpio_desc *gpio; + const void *blob = gd->fdt_blob; + int node = dev->of_offset, flags = GPIOD_IS_OUT; int ret; dev_pdata = dev_get_platdata(dev); @@ -37,9 +39,12 @@ static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) /* Set type to fixed */ uc_pdata->type = REGULATOR_TYPE_FIXED; + if (fdtdec_get_bool(blob, node, "enable-active-high")) + flags |= GPIOD_IS_OUT_ACTIVE; + /* Get fixed regulator optional enable GPIO desc */ gpio = &dev_pdata->gpio; - ret = gpio_request_by_name(dev, "gpio", 0, gpio, GPIOD_IS_OUT); + ret = gpio_request_by_name(dev, "gpio", 0, gpio, flags); if (ret) { debug("Fixed regulator optional enable GPIO - not found! Error: %d\n", ret); -- 2.11.0

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[U-Boot] Pull request: u-boot-sunxi/master
by Jagan Teki 27 Dec '16

27 Dec '16

Hi Tom, Please pull this fix. thanks! Jagan. The following changes since commit 4cf5c5f1e60e6541630ae829b5fa2db704c268f0: Prepare v2017.01-rc2 (2016-12-19 16:08:57 -0500) are available in the git repository at: git://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to c23749dbf2601986a23e2654d153e0d66a9804ba: sunxi: fix SID read on H3 (2016-12-23 13:07:04 +0100) ---------------------------------------------------------------- Icenowy Zheng (1): sunxi: fix SID read on H3 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 1 + arch/arm/mach-sunxi/cpu_info.c | 44 +++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+)

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[U-Boot] [PATCH v3 0/4] cl-som-am57x: initial support
by Uri Mashiach 27 Dec '16

27 Dec '16

This patch series adds support for CompuLab CL-SOM-AM57X board and the SBC-AM57X evaluation kit. CL-SOM-AM57x is a miniature System-on-Module (SoM) based on TI Sitara AM57x ARM Cortex-A15 System-on-Chip family. SBC-AM57x is a single board computer, implemented with the CL-SOM-AM57x computer-on-module and the SB-SOM-AM57x carrier board. The CL-SOM-AM57x providing most of the functions and the SB-SOM-AM57x providing additional peripheral functions and connectors. The SBC-AM57x has the following features: CPU: Texas Instruments Sitara AM5728 dual-core ARM Cortex-A15, 1.5GHz or Texas Instruments Sitara AM5718 single-core ARM Cortex-A15, 1.5GHz RAM: DDR3, 512MB – 4GB Storage: NAND flash, 512MB - 1GB or eMMC flash, 4GB - 32GB SPI-flash 2MB Ethernet: Up to 2x 10/100/1000Mbps Ethernet ports (MAC+PHY) WiFi/BT: 802.11b/g/n WiFi interface (TI WiLink 8 WL1801 chipset) or Dual-band 2x2 802.11a/b/g/n WiFi interface (TI WiLink 8 WL1837 chipset) Analog Audio: Audio codec with stereo output, stereo input and microphone support More details can be found here: https://www.compulab.co.il/products/computer-on-modules/cl-som-am57x-ti-am5… https://www.compulab.co.il/products/sbcs/sbc-am57x-ti-am5728-am5718-single-… Dmitry Lifshitz (3): arm: am57xx: cl-som-am57x: add initial board support arm: am57xx: cl-som-am57x: fetch board rev from EEPROM arm: am57xx: cl-som-am57x: add ETH support Uri Mashiach (1): arm: am57xx: cl-som-am57x: update default env arch/arm/mach-omap2/omap5/Kconfig | 4 + board/compulab/cl-som-am57x/Kconfig | 12 ++ board/compulab/cl-som-am57x/MAINTAINERS | 6 + board/compulab/cl-som-am57x/Makefile | 17 +++ board/compulab/cl-som-am57x/cl-som-am57x.c | 76 ++++++++++ board/compulab/cl-som-am57x/eth.c | 199 ++++++++++++++++++++++++++ board/compulab/cl-som-am57x/mux.c | 123 ++++++++++++++++ board/compulab/cl-som-am57x/spl.c | 222 +++++++++++++++++++++++++++++ configs/cl-som-am57x_defconfig | 41 ++++++ include/configs/cl-som-am57x.h | 197 +++++++++++++++++++++++++ 10 files changed, 897 insertions(+) create mode 100644 board/compulab/cl-som-am57x/Kconfig create mode 100644 board/compulab/cl-som-am57x/MAINTAINERS create mode 100644 board/compulab/cl-som-am57x/Makefile create mode 100644 board/compulab/cl-som-am57x/cl-som-am57x.c create mode 100644 board/compulab/cl-som-am57x/eth.c create mode 100644 board/compulab/cl-som-am57x/mux.c create mode 100644 board/compulab/cl-som-am57x/spl.c create mode 100644 configs/cl-som-am57x_defconfig create mode 100644 include/configs/cl-som-am57x.h -- 2.7.4

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[U-Boot] [PATCH v2] mmc: rockchip_sdhci: add clock init for mmc
by Kever Yang 27 Dec '16

27 Dec '16

Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver api. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v2: - using the return value drivers/mmc/rockchip_sdhci.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index c56e1a3..c37c697 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -12,6 +12,7 @@ #include <libfdt.h> #include <malloc.h> #include <sdhci.h> +#include <clk.h> /* 400KHz is max freq for card ID etc. Use that as min */ #define EMMC_MIN_FREQ 400000 @@ -33,6 +34,16 @@ static int arasan_sdhci_probe(struct udevice *dev) struct rockchip_sdhc *prv = dev_get_priv(dev); struct sdhci_host *host = &prv->host; int ret; + struct clk clk; + + ret = clk_get_by_index(dev, 0, &clk); + if (!ret) { + ret = clk_set_rate(&clk, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ); + if (IS_ERR_VALUE(ret)) + printf("%s clk set rate fail!\n", __func__); + } else { + printf("%s fail to get clk\n", __func__) + } host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; -- 1.9.1

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[U-Boot] Hoping to dual-boot an M8S Pro / Amlogic S812 machine
by Alexandru Lovin 27 Dec '16

27 Dec '16

Hello everyone, happy holidays, I want to dual-boot Gentoo and the original Android on one of these <https://www.amazon.com/NinkBox-Android-Amlogic-Bluetooth-streaming/dp/B01EO…> boxes. To install Gentoo, I found an equivalent tutorial for a box named TrimSlice, here <https://wiki.gentoo.org/wiki/TrimSlice>. Nowhere in that tutorial do they actually make the target box dual-bootable, so that is my question: How do I make that M8S Pro dual-boot with U-boot? I don't want to nuke the original Android off it.

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[U-Boot] Targets for BeagleBones
by Kristian Amlie 27 Dec '16

27 Dec '16

I assume that the most appropriate configuration target for BeagleBone Black is am335x_boneblack_config. But what about BeagleBone White? Up until now we've been using am335x_evm_config, but are considering switching to the former. This discussion started after the commit 80b24fcd3 in U-Boot broke some MMC compatibility on the BeagleBone Black (specifically, accessing the internal MMC when holding the button to boot from external MMC). This was due to the addition of the CONFIG_DM_MMC option. Since this still works with the am335_boneblack_config target, we're considering the switch for both boards. -- Kristian

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[U-Boot] [PATCH 1/2] armv8: ls1046a: added usb feature support
by yuantian.tang＠nxp.com 27 Dec '16

27 Dec '16

From: Tang Yuantian <Yuantian.Tang(a)nxp.com> The LS1046A processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: Tang Yuantian <yuantian.tang(a)nxp.com> --- arch/arm/dts/fsl-ls1046a.dtsi | 22 ++++++++++++++++++++++ include/configs/ls1046ardb.h | 8 ++++++++ include/linux/usb/xhci-fsl.h | 2 +- 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 359a9d1..ee3180e 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -216,5 +216,27 @@ big-endian; status = "disabled"; }; + + usb0: usb@2f00000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 60 4>; + dr_mode = "host"; + }; + + usb1: usb@3000000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = <0 61 4>; + dr_mode = "host"; + }; + + usb2: usb@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 63 4>; + dr_mode = "host"; + }; + }; }; diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 2fe8fc1..d363d1f 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -211,6 +211,14 @@ #define CONFIG_SPI_FLASH_BAR #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 15cac40..1fa3161 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -62,7 +62,7 @@ struct fsl_xhci { #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_LS1043A) +#elif defined(CONFIG_LS1043A) || defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 2/7] ext4: determine group descriptor size for 64bit feature
by Stefan Brüns 27 Dec '16

27 Dec '16

If EXT4_FEATURE_INCOMPAT_64BIT is set, the descriptor can be read from the superblocks, otherwise it defaults to 32. Signed-off-by: Stefan Brüns <stefan.bruens(a)rwth-aachen.de> --- fs/ext4/ext4_common.c | 18 ++++++++++++++---- include/ext4fs.h | 2 ++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index a78b0b8..416a9db 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -2233,13 +2233,23 @@ int ext4fs_mount(unsigned part_length) goto fail; } - if (le32_to_cpu(data->sblock.revision_level) == 0) + if (le32_to_cpu(data->sblock.revision_level) == 0) { fs->inodesz = 128; - else + } else { + debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: %08x\n", + __le32_to_cpu(data->sblock.feature_compatibility), + __le32_to_cpu(data->sblock.feature_incompat), + __le32_to_cpu(data->sblock.feature_ro_compat)); + fs->inodesz = le16_to_cpu(data->sblock.inode_size); + fs->gdsize = le32_to_cpu(data->sblock.feature_incompat) & + EXT4_FEATURE_INCOMPAT_64BIT ? + le16_to_cpu(data->sblock.descriptor_size) : 32; + } - debug("EXT2 rev %d, inode_size %d\n", - le32_to_cpu(data->sblock.revision_level), fs->inodesz); + debug("EXT2 rev %d, inode_size %d, descriptor size %d\n", + le32_to_cpu(data->sblock.revision_level), + fs->inodesz, fs->gdsize); data->diropen.data = data; data->diropen.ino = 2; diff --git a/include/ext4fs.h b/include/ext4fs.h index 6e31c73..7e1ee6c 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -87,6 +87,8 @@ struct ext_filesystem { uint32_t inodesz; /* Sectors per Block */ uint32_t sect_perblk; + /* Group Descriptor size */ + uint16_t gdsize; /* Group Descriptor Block Number */ uint32_t gdtable_blkno; /* Total block groups of partition */ -- 2.10.0

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[U-Boot] Linux 4.9 on cortex-M4 STM32F429-disc1
by Steven VALSESIA 26 Dec '16

26 Dec '16

Hi, I'm stuck since days with this problem, Linux don't boot. My board flash start 0x0800 0000 2MB. My board external RAM start at 0xD000 0000 8MB. I have a Linux 4.9, near the default stm32f2_defconfig. U-BOOT at 0x0800 0000. DTB at 0x0804 0000. XIP kernel at 0x0806 0000. I just have "Starting kernel..." on last message. I tried to add a LED toggle on the kernel start (arch/arm/boot/compressed/head.S) and it's not called. Same asm code run fine with u-boot on init. more details here: http://stackoverflow.com/questions/41321971/running-linux-4-9-on-cortex-m4-… If you have any clues, any idea, don't hesitate, I'm desperate.

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[U-Boot] [RFC PATCH] pcf2127: add watchdog support
by Sean Nyekjaer 26 Dec '16

26 Dec '16

Signed-off-by: Sean Nyekjaer <sean.nyekjaer(a)prevas.dk> --- - I have just noticed that the RTC driver for this device have been merged, should the watchdog part be included in the rtc driver or standalone? - The hw_watchdog_reset is called far too often the device here is on i2c, with what i have done the reset is written every 1s - What should be the default delay? I have chosen 20? drivers/watchdog/Kconfig | 11 +++++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/pcf2127_wdt.c | 69 ++++++++++++++++++++++++++++++++++++++++++ include/pcf2127_wdt.h | 3 ++ 4 files changed, 84 insertions(+) create mode 100644 drivers/watchdog/pcf2127_wdt.c create mode 100644 include/pcf2127_wdt.h diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index e69de29bb2..957f2f3a87 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -0,0 +1,11 @@ +# +# Watchdog drivers configuration +# + +menu "Watchdog" + +config PCF2127_WATCHDOG + depends on DM_I2C + bool "Enable pcf2127 i2c watchdog" + +endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index a007ae8234..3c573de016 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o +obj-$(CONFIG_PCF2127_WATCHDOG) += pcf2127_wdt.o diff --git a/drivers/watchdog/pcf2127_wdt.c b/drivers/watchdog/pcf2127_wdt.c new file mode 100644 index 0000000000..f9276e3ea5 --- /dev/null +++ b/drivers/watchdog/pcf2127_wdt.c @@ -0,0 +1,69 @@ +#include <common.h> +#include <i2c.h> +#include <watchdog.h> +#include <pcf2127_wdt.h> + +#define PCF2127_REG_WDT_CTRL 0x10 +#define PCF2127_REG_WDT_TIM 0x11 + +#define PCF2127_WDT_MODE(wdt_mode) (wdt_mode << 6) +#define PCF2127_WDT_DISABLED 0b00 /* watchdog timer disabled */ +#define PCF2127_WDT_ENABLED_RST 0b11 /* watchdog timer enabled, + rst activated when timeout */ + +#define PCF2127_WDT_TIMER_SRC(src) (src) +#define PCF2127_WDT_4096HZ 0b00 +#define PCF2127_WDT_64HZ 0b01 +#define PCF2127_WDT_1HZ 0b10 +#define PCF2127_WDT_16mHZ 0b11 + +#define DCNT 4194304 + +static uchar timeout = 20; +static bool wdt_active = false; +static uint32_t cnt = DCNT-1; /* minus one to ensure the reset is called in SPL */ + +int pcf2127_reg_read(const uchar reg, uchar *val) +{ + return i2c_read(PCF2127_I2C_ADDR, reg, 1, val, 1); +} + +int pcf2127_reg_write(const uchar reg, uchar val) +{ + return i2c_write(PCF2127_I2C_ADDR, reg, 1, &val, 1); +} + +static int pcf2127_wdt_setup(uchar mode, uchar tim_src) +{ + pcf2127_reg_write(PCF2127_REG_WDT_CTRL, + PCF2127_WDT_MODE(mode) | PCF2127_WDT_TIMER_SRC(tim_src)); + return 0; +} + +static int pcf2127_wdt_settimeout(uchar t_out) +{ + timeout = (uchar)t_out; + pcf2127_reg_write(PCF2127_REG_WDT_TIM, timeout); + return 0; +} + +void pcf2127_wdt_enable(void) +{ + wdt_active = true; +} + +void hw_watchdog_reset(void) +{ + if(wdt_active == true) { + if (cnt++ % DCNT == 0) + pcf2127_wdt_settimeout(20); + } +} + +void hw_watchdog_init(void) +{ + if(wdt_active == true) { + pcf2127_wdt_setup(PCF2127_WDT_ENABLED_RST, PCF2127_WDT_1HZ); + pcf2127_wdt_settimeout(20); + } +} diff --git a/include/pcf2127_wdt.h b/include/pcf2127_wdt.h new file mode 100644 index 0000000000..3f293b2348 --- /dev/null +++ b/include/pcf2127_wdt.h @@ -0,0 +1,3 @@ +#define PCF2127_I2C_ADDR 0x51 + +void pcf2127_wdt_enable(void); -- 2.11.0

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