December 2016 - U-Boot

[U-Boot] [PATCH] fs/ext4: Initialize group descriptor size for revision level 0 filesystems
by Stefan Brüns 29 Dec '16

29 Dec '16

genext2fs creates revision level 0 filesystems, which are not readable by u-boot due to the initialized group descriptor size field. f798b1dda1c5de818b806189e523d1b75db7e72d Reported-by: Kever Yang <kever.yang(a)rock-chips.com> Reported-by: FrostyBytes(a)protonmail.com Signed-off-by: Stefan Brüns <stefan.bruens(a)rwth-aachen.de> --- fs/ext4/ext4_common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index bfebe7e379..621c61e5c7 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -2334,6 +2334,7 @@ int ext4fs_mount(unsigned part_length) if (le32_to_cpu(data->sblock.revision_level) == 0) { fs->inodesz = 128; + fs->gdsize = 32; } else { debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: %08x\n", __le32_to_cpu(data->sblock.feature_compatibility), -- 2.11.0

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[U-Boot] [PATCH] disk: Fixed capacity message
by Jean-Jacques Hiblot 29 Dec '16

29 Dec '16

With capacities getting bigger, we can see see messages with negative numbers like "Capacity: 1907729.0 MB = 1863.0 GB (-387938128 x 512)". Here the printed LBA is -387938128 when it should have been 3907029168. To fix this, use the right format when displaying the unsigned integers. Signed-off-by: Jean-Jacques Hiblot <jjhiblot(a)ti.com> Reported-by: Yan Liu <yan-liu(a)ti.com> --- disk/part.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/disk/part.c b/disk/part.c index 543cab8..d93a643 100644 --- a/disk/part.c +++ b/disk/part.c @@ -241,13 +241,13 @@ void dev_print (struct blk_desc *dev_desc) printf (" Supports 48-bit addressing\n"); #endif #if defined(CONFIG_SYS_64BIT_LBA) - printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%Ld x %ld)\n", + printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%llu x %lu)\n", mb_quot, mb_rem, gb_quot, gb_rem, lba, dev_desc->blksz); #else - printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n", + printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%lu x %lu)\n", mb_quot, mb_rem, gb_quot, gb_rem, (ulong)lba, -- 1.9.1

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[U-Boot] [PATCH] Update Maintainer and Auther's email address
by Ajay Bhargav 29 Dec '16

29 Dec '16

I am not longer using my old email address "ajay.bhargav(a)einfochips.com". For U-Boot development email address is now updated to contact(a)8051projects.net Signed-off-by: Ajay Bhargav <contact(a)8051projects.net> --- arch/arm/include/asm/arch-armada100/gpio.h | 2 +- arch/arm/include/asm/arch-armada100/spi.h | 2 +- arch/arm/include/asm/arch-armada100/utmi-armada100.h | 2 +- board/Marvell/gplugd/MAINTAINERS | 2 +- board/Marvell/gplugd/Makefile | 2 +- board/Marvell/gplugd/gplugd.c | 2 +- drivers/gpio/mvgpio.c | 2 +- drivers/gpio/mvgpio.h | 2 +- drivers/net/armada100_fec.c | 2 +- drivers/net/armada100_fec.h | 2 +- drivers/spi/armada100_spi.c | 2 +- drivers/usb/host/ehci-armada100.c | 2 +- drivers/usb/host/utmi-armada100.c | 2 +- include/configs/gplugd.h | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h index 4927abea9c..54e6ccf0c2 100644 --- a/arch/arm/include/asm/arch-armada100/gpio.h +++ b/arch/arm/include/asm/arch-armada100/gpio.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2011 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * (C) Copyright 2010 * Marvell Semiconductor <www.marvell.com> diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h index 9efa1bf1e7..631acf3656 100644 --- a/arch/arm/include/asm/arch-armada100/spi.h +++ b/arch/arm/include/asm/arch-armada100/spi.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2011 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * (C) Copyright 2010 * Marvell Semiconductor <www.marvell.com> diff --git a/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/arch/arm/include/asm/arch-armada100/utmi-armada100.h index 953dd44138..fca18276d5 100644 --- a/arch/arm/include/asm/arch-armada100/utmi-armada100.h +++ b/arch/arm/include/asm/arch-armada100/utmi-armada100.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2012 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> diff --git a/board/Marvell/gplugd/MAINTAINERS b/board/Marvell/gplugd/MAINTAINERS index 320bc09de5..197c6a01dd 100644 --- a/board/Marvell/gplugd/MAINTAINERS +++ b/board/Marvell/gplugd/MAINTAINERS @@ -1,5 +1,5 @@ GPLUGD BOARD -M: Ajay Bhargav <ajay.bhargav(a)einfochips.com> +M: Ajay Bhargav <contact(a)8051projects.net> S: Maintained F: board/Marvell/gplugd/ F: include/configs/gplugd.h diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile index b38457845d..8929da5be2 100644 --- a/board/Marvell/gplugd/Makefile +++ b/board/Marvell/gplugd/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2011 # eInfochips Ltd. <www.einfochips.com> -# Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> +# Written-by: Ajay Bhargav <contact(a)8051projects.net> # # Based on Aspenite: # (C) Copyright 2010 diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index 0e8ebcc70d..c8c4ad2a98 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2011 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * Based on Aspenite: * (C) Copyright 2010 diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c index 8bfbc3a585..407385bdf0 100644 --- a/drivers/gpio/mvgpio.c +++ b/drivers/gpio/mvgpio.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2011 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * (C) Copyright 2010 * Marvell Semiconductor <www.marvell.com> diff --git a/drivers/gpio/mvgpio.h b/drivers/gpio/mvgpio.h index 1de739568a..1eb7acd451 100644 --- a/drivers/gpio/mvgpio.h +++ b/drivers/gpio/mvgpio.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2011 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * (C) Copyright 2010 * Marvell Semiconductor <www.marvell.com> diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c index ba2cb1ad6d..caca8fde9f 100644 --- a/drivers/net/armada100_fec.c +++ b/drivers/net/armada100_fec.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2011 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * (C) Copyright 2010 * Marvell Semiconductor <www.marvell.com> diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h index 5a0a3d982d..826048ea1c 100644 --- a/drivers/net/armada100_fec.h +++ b/drivers/net/armada100_fec.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2011 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * (C) Copyright 2010 * Marvell Semiconductor <www.marvell.com> diff --git a/drivers/spi/armada100_spi.c b/drivers/spi/armada100_spi.c index 53aaf95340..acd65b1c64 100644 --- a/drivers/spi/armada100_spi.c +++ b/drivers/spi/armada100_spi.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2011 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> diff --git a/drivers/usb/host/ehci-armada100.c b/drivers/usb/host/ehci-armada100.c index 012eb3a1a4..237d287747 100644 --- a/drivers/usb/host/ehci-armada100.c +++ b/drivers/usb/host/ehci-armada100.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2012 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * This driver is based on Kirkwood echi driver * (C) Copyright 2009 diff --git a/drivers/usb/host/utmi-armada100.c b/drivers/usb/host/utmi-armada100.c index 1e878280f2..17fc132e9a 100644 --- a/drivers/usb/host/utmi-armada100.c +++ b/drivers/usb/host/utmi-armada100.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2012 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index c1b43fd0fe..2f962552cb 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2011 * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * Written-by: Ajay Bhargav <contact(a)8051projects.net> * * Based on Aspenite: * (C) Copyright 2010 -- 2.11.0

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[U-Boot] [PATCH] tools: mkimage: Call fclose in error path
by Michal Simek 29 Dec '16

29 Dec '16

This patch is fixing missing fclose() calls in error patch introduced by: "tools: mkimage: Use fstat instead of stat to avoid malicious hacks" (sha1: ebe0f53f48e8f9ecc823e533a85b05c13638c350) Reported-by: Coverity (CID: 155064, 155065) Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- tools/zynqimage.c | 8 ++++++-- tools/zynqmpimage.c | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/tools/zynqimage.c b/tools/zynqimage.c index b47132b02a60..021d2d3fc91f 100644 --- a/tools/zynqimage.c +++ b/tools/zynqimage.c @@ -239,11 +239,15 @@ static void zynqimage_parse_initparams(struct zynq_header *zynqhdr, } err = fstat(fileno(fp), &path_stat); - if (err) + if (err) { + fclose(fp); return; + } - if (!S_ISREG(path_stat.st_mode)) + if (!S_ISREG(path_stat.st_mode)) { + fclose(fp); return; + } do { r = fscanf(fp, "%x %x", &reginit.address, &reginit.data); diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c index 60d8ed23b4a1..0c9a3daddd6a 100644 --- a/tools/zynqmpimage.c +++ b/tools/zynqmpimage.c @@ -251,11 +251,15 @@ static void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr, } err = fstat(fileno(fp), &path_stat); - if (err) + if (err) { + fclose(fp); return; + } - if (!S_ISREG(path_stat.st_mode)) + if (!S_ISREG(path_stat.st_mode)) { + fclose(fp); return; + } do { r = fscanf(fp, "%x %x", &reginit.address, &reginit.data); -- 1.9.1

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[U-Boot] [PATCH 0/3] ARM: fix the Kconfig misconversion of CONFIG_USE_ARCH_MEMCPY/MEMSET
by Masahiro Yamada 29 Dec '16

29 Dec '16

Masahiro Yamada (3): ARM: revive CONFIG_USE_ARCH_MEMCPY/MEMSET for UniPhier and Tegra common/init: remove meaningless defined(CONFIG_USE_ARCH_MEMSET) README: remove description about CONFIG_USE_ARCH_MEMCPY/SET README | 6 ------ arch/arm/Kconfig | 4 ++-- arch/arm/include/asm/string.h | 4 ++-- common/init/board_init.c | 4 +--- 4 files changed, 5 insertions(+), 13 deletions(-) -- 2.7.4

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[U-Boot] [PATCH] doc/README.cfi: Update code snippet for flash_cmd_reset()
by Robert P. J. Day 29 Dec '16

29 Dec '16

Minor update in code snippet in the doc file to match source. Signed-off-by: Robert P. J. Day <rpjday(a)crashcourse.ca> --- diff --git a/doc/README.cfi b/doc/README.cfi index 81e7cf1..6b8be41 100644 --- a/doc/README.cfi +++ b/doc/README.cfi @@ -1,7 +1,7 @@ The common CFI driver provides this weak default implementation for flash_cmd_reset(): -void __flash_cmd_reset(flash_info_t *info) +static void __flash_cmd_reset(flash_info_t *info) { /* * We do not yet know what kind of commandset to use, so we issue @@ -9,12 +9,12 @@ void __flash_cmd_reset(flash_info_t *info) * that AMD flash roms ignore the Intel command. */ flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + udelay(1); flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); } void flash_cmd_reset(flash_info_t *info) __attribute__((weak,alias("__flash_cmd_reset"))); - Some flash chips seems to have trouble with this reset sequence. In this case the board specific code can override this weak default version with a board specific function. For example the digsy_mtc board equipped with the M29W128GH -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

1 0

[U-Boot] [PATCH v2 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10
by Chee Tien Fong 29 Dec '16

29 Dec '16

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Add remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> Reviewed-by: Stefan Roese <sr(a)denx.de> --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index a7056d4..902c321 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -29,6 +29,9 @@ #define SOCFPGA_MPUL2_ADDRESS 0xfffff000 #define SOCFPGA_I2C0_ADDRESS 0xffc02200 #define SOCFPGA_I2C1_ADDRESS 0xffc02300 +#define SOCFPGA_I2C2_ADDRESS 0xffc02400 +#define SOCFPGA_I2C3_ADDRESS 0xffc02500 +#define SOCFPGA_I2C4_ADDRESS 0xffc02600 #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 -- 2.2.2

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[U-Boot] curious snippet in drivers/mtd/dataflash.c
by Robert P. J. Day 28 Dec '16

28 Dec '16

not sure about this bit of code in that source file: /* Set the environment according to the label...*/ if(protected == FLAG_PROTECT_INVALID) { dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_INVALID; } else { dataflash_info[i].Device.area_list[j].protected = protected; } is that not just setting the value to "protected" in both cases? what is the point of that conditional? rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] i'm assuming comment "/* board/?/flash.c */" in flash.h is way obsolete
by Robert P. J. Day 28 Dec '16

28 Dec '16

digging around in CONFIG_SYS_FLASH_PROTECTION, and i see this snippet in include/flash.h: /* board/?/flash.c */ #if defined(CONFIG_SYS_FLASH_PROTECTION) extern int flash_real_protect(flash_info_t *info, long sector, int prot); extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len); extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len); #endif /* CONFIG_SYS_FLASH_PROTECTION */ i'm assuming that opening comment is long-since obsolete, yes? i can submit a patch to trash it, but since i'm poring over that file, i can collect any other tweaks anyone else wants to suggest to make it worth it. any other content in that file that needs updating or removal? no rush. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

1 0

[U-Boot] [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system initialization
by Zhiqiang Hou 28 Dec '16

28 Dec '16

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- V3: - Generate the patch set base on the latest git://git.denx.de/u-boot-fsl-qoriq.git. - Use the Kconfig instead of header file to add CONFIG_* arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 76 ++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68 ++++++++++++++----- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + include/configs/ls1012a_common.h | 6 +- include/configs/ls1043a_common.h | 3 +- include/configs/ls1046a_common.h | 3 +- include/configs/ls2080aqds.h | 2 - include/configs/ls2080ardb.h | 1 - 9 files changed, 134 insertions(+), 29 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index cc0dc88..de1e5a4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -87,6 +87,82 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +menu "Layerscape clock tree configuration" + depends on FSL_LSCH2 || FSL_LSCH3 + +config SYS_FSL_CLK + bool "Enable clock tree initialization" + default y + +config CLUSTER_CLK_FREQ + int "Reference clock of core cluster" + depends on ARCH_LS1012A + default 100000000 + help + This number is the reference clock frequency of core PLL. + For most platforms, the core PLL and Platform PLL have the same + reference clock, but for some platforms, LS1012A for instance, + they are provided sepatately. + +config SYS_FSL_PCLK_DIV + int "Platform clock divider" + default 1 if ARCH_LS1043A + default 1 if ARCH_LS1046A + default 2 + help + This is the divider that is used to derive Platform clock from + Platform PLL, in another word: + Platform_clk = Platform_PLL_freq / this_divider + +config SYS_FSL_DSPI_CLK_DIV + int "DSPI clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive DSPI clock from Platform + PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. + +config SYS_FSL_DUART_CLK_DIV + int "DUART clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive DUART clock from Platform + PLL, in another word DUART_clk = Platform_PLL_freq / this_divider. + +config SYS_FSL_I2C_CLK_DIV + int "I2C clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive I2C clock from Platform + PLL, in another word I2C_clk = Platform_PLL_freq / this_divider. + +config SYS_FSL_IFC_CLK_DIV + int "IFC clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive IFC clock from Platform + PLL, in another word IFC_clk = Platform_PLL_freq / this_divider. + +config SYS_FSL_LPUART_CLK_DIV + int "LPUART clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive LPUART clock from Platform + PLL, in another word LPUART_clk = Platform_PLL_freq / this_divider. + +config SYS_FSL_SDHC_CLK_DIV + int "SDHC clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive SDHC clock from Platform + PLL, in another word SDHC_clk = Platform_PLL_freq / this_divider. +endmenu + config NUM_DDR_CONTROLLERS int "Maximum DDR controllers" default 3 if ARCH_LS2080A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 467d9af..3bdeb0e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -345,8 +345,9 @@ int print_cpuinfo(void) (type == TY_ITYP_VER_A72 ? "A72" : " "))), strmhz(buf, sysinfo.freq_processor[core])); } + /* Display platform clock as Bus frequency. */ printf("\n Bus: %-4s MHz ", - strmhz(buf, sysinfo.freq_systembus)); + strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV)); printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); #ifdef CONFIG_SYS_DPAA_FMAN printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 55005f0..f216231 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info) uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + unsigned long cluster_clk; sys_info->freq_systembus = sysclk; +#ifndef CONFIG_CLUSTER_CLK_FREQ +#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ +#endif + cluster_clk = CONFIG_CLUSTER_CLK_FREQ; + #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; #else sys_info->freq_ddrbus = sysclk; #endif -#ifdef CONFIG_ARCH_LS1012A - sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; -#else + /* The freq_systembus is used to record frequency of platform PLL */ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; + +#ifdef CONFIG_ARCH_LS1012A + sys_info->freq_ddrbus = 2 * sys_info->freq_systembus; +#else sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; @@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info) for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; if (ratio[i] > 4) - freq_c_pll[i] = sysclk * ratio[i]; + freq_c_pll[i] = cluster_clk * ratio[i]; else freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } @@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#ifdef CONFIG_ARCH_LS1012A - sys_info->freq_systembus = sys_info->freq_ddrbus / 2; - sys_info->freq_ddrbus *= 2; -#endif - #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 #ifdef CONFIG_SYS_DPAA_FMAN @@ -148,7 +149,8 @@ void get_sys_info(struct sys_info *sys_info) break; } #else - sys_info->freq_sdhc = sys_info->freq_systembus; + sys_info->freq_sdhc = sys_info->freq_systembus / + CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif #endif @@ -166,7 +168,7 @@ int get_clocks(void) get_sys_info(&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; - gd->bus_clk = sys_info.freq_systembus; + gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV; gd->mem_clk = sys_info.freq_ddrbus; #ifdef CONFIG_FSL_ESDHC @@ -179,41 +181,73 @@ int get_clocks(void) return 1; } +/******************************************** + * get_bus_freq + * return platform clock in Hz + *********************************************/ ulong get_bus_freq(ulong dummy) { + if (!gd->bus_clk) + get_clocks(); + return gd->bus_clk; } ulong get_ddr_freq(ulong dummy) { + if (!gd->mem_clk) + get_clocks(); + return gd->mem_clk; } #ifdef CONFIG_FSL_ESDHC int get_sdhc_freq(ulong dummy) { + if (!gd->arch.sdhc_clk) + get_clocks(); + return gd->arch.sdhc_clk; } #endif int get_serial_clock(void) { - return gd->bus_clk; + return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; +} + +int get_i2c_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV; +} + +int get_dspi_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; } +#ifdef CONFIG_FSL_LPUART +int get_uart_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV; +} +#endif + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { case MXC_I2C_CLK: - return get_bus_freq(0); + return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: - return get_bus_freq(0); + return get_dspi_freq(0); +#ifdef CONFIG_FSL_LPUART case MXC_UART_CLK: - return get_bus_freq(0); + return get_uart_freq(0); +#endif default: printf("Unsupported clock\n"); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index b3cfd89..6ace3da 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -137,6 +137,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; + /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus; diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 20f0c61..910835e 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40100000 -#define CONFIG_SYS_FSL_CLK -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 125000000 +#define CONFIG_SYS_CLK_FREQ 125000000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 @@ -82,7 +80,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index c1e3ec6..f7a4397 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -11,7 +11,6 @@ #define CONFIG_FSL_LAYERSCAPE #define CONFIG_LS1043A #define CONFIG_MP -#define CONFIG_SYS_FSL_CLK #define CONFIG_GICV2 #include <asm/arch/config.h> @@ -42,7 +41,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 3887faa..b51e8bf 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -10,7 +10,6 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE #define CONFIG_MP -#define CONFIG_SYS_FSL_CLK #define CONFIG_GICV2 #include <asm/arch/config.h> @@ -41,7 +40,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 838568f..793e1ac 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -14,8 +14,6 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif -#define CONFIG_SYS_FSL_CLK - #ifdef CONFIG_FSL_QSPI #define CONFIG_SYS_NO_FLASH #undef CONFIG_CMD_IMLS diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 31df781..76e8622 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -32,7 +32,6 @@ unsigned long get_board_sys_clk(void); #endif -#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ 133333333 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) -- 2.1.0.27.g96db324

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