October 2016 - U-Boot

[U-Boot] imx53 performance issue after updating to version 2016.9 (tftp download, hash calculation)
by Martin Reichherzer 05 Oct '16

05 Oct '16

After updating a mx53 based custom design to u-boot version 2016.9 from 2013.10 I’m facing performance problems. Change in performance can be observed e.g. during following situations: - TFTP download has decreased from 3 MiB/s to only 517.6 KiB/s - Hash value calculation (sha1) during FIT image format check. Hash calculation now takes a noticeable amount of time instead of finishing virtually immediately. Unfortunately I don’t have access to a Freescale evaluation board to cross check my problems with another i.Mx53 based design. My first assumption was a connection with caching, but according to lowlevel_init.S L2 cache is enabled. Same for D-cache and I-cache. Is anybody facing the same problems or could state information about the behavior on other MX53 boards? Any other suggestions? Regards Martin

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Re: [U-Boot] x86: SPI-NOR (MTD): ACPI missing?
by Bin Meng 05 Oct '16

05 Oct '16

+ML since others may be interested in it Hi Stefan, On Wed, Oct 5, 2016 at 3:30 PM, Stefan Roese <sr(a)denx.de> wrote: > Hi Bin, > > I do have a quick questions for you: > > I'm currently trying to integrate the MTD SPI NOR support for > BayTrail. For this I've integrated this patch series on top > of v4.8: > > https://lkml.org/lkml/2016/8/15/55 Can you point me the v3 diffs? (like a patchwork link). From http://lists.infradead.org/pipermail/linux-mtd/2016-June/068280.html, v2 patch does not use ACPI. > > First tests show that the driver probe / init is not called > at all. Is my assumption correct that some ACPI code might be > missing in U-Boot so that the driver will get instantiated in > Linux? If yes, could you give me a quick hint, what might be > missing? Perhaps point to some other driver example that also > needs such ACPI code in the bootloader that you already > integrated? > It may be caused by a kernel config that does not include this driver. Regards, Bin

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[U-Boot] [PATCH v2] x86: Fix Linux v4.7+ zimage booting (update bootparam.h)
by Stefan Roese 05 Oct '16

05 Oct '16

Booting Linux kernel v4.7+ does not work since commit Linux commit 974f221c "x86/boot: Move compressed kernel to the end of the decompression buffer". This patch adds the latest version of the setup_header struct, adding "init_size" which is needed since this commit referenced above. With this patch, booting Linux v4.8-rc8 does work again on x86 boards. Signed-off-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> Tested-by: Bin Meng <bmeng.cn(a)gmail.com> --- v2: - Specified that the refereced git commit is a Linux commit as suggested by Bin arch/x86/include/asm/bootparam.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h index 1400951..a373a79 100644 --- a/arch/x86/include/asm/bootparam.h +++ b/arch/x86/include/asm/bootparam.h @@ -63,6 +63,9 @@ struct setup_header { __u32 payload_offset; __u32 payload_length; __u64 setup_data; + __u64 pref_address; + __u32 init_size; + __u32 handover_offset; } __attribute__((packed)); struct sys_desc_table { -- 2.9.3

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[U-Boot] [PATCH v2 6/8] arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to Kconfig
by York Sun 05 Oct '16

05 Oct '16

Move these options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun(a)nxp.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/arm/cpu/armv7/ls102xa/Kconfig | 11 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 16 ++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 ----- arch/arm/include/asm/arch-ls102xa/config.h | 2 -- include/configs/ls1012a_common.h | 2 -- include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atwr.h | 2 -- include/configs/ls1043a_common.h | 3 --- include/configs/ls1043aqds.h | 2 -- include/configs/ls1046a_common.h | 3 --- include/configs/ls1046aqds.h | 2 -- include/configs/ls2080a_common.h | 3 --- 12 files changed, 27 insertions(+), 26 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 88983f4..17f1975 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,6 +1,8 @@ config ARCH_LS1021A bool select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES menu "LS102xA architecture" depends on ARCH_LS1021A @@ -23,6 +25,15 @@ config MAX_CPUS config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" +config SYS_FSL_SRDS_1 + bool + +config SYS_FSL_SRDS_2 + bool + +config SYS_HAS_SERDES + bool + config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f683a14..66e509e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -12,16 +12,23 @@ config ARCH_LS1043A config ARCH_LS1046A bool select FSL_LSCH2 + select SYS_FSL_SRDS_2 config ARCH_LS2080A bool select FSL_LSCH3 + select SYS_FSL_HAS_DP_DDR + select SYS_FSL_SRDS_2 config FSL_LSCH2 bool + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES config FSL_LSCH3 bool + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3 @@ -60,4 +67,13 @@ config SYS_FSL_IFC_BANK_COUNT config SYS_FSL_HAS_DP_DDR bool +config SYS_FSL_SRDS_1 + bool + +config SYS_FSL_SRDS_2 + bool + +config SYS_HAS_SERDES + bool + endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6ee75cb..3039e72 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -32,8 +32,6 @@ #ifdef CONFIG_LS2080A #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 -#define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_PAGE_SIZE 0x10000 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 @@ -162,8 +160,6 @@ #define CONFIG_SYS_FSL_PEX_LUT_BE #define CONFIG_SYS_FSL_SEC_BE -#define CONFIG_SYS_FSL_SRDS_1 - /* SoC related */ #ifdef CONFIG_LS1043A #define CONFIG_SYS_FMAN_V3 @@ -212,7 +208,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SNVS_LE diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 70cc703..dfcb546 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -120,8 +120,6 @@ #define DCU_LAYER_MAX_NUM 16 -#define CONFIG_SYS_FSL_SRDS_1 - #ifdef CONFIG_LS102XA #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 1056755..ced8ead 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -10,8 +10,6 @@ #define CONFIG_FSL_LAYERSCAPE #define CONFIG_GICV2 -#define CONFIG_SYS_HAS_SERDES - #include <asm/arch/config.h> #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 0d72e69..5ff3db6 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -143,8 +143,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_HAS_SERDES - #define CONFIG_FSL_CAAM /* Enable CAAM */ #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index e5ac50e..67b43c6 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -170,8 +170,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_HAS_SERDES - #define CONFIG_FSL_CAAM /* Enable CAAM */ #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index ac86c08..3a85b6a 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -15,9 +15,6 @@ #define CONFIG_GICV2 #include <asm/arch/config.h> -#ifdef CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_HAS_SERDES -#endif /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index a80e33d..b18fcc0 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -52,8 +52,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_HAS_SERDES - #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET #define CONFIG_PHYLIB diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index ec6c908..c4bbd56 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -14,9 +14,6 @@ #define CONFIG_GICV2 #include <asm/arch/config.h> -#ifdef CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_HAS_SERDES -#endif /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 2e5c2f1..d1adf3f 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -49,8 +49,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_HAS_SERDES - /* DSPI */ #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index d9eea09..187aee1 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -15,9 +15,6 @@ #include <asm/arch/ls2080a_stream_id.h> #include <asm/arch/config.h> -#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) -#define CONFIG_SYS_HAS_SERDES -#endif /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -- 2.7.4

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[U-Boot] [PATCH v2 5/8] arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to Kconfig
by York Sun 04 Oct '16

04 Oct '16

Move this option to Kconfig and clean up existing uses. NUM_DDR_CONTROLLERS is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun(a)nxp.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 --- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index aa412ec..f683a14 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -45,6 +45,11 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config NUM_DDR_CONTROLLERS + int "Maximum DDR controllers" + default 3 if ARCH_LS2080A + default 1 + config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A @@ -52,4 +57,7 @@ config SYS_FSL_IFC_BANK_COUNT default 4 if ARCH_LS1046A default 8 if ARCH_LS2080A +config SYS_FSL_HAS_DP_DDR + bool + endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 2f10ab7..6ee75cb 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -30,8 +30,6 @@ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ #ifdef CONFIG_LS2080A -#define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 @@ -150,7 +148,6 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ -- 2.7.4

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[U-Boot] [PATCH v2 4/8] arm: Move SYS_FSL_IFC_BANK_COUNT to Kconfig
by York Sun 04 Oct '16

04 Oct '16

Move this option to Kconfig and clean up existing uses. This option is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun(a)nxp.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/arm/cpu/armv7/ls102xa/Kconfig | 5 +++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 --- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index e8264f5..88983f4 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -23,4 +23,9 @@ config MAX_CPUS config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" +config SYS_FSL_IFC_BANK_COUNT + int "Maximum banks of Integrated flash controller" + depends on ARCH_LS1021A + default 8 + endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 6d87fd8..aa412ec 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -45,4 +45,11 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config SYS_FSL_IFC_BANK_COUNT + int "Maximum banks of Integrated flash controller" + depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + default 4 if ARCH_LS1043A + default 4 if ARCH_LS1046A + default 8 if ARCH_LS2080A + endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 572fa94..2f10ab7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -30,7 +30,6 @@ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ #ifdef CONFIG_LS2080A -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } @@ -174,7 +173,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -213,7 +211,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -- 2.7.4

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[U-Boot] [PATCH v2 3/8] arm: Move MAX_CPUS to Kconfig
by York Sun 04 Oct '16

04 Oct '16

Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This option is used by Freescale Layerscape SoCs. Signed-off-by: York Sun <york.sun(a)nxp.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/arm/cpu/armv7/ls102xa/Kconfig | 11 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 13 +++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ---- arch/arm/include/asm/arch-ls102xa/config.h | 1 - 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 2648416..e8264f5 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -9,6 +9,17 @@ config LS1_DEEP_SLEEP bool "Deep sleep" depends on ARCH_LS1021A +config MAX_CPUS + int "Maximum number of CPUs permitted for LS102xA" + depends on ARCH_LS1021A + default 2 + help + Set this number to the maximum number of possible CPUs in the SoC. + SoCs may have multiple clusters with each cluster may have multiple + ports. If some ports are reserved but higher ports are used for + cores, count the reserved ports. This will allocate enough memory + in spin table to properly handle all cores. + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5619e0d..6d87fd8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -32,4 +32,17 @@ config SYS_FSL_MMDC config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" +config MAX_CPUS + int "Maximum number of CPUs permitted for Layerscape" + default 4 if ARCH_LS1043A + default 4 if ARCH_LS1046A + default 16 if ARCH_LS2080A + default 1 + help + Set this number to the maximum number of possible CPUs in the SoC. + SoCs may have multiple clusters with each cluster may have multiple + ports. If some ports are reserved but higher ports are used for + cores, count the reserved ports. This will allocate enough memory + in spin table to properly handle all cores. + endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a5c6c4c..572fa94 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -30,7 +30,6 @@ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ #ifdef CONFIG_LS2080A -#define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ @@ -171,7 +170,6 @@ /* SoC related */ #ifdef CONFIG_LS1043A -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 @@ -206,13 +204,11 @@ #define CONFIG_SYS_FSL_ERRATUM_A009660 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_ARCH_LS1012A) -#define CONFIG_MAX_CPUS 1 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 #elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index fab8774..70cc703 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -123,7 +123,6 @@ #define CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_LS102XA -#define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -- 2.7.4

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[U-Boot] [PATCH v5 00/21] imx6: Add Engicam i.CoreM6 QDL support
by Jagan Teki 04 Oct '16

04 Oct '16

From: Jagan Teki <jagan(a)amarulasolutions.com> This series supports Engicam i.CoreM6 QDL modules on top of u-boot-imx.git/next and test on the respective starter kits as well. Tested both MMC and NAND boot. Changes for v5: - Add NAND support Changes for v4: - Add 'net: Kconfig: Add FEC_MXC entry' patch - Updated ENV configs along with comments - Restructured configs for more readability - Add CONFIG_ENV_OVERWRITE - Rename icorem6qdl_defconfig with icorem6qdl_mmc_defconfig Changes for v3: - Remove "v2 01/17 imx: iomux-v3: Fix build error with snvs base" patch - Remove 'default n' on Kconfig DEFAULT_FDT_FILE patch - Add minimal devicetree support for Engicam i.CoreM6 QDL - Add is_mx6dl() - Add is_mx6solo() - Use is_mx6dq() - Add last commit sha1 and header in pull devicetree files from Linux Changes for v2: - Make static to local iomux structure in board file - Corrected rowaddr in mx6_ddr3_cfg - Used imx_ddr_size - Add FEC support and tested the same - Add DM_GPIO, DM_MMC support - Add pinctrl support - Add devicetree support Jagan Teki (21): serial: Kconfig: Add MXC_UART entry thermal: Kconfig: Add IMX_THERMAL entry Kconfig: Add DEFAULT_FDT_FILE entry arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support net: Kconfig: Add FEC_MXC entry imx6: icorem6: Add ENET support imx: s/docs\/README.imximage/doc\/README.imximage/g arm: dts: Add devicetree for i.MX6DL arm: dts: Add devicetree for i.MX6DQL arm: dts: imx6dl: Add pinctrl defines dt-bindings: clock: imx6qdl: Add clock defines arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/Solo imx6q: icorem6: Enable pinctrl driver engicam: icorem6: Add DM_GPIO, DM_MMC support arm: dts: Add devicetree for i.MX6Q arm: dts: imx6q: Add pinctrl defines arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/Dual mtd: nand: Kconfig: Add NAND_MXS entry imx6: icorem6: Add NAND support imx6: icorem6: Enable MTD device support imx6: icorem6: Add default mtd nand partition table arch/arm/cpu/armv7/mx6/Kconfig | 11 + arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6dl-icore.dts | 59 ++ arch/arm/dts/imx6dl-pinfunc.h | 1091 +++++++++++++++++++++++ arch/arm/dts/imx6dl.dtsi | 133 +++ arch/arm/dts/imx6q-icore.dts | 59 ++ arch/arm/dts/imx6q-pinfunc.h | 1047 ++++++++++++++++++++++ arch/arm/dts/imx6q.dtsi | 300 +++++++ arch/arm/dts/imx6qdl-icore.dtsi | 196 ++++ arch/arm/dts/imx6qdl.dtsi | 1281 +++++++++++++++++++++++++++ arch/arm/include/asm/imx-common/sys_proto.h | 2 + board/barco/titanium/imximage.cfg | 2 +- board/ccv/xpress/imximage.cfg | 2 +- board/denx/m53evk/imximage.cfg | 2 +- board/engicam/icorem6/Kconfig | 12 + board/engicam/icorem6/MAINTAINERS | 6 + board/engicam/icorem6/Makefile | 6 + board/engicam/icorem6/README | 38 + board/engicam/icorem6/icorem6.c | 537 +++++++++++ board/freescale/mx6sabresd/mx6dlsabresd.cfg | 2 +- board/freescale/mx6slevk/imximage.cfg | 2 +- board/freescale/mx6ullevk/imximage.cfg | 2 +- board/freescale/mx7dsabresd/imximage.cfg | 2 +- board/freescale/s32v234evb/s32v234evb.cfg | 2 +- board/freescale/vf610twr/imximage.cfg | 2 +- board/phytec/pcm052/imximage.cfg | 2 +- board/technexion/pico-imx6ul/imximage.cfg | 2 +- board/toradex/colibri_imx7/imximage.cfg | 2 +- board/toradex/colibri_vf/imximage.cfg | 2 +- board/warp/imximage.cfg | 2 +- board/warp7/imximage.cfg | 2 +- common/Kconfig | 5 + configs/imx6qdl_icore_mmc_defconfig | 34 + configs/imx6qdl_icore_nand_defconfig | 30 + drivers/mtd/nand/Kconfig | 7 + drivers/net/Kconfig | 7 + drivers/serial/Kconfig | 7 + drivers/thermal/Kconfig | 13 + include/configs/imx6qdl_icore.h | 168 ++++ include/dt-bindings/clock/imx6qdl-clock.h | 274 ++++++ 40 files changed, 5341 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/imx6dl-icore.dts create mode 100644 arch/arm/dts/imx6dl-pinfunc.h create mode 100644 arch/arm/dts/imx6dl.dtsi create mode 100644 arch/arm/dts/imx6q-icore.dts create mode 100644 arch/arm/dts/imx6q-pinfunc.h create mode 100644 arch/arm/dts/imx6q.dtsi create mode 100644 arch/arm/dts/imx6qdl-icore.dtsi create mode 100644 arch/arm/dts/imx6qdl.dtsi create mode 100644 board/engicam/icorem6/Kconfig create mode 100644 board/engicam/icorem6/MAINTAINERS create mode 100644 board/engicam/icorem6/Makefile create mode 100644 board/engicam/icorem6/README create mode 100644 board/engicam/icorem6/icorem6.c create mode 100644 configs/imx6qdl_icore_mmc_defconfig create mode 100644 configs/imx6qdl_icore_nand_defconfig create mode 100644 include/configs/imx6qdl_icore.h create mode 100644 include/dt-bindings/clock/imx6qdl-clock.h -- 2.7.4

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[U-Boot] [PATCH v4 1/3] net: fec_mxc: Convert into driver model
by Jagan Teki 04 Oct '16

04 Oct '16

From: Jagan Teki <jagan(a)amarulasolutions.com> This patch add driver model support for fec_mxc driver. Cc: Simon Glass <sjg(a)chromium.org> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Michael Trimarchi <michael(a)amarulasolutions.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/net/fec_mxc.c | 273 +++++++++++++++++++++++++++++++++++++++++++++----- drivers/net/fec_mxc.h | 11 ++ 2 files changed, 258 insertions(+), 26 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 8e3b839..a58ab19 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <dm.h> #include <malloc.h> #include <memalign.h> #include <net.h> @@ -362,17 +363,32 @@ static void fec_rbd_clean(int last, struct fec_bd *pRbd) writew(0, &pRbd->data_length); } +#ifdef CONFIG_DM_ETH +static int fec_get_hwaddr(struct udevice *dev, int dev_id, + unsigned char *mac) +#else static int fec_get_hwaddr(struct eth_device *dev, int dev_id, unsigned char *mac) +#endif { imx_get_mac_from_fuse(dev_id, mac); return !is_valid_ethaddr(mac); } +#ifdef CONFIG_DM_ETH +static int fecmxc_set_hwaddr(struct udevice *dev) +#else static int fec_set_hwaddr(struct eth_device *dev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + uchar *mac = pdata->enetaddr; +#else uchar *mac = dev->enetaddr; struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif writel(0, &fec->eth->iaddr1); writel(0, &fec->eth->iaddr2); @@ -427,9 +443,17 @@ static void fec_reg_setup(struct fec_priv *fec) * Start the FEC engine * @param[in] dev Our device to handle */ +#ifdef CONFIG_DM_ETH +static int fec_open(struct udevice *dev) +#else static int fec_open(struct eth_device *edev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)edev->priv; +#endif int speed; uint32_t addr, size; int i; @@ -535,14 +559,26 @@ static int fec_open(struct eth_device *edev) return 0; } +#ifdef CONFIG_DM_ETH +static int fecmxc_init(struct udevice *dev) +#else static int fec_init(struct eth_device *dev, bd_t* bd) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; int i; /* Initialize MAC address */ +#ifdef CONFIG_DM_ETH + fecmxc_set_hwaddr(dev); +#else fec_set_hwaddr(dev); +#endif /* * Setup transmit descriptors, there are two in total. @@ -596,9 +632,17 @@ static int fec_init(struct eth_device *dev, bd_t* bd) * Halt the FEC engine * @param[in] dev Our device to handle */ +#ifdef CONFIG_DM_ETH +static void fecmxc_halt(struct udevice *dev) +#else static void fec_halt(struct eth_device *dev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif int counter = 0xffff; /* @@ -638,7 +682,11 @@ static void fec_halt(struct eth_device *dev) * @param[in] length Data count in bytes * @return 0 on success */ +#ifdef CONFIG_DM_ETH +static int fecmxc_send(struct udevice *dev, void *packet, int length) +#else static int fec_send(struct eth_device *dev, void *packet, int length) +#endif { unsigned int status; uint32_t size, end; @@ -650,7 +698,11 @@ static int fec_send(struct eth_device *dev, void *packet, int length) * This routine transmits one frame. This routine only accepts * 6-byte Ethernet addresses. */ +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif /* * Check for valid length of data. @@ -783,9 +835,17 @@ out: * @param[in] dev Our ethernet device to handle * @return Length of packet read */ +#ifdef CONFIG_DM_ETH +static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) +#else static int fec_recv(struct eth_device *dev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; unsigned long ievent; int frame_length, len = 0; @@ -801,8 +861,13 @@ static int fec_recv(struct eth_device *dev) writel(ievent, &fec->eth->ievent); debug("fec_recv: ievent 0x%lx\n", ievent); if (ievent & FEC_IEVENT_BABR) { +#ifdef CONFIG_DM_ETH + fecmxc_halt(dev); + fecmxc_init(dev); +#else fec_halt(dev); fec_init(dev, fec->bd); +#endif printf("some error: 0x%08lx\n", ievent); return 0; } @@ -814,10 +879,18 @@ static int fec_recv(struct eth_device *dev) if (ievent & FEC_IEVENT_GRA) { /* Graceful stop complete */ if (readl(&fec->eth->x_cntrl) & 0x00000001) { +#ifdef CONFIG_DM_ETH + fecmxc_halt(dev); +#else fec_halt(dev); +#endif writel(~0x00000001 & readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl); +#ifdef CONFIG_DM_ETH + fecmxc_init(dev); +#else fec_init(dev, fec->bd); +#endif } } @@ -971,6 +1044,33 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); } +struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) +{ + struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; + struct mii_dev *bus; + int ret; + + bus = mdio_alloc(); + if (!bus) { + printf("mdio_alloc failed\n"); + return NULL; + } + bus->read = fec_phy_read; + bus->write = fec_phy_write; + bus->priv = eth; + fec_set_dev_name(bus->name, dev_id); + + ret = mdio_register(bus); + if (ret) { + printf("mdio_register failed\n"); + free(bus); + return NULL; + } + fec_mii_setspeed(eth); + return bus; +} + +#ifndef CONFIG_DM_ETH #ifdef CONFIG_PHYLIB int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, struct mii_dev *bus, struct phy_device *phydev) @@ -1062,32 +1162,6 @@ err1: return ret; } -struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) -{ - struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; - struct mii_dev *bus; - int ret; - - bus = mdio_alloc(); - if (!bus) { - printf("mdio_alloc failed\n"); - return NULL; - } - bus->read = fec_phy_read; - bus->write = fec_phy_write; - bus->priv = eth; - fec_set_dev_name(bus->name, dev_id); - - ret = mdio_register(bus); - if (ret) { - printf("mdio_register failed\n"); - free(bus); - return NULL; - } - fec_mii_setspeed(eth); - return bus; -} - int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) { uint32_t base_mii; @@ -1147,3 +1221,150 @@ int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) return 0; } #endif + +#else + +static const struct eth_ops fecmxc_ops = { + .start = fecmxc_init, + .send = fecmxc_send, + .recv = fecmxc_recv, + .stop = fecmxc_halt, + .write_hwaddr = fecmxc_set_hwaddr, +}; + +static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) +{ + struct phy_device *phydev; + int mask = 0xffffffff; + +#ifdef CONFIG_PHYLIB + mask = 1 << CONFIG_FEC_MXC_PHYADDR; +#endif + + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +static int fecmxc_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct fec_priv *priv = dev_get_priv(dev); + struct mii_dev *bus = NULL; + int dev_id = -1; + unsigned char ethaddr[6]; + uint32_t start; + int ret; + + ret = fec_alloc_descs(priv); + if (ret) + return ret; + + bus = fec_get_miibus((uint32_t)priv->eth, dev_id); + if (!bus) + goto err_mii; + + priv->bus = bus; + priv->xcv_type = CONFIG_FEC_XCV_TYPE; + priv->interface = pdata->phy_interface; + ret = fec_phy_init(priv, dev); + if (ret) + goto err_phy; + + /* Reset chip. */ + writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, &priv->eth->ecntrl); + start = get_timer(0); + while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { + if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { + printf("FEC MXC: Timeout reseting chip\n"); + goto err_timeout; + } + udelay(10); + } + + fec_reg_setup(priv); + fec_set_dev_name((char *)dev->name, dev_id); + priv->dev_id = (dev_id == -1) ? 0 : dev_id; + + ret = fec_get_hwaddr(dev, dev_id, ethaddr); + if (!ret) { + debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); + memcpy(pdata->enetaddr, ethaddr, 6); + if (!getenv("ethaddr")) + eth_setenv_enetaddr("ethaddr", ethaddr); + } + + return 0; + +err_timeout: + free(priv->phydev); +err_phy: + mdio_unregister(bus); + free(bus); +err_mii: + fec_free_descs(priv); + return ret; +} + +static int fecmxc_remove(struct udevice *dev) +{ + struct fec_priv *priv = dev_get_priv(dev); + + free(priv->phydev); + fec_free_descs(priv); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +static int fecmxc_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct fec_priv *priv = dev_get_priv(dev); + const char *phy_mode; + + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + priv->eth = (struct ethernet_regs *)pdata->iobase; + + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + /* TODO + * Need to get the reset-gpio and related properties from DT + * and implemet the enet reset code on .probe call + */ + + return 0; +} + +static const struct udevice_id fecmxc_ids[] = { + { .compatible = "fsl,imx6q-fec" }, + { } +}; + +U_BOOT_DRIVER(fecmxc_gem) = { + .name = "fecmxc", + .id = UCLASS_ETH, + .of_match = fecmxc_ids, + .ofdata_to_platdata = fecmxc_ofdata_to_platdata, + .probe = fecmxc_probe, + .remove = fecmxc_remove, + .ops = &fecmxc_ops, + .priv_auto_alloc_size = sizeof(struct fec_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; +#endif diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 0717cc6..84f4149 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -18,6 +18,10 @@ #ifndef __FEC_MXC_H #define __FEC_MXC_H +#ifdef CONFIG_DM_GPIO +#include <asm-generic/gpio.h> +#endif + void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); /** @@ -264,6 +268,13 @@ struct fec_priv { int phy_id; int (*mii_postcall)(int); #endif + +#ifdef CONFIG_DM_GPIO + struct gpio_desc reset_gpio; +#endif +#ifdef CONFIG_DM_ETH + u32 interface; +#endif }; /** -- 2.7.4

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[U-Boot] [PATCH v4 0/3] net: fec_mxc: Convert to DM
by Jagan Teki 04 Oct '16

04 Oct '16

From: Jagan Teki <jagan(a)amarulasolutions.com> This series convert fec_mxc to DM and tested both dm and non-dm code and it is on top of u-boot-imx/master Changes for v4: - rebase to u-boot-imx/master Changes for v3: - Add ARM: dts: imx6qdl-icore: Add FEC support - icorem6: Use CONFIG_DM_ETH support Changes for v2: - Add TODO for implementing the enet reset code Jagan Teki (3): net: fec_mxc: Convert into driver model ARM: dts: imx6qdl-icore: Add FEC support icorem6: Use CONFIG_DM_ETH support arch/arm/cpu/armv7/mx6/Kconfig | 1 + arch/arm/dts/imx6qdl-icore.dtsi | 24 +++ board/engicam/icorem6/icorem6.c | 71 --------- configs/imx6qdl_icore_mmc_defconfig | 1 - configs/imx6qdl_icore_nand_defconfig | 1 - drivers/net/fec_mxc.c | 273 +++++++++++++++++++++++++++++++---- drivers/net/fec_mxc.h | 11 ++ 7 files changed, 283 insertions(+), 99 deletions(-) -- 2.7.4

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