October 2016 - U-Boot

[U-Boot] [PATCH v2] ARMv7: LS102xA: Move two macros from header files to Kconfig
by macro.wave.z＠gmail.com 08 Oct '16

08 Oct '16

From: Hongbo Zhang <hongbo.zhang(a)nxp.com> Following commits 217f92b and 1544698, these two config CPU_V7_HAS_NONSEC and CPU_V7_HAS_VIRT are moved to Kconfig, for correctly select ARMV7_PSCI. Signed-off-by: Hongbo Zhang <hongbo.zhang(a)nxp.com> --- arch/arm/Kconfig | 4 ++++ include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atwr.h | 2 -- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1560bcc..7fcb1cb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -818,12 +818,16 @@ config TARGET_LS1021AQDS select CPU_V7 select SUPPORT_SPL select ARCH_SUPPORT_PSCI + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT config TARGET_LS1021ATWR bool "Support ls1021atwr" select CPU_V7 select SUPPORT_SPL select ARCH_SUPPORT_PSCI + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT config TARGET_LS1043AQDS bool "Support ls1043aqds" diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5aaecc7..7b608c1 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -563,8 +563,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING -#define CONFIG_ARMV7_NONSEC -#define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index ef238a4..d946224 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -425,8 +425,6 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING -#define CONFIG_ARMV7_NONSEC -#define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -- 2.1.4

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[U-Boot] [PATCH] armv8: fsl-layerscape: Fix "cpu status" command
by York Sun 08 Oct '16

08 Oct '16

The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 21 +++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/mp.c | 16 ++++++++++++---- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 1 + 3 files changed, 34 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index e12b773..e69268a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -201,6 +201,27 @@ static inline u32 initiator_type(u32 cluster, int init_id) return 0; } +u32 cpu_pos_mask(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0; + u32 cluster, type, mask = 0; + + do { + int j; + + cluster = gur_in32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = initiator_type(cluster, j); + if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)) + mask |= 1 << (i * TP_INIT_PER_CLUSTER + j); + } + i++; + } while ((cluster & TP_CLUSTER_EOC) == 0x0); + + return mask; +} + u32 cpu_mask(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index df7ffb8..f607c39 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -104,6 +104,11 @@ int is_core_valid(unsigned int core) return !!((1 << core) & cpu_mask()); } +static int is_pos_valid(unsigned int pos) +{ + return !!((1 << pos) & cpu_pos_mask()); +} + int is_core_online(u64 cpu_id) { u64 *table; @@ -126,9 +131,9 @@ int cpu_disable(int nr) return 0; } -int core_to_pos(int nr) +static int core_to_pos(int nr) { - u32 cores = cpu_mask(); + u32 cores = cpu_pos_mask(); int i, count = 0; if (nr == 0) { @@ -139,14 +144,17 @@ int core_to_pos(int nr) } for (i = 1; i < 32; i++) { - if (is_core_valid(i)) { + if (is_pos_valid(i)) { count++; if (count == nr) break; } } - return count; + if (count != nr) + return -1; + + return i; } int cpu_status(int nr) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index e46e076..f7306ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -34,5 +34,6 @@ void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); void secondary_boot_func(void); int is_core_online(u64 cpu_id); +u32 cpu_pos_mask(void); #endif #endif /* _FSL_LAYERSCAPE_MP_H */ -- 2.7.4

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[U-Boot] [PATCH] armv8/fsl-layerscape: print SoC revsion number
by Wenbin song 08 Oct '16

08 Oct '16

The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song(a)nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 340d9f9..37a96e4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -43,6 +43,9 @@ void cpu_name(char *name) if (IS_E_PROCESSOR(svr)) strcat(name, "E"); + + sprintf(name + strlen(name), " Rev%d.%d", + SVR_MAJ(svr), SVR_MIN(svr)); break; } -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2] fsl_sfp : Modify macros as per changes in SFP v3.4
by Sumit Garg 08 Oct '16

08 Oct '16

SFP v3.4 supports 8 keys in SRK table which leads to corresponding changes in OSPR key revocation field. So modify OSPR_KEY_REVOC_XXX macros accordingly. Signed-off-by: Sumit Garg <sumit.garg(a)nxp.com> --- Changes in v2: Corrected commit message. Also removed whitspace changes in this patch. include/fsl_sfp.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index 2976a2c..d3a2813 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -78,9 +78,16 @@ struct ccsr_sfp_regs { u32 fsl_uid; /* 0xB0 FSL Unique ID */ }; #endif + #define ITS_MASK 0x00000004 #define ITS_BIT 2 -#define OSPR_KEY_REVOC_SHIFT 13 -#define OSPR_KEY_REVOC_MASK 0x0000e000 + +#if defined(CONFIG_SYS_FSL_SFP_VER_3_4) +#define OSPR_KEY_REVOC_SHIFT 9 +#define OSPR_KEY_REVOC_MASK 0x0000fe00 +#else +#define OSPR_KEY_REVOC_SHIFT 13 +#define OSPR_KEY_REVOC_MASK 0x0000e000 +#endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */ #endif -- 1.8.1.4

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[U-Boot] [PATCH] fsl_sec_mon: Update driver for Security Monitor
by Sumit Garg 08 Oct '16

08 Oct '16

Update the API's for transition of Security Monitor states. Instead of providing both initial and final states for transition, just provide final state for transition as Security Monitor driver will take care of it internally. Signed-off-by: Sumit Garg <sumit.garg(a)nxp.com> --- board/freescale/common/fsl_validate.c | 52 ++------ drivers/misc/fsl_sec_mon.c | 240 ++++++++++++++++++---------------- include/fsl_sec_mon.h | 12 +- 3 files changed, 151 insertions(+), 153 deletions(-) diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 37c249d..91e6b50 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -339,27 +339,15 @@ static inline u32 get_key_len(struct fsl_secboot_img_priv *img) */ static void fsl_secboot_header_verification_failure(void) { - struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); /* 29th bit of OSPR is ITS */ u32 its = sfp_in32(&sfp_regs->ospr) >> 2; - /* - * Read the SEC_MON status register - * Read SSM_ST field - */ - sts = sec_mon_in32(&sec_mon_regs->hp_stat); - if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { - if (its == 1) - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_SOFT_FAIL); - else - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_NON_SECURE); - } + if (its == 1) + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); + else + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); printf("Generating reset request\n"); do_reset(NULL, 0, 0, NULL); @@ -376,32 +364,20 @@ static void fsl_secboot_header_verification_failure(void) */ static void fsl_secboot_image_verification_failure(void) { - struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; - /* - * Read the SEC_MON status register - * Read SSM_ST field - */ - sts = sec_mon_in32(&sec_mon_regs->hp_stat); - if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { - if (its == 1) { - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_SOFT_FAIL); - - printf("Generating reset request\n"); - do_reset(NULL, 0, 0, NULL); - /* If reset doesn't coocur, halt execution */ - do_esbc_halt(NULL, 0, 0, NULL); - - } else { - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_NON_SECURE); - } + if (its == 1) { + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); + + printf("Generating reset request\n"); + do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); + + } else { + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); } } diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c index d482a7d..415232e 100644 --- a/drivers/misc/fsl_sec_mon.c +++ b/drivers/misc/fsl_sec_mon.c @@ -7,140 +7,158 @@ #include <common.h> #include <fsl_sec_mon.h> -int change_sec_mon_state(u32 initial_state, u32 final_state) +static u32 get_sec_mon_state(void) { struct ccsr_sec_mon_regs *sec_mon_regs = (void *) (CONFIG_SYS_SEC_MON_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); + return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK; +} + +static int set_sec_mon_state_non_sec(void) +{ + u32 sts; int timeout = 10; + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); - if ((sts & HPSR_SSM_ST_MASK) != initial_state) - return -1; + sts = get_sec_mon_state(); - if (initial_state == HPSR_SSM_ST_TRUST) { - switch (final_state) { - case HPSR_SSM_ST_NON_SECURE: - printf("SEC_MON state transitioning to Soft Fail.\n"); - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV); - - /* - * poll till SEC_MON is in - * Soft Fail state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_SOFT_FAIL)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_SOFT_FAIL) - break; - - udelay(10); - timeout--; - } - } + switch (sts) { + /* + * If initial state is check or Non-Secure, then set the Software + * Security Violation Bit and transition to Non-Secure State. + */ + case HPSR_SSM_ST_CHECK: + printf("SEC_MON state transitioning to Non Secure.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV); - if (timeout == 0) { - printf("SEC_MON state transition timeout.\n"); - return -1; - } + /* polling loop till SEC_MON is in Non Secure state */ + while (timeout) { + sts = get_sec_mon_state(); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_NON_SECURE) + break; + + udelay(10); + timeout--; + } - timeout = 10; + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } + break; + + /* + * If initial state is Trusted, Secure or Soft-Fail, then first set + * the Software Security Violation Bit and transition to Soft-Fail + * State. + */ + case HPSR_SSM_ST_TRUST: + case HPSR_SSM_ST_SECURE: + case HPSR_SSM_ST_SOFT_FAIL: + printf("SEC_MON state transitioning to Soft Fail.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV); + + /* polling loop till SEC_MON is in Soft-Fail state */ + while (timeout) { + sts = get_sec_mon_state(); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_SOFT_FAIL) + break; + + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } + + timeout = 10; + /* + * If SSM Soft Fail to Non-Secure State Transition + * disable is not set, then set SSM_ST bit and + * transition to Non-Secure State. + */ + if ((sec_mon_in32(&sec_mon_regs->hp_com) & + HPCOMR_SSM_SFNS_DIS) == 0) { printf("SEC_MON state transitioning to Non Secure.\n"); sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST); - /* - * poll till SEC_MON is in - * Non Secure state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_NON_SECURE)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_NON_SECURE) - break; - - udelay(10); - timeout--; - } - } + /* polling loop till SEC_MON is in Non Secure*/ + while (timeout) { + sts = get_sec_mon_state(); - if (timeout == 0) { - printf("SEC_MON state transition timeout.\n"); - return -1; - } - break; - case HPSR_SSM_ST_SOFT_FAIL: - printf("SEC_MON state transitioning to Soft Fail.\n"); - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); - - /* - * polling loop till SEC_MON is in - * Soft Fail state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_SOFT_FAIL)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_SOFT_FAIL) - break; - - udelay(10); - timeout--; - } + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_NON_SECURE) + break; + + udelay(10); + timeout--; } if (timeout == 0) { printf("SEC_MON state transition timeout.\n"); return -1; } - break; - default: - return -1; } - } else if (initial_state == HPSR_SSM_ST_NON_SECURE) { - switch (final_state) { - case HPSR_SSM_ST_SOFT_FAIL: - printf("SEC_MON state transitioning to Soft Fail.\n"); - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); - - /* - * polling loop till SEC_MON is in - * Soft Fail state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_SOFT_FAIL)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_SOFT_FAIL) - break; - - udelay(10); - timeout--; - } - } + break; + default: + printf("SEC_MON already in Non Secure state.\n"); + return 0; + } + return 0; +} - if (timeout == 0) { - printf("SEC_MON state transition timeout.\n"); - return -1; - } +static int set_sec_mon_state_soft_fail(void) +{ + u32 sts; + int timeout = 10; + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); + + printf("SEC_MON state transitioning to Soft Fail.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); + + /* polling loop till SEC_MON is in Soft-Fail state */ + while (timeout) { + sts = get_sec_mon_state(); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_SOFT_FAIL) break; - default: - return -1; - } + + udelay(10); + timeout--; } + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } return 0; } + +int set_sec_mon_state(u32 state) +{ + int ret = -1; + + switch (state) { + case HPSR_SSM_ST_NON_SECURE: + ret = set_sec_mon_state_non_sec(); + break; + case HPSR_SSM_ST_SOFT_FAIL: + ret = set_sec_mon_state_soft_fail(); + break; + default: + printf("SEC_MON state transition not supported.\n"); + return 0; + } + + return ret; +} diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h index b6794ce..1f31f88 100644 --- a/include/fsl_sec_mon.h +++ b/include/fsl_sec_mon.h @@ -34,13 +34,16 @@ struct ccsr_sec_mon_regs { u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */ }; -#define HPCOMR_SW_SV 0x100 /* Security Violation bit */ -#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ -#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ +#define HPCOMR_SW_SV 0x100 /* Security Violation bit */ +#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ +#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ +#define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */ +#define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */ #define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */ #define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */ #define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */ #define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */ +#define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */ #define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */ /* @@ -53,6 +56,7 @@ enum { SEC_MON_SW_SV, }; -int change_sec_mon_state(uint32_t initial_state, uint32_t final_state); +/* Transition SEC_MON state */ +int set_sec_mon_state(u32 state); #endif /* __FSL_SEC_MON_H */ -- 1.8.1.4

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[U-Boot] [PATCH 1/2] armv8: fsl-lsch2: adjust sata parameter
by yuantian.tang＠nxp.com 08 Oct '16

08 Oct '16

From: Tang Yuantian <Yuantian.Tang(a)nxp.com> The default values for Port Phy2Cfg register and Port Phy3Cfg register are better, no need to overwrite them. Signed-off-by: Tang Yuantian <yuantian.tang(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 -- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index f62b78d..6333122 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -223,8 +223,6 @@ int sata_init(void) struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); - out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); ahci_init((void __iomem *)CONFIG_SYS_SATA); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 8d4a7ad..d5fe0ce 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -60,8 +60,6 @@ struct cpu_type { /* ahci port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28184d1f -#define AHCI_PORT_PHY_3_CFG 0x0e081509 #define AHCI_PORT_TRANS_CFG 0x08000029 /* AHCI (sata) register map */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] cmd: Make CMD_USB_MASS_STORAGE visible only with USB_GADGET and default y
by Tom Rini 08 Oct '16

08 Oct '16

In order for CMD_USB_MASS_STORAGE to be useful we must have USB_GADGET enabled, so only show this option when USB_GADGET is set. In addition, expand the help text so it's clearer what this does and given the overall utility of this command, make it enabled by default. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- cmd/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index d28da54ed659..ddbd5a82d80f 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -408,10 +408,14 @@ config CMD_DFU Enables the command "dfu" which is used to have U-Boot create a DFU class device via USB. +if USB_GADGET config CMD_USB_MASS_STORAGE bool "UMS usb mass storage" + default y help - USB mass storage support + Enables the command "ums" which is used to have U-Boot expose + local storage such as eMMC as a USB Mass Storage Device class device. +endif config CMD_FPGA bool "fpga" -- 1.9.1

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[U-Boot] [PULL] Please pull u-boot-imx
by Stefano Babic 08 Oct '16

08 Oct '16

Hi Tom, please pull from u-boot-imx, thanks ! The following changes since commit 53fec162061811a73c7dab3207f8fdb2343ae289: Prepare v2016.11-rc1 (2016-10-03 09:28:13 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to 3dddc793e0114eb7dfc68b98a4316644d4031fcb: board: ge: bx50v3: Pass video bootargs for b850v3 (2016-10-07 16:32:28 +0200) ---------------------------------------------------------------- Albert ARIBAUD $3ADEV$ (6): pcm052: fix MTD partitioning pcm052: remove target-specific dtb name from env pcm052: add 'm4go' command tools: mkimage: add support for Vybrid image format pcm052: allow specifying onboard DDR size in configs pcm052: add new BK4r1 target based on PCM052 SoM Fabio Estevam (5): wandboard: Fix hang when going into low frequency wandboard: Remove videoargs script mx6sabresd: Make SPL DDR configuration to match the DCD table README.imx6: Fix Boundary Devices name udoo: Add a README file Filip Brozovic (1): imx: iomux-v3: fix pad setup on i.MX6DQP when CONFIG_MX6QDL is defined Ken Lin (1): board: ge: bx50v3: Pass video bootargs for b850v3 Peng Fan (22): imx: mx6ull: add iomux header file imx: mx6ull: add mx6ull major cpu type imx-common: introduce is_mx6ull imx: ocotp: support i.MX6ULL imx: timer: update gpt driver for i.MX6ULL imx: mx6ull: skip setting ahb clock imx: mx6ul: using runtime check when configuring PMIC_STBY_REQ imx: mx6ull: misc soc update imx: mx6ull: adjust POR_B setting for i.MX6ULL imx: mx6ull: update clock settings and CCM register map imx: mx6ull: Update memory map address imx: mx6ull: Add AIPS3 initialization imx: imx6ull: adjust the ldo 1.2v bandgap voltage imx: iomux: fix snvs usage for i.MX6ULL pinctrl: imx6: support i.MX6ULL arm: dts: imx6ull: add pinctrl defines dt-bindings: add i.mx6ul clock header arm: dts: add device tree for i.MX6ULL dm: mmc: intialize dev when probe arm: imx: add i.MX6ULL 14x14 EVK board support imx-common: enlarge mux width to 4 imx: imx6ul: disable POR_B internal pull up Ross Parker (1): imx_watchdog: Do not assert WDOG_B on watchdog init Soeren Moch (2): board: tbs2910: Fix BOOTMAPSZ board: tbs2910: Add CMD_PART Stefan Agner (12): imx: mx6: fix USB bmode to use reserved value dm: imx: serial: support device tree pinctrl: imx: do not announce driver initialization arm: dts: imx7: add pinctrl defines arm: dts: imx7: add basic i.MX 7/Colibri iMX7 device tree colibri_imx7: remove legancy I2C support colibri_imx7: remove legancy UART platform data power: pmic: add Ricoh RN5T567 PMIC support arm: dts: imx7: add Ricoh RN5T567 PMIC node colibri_imx7: use Ricoh RN5T567 to reboot the board configs: enable device tree for Colibri iMX7 ARM: vf610: use strcpy for soc environment variable Ye Li (1): imx: mx6ull: add kconfig entry for MX6ULL Makefile | 6 + arch/arm/Kconfig | 4 + arch/arm/config.mk | 3 + arch/arm/cpu/armv7/mx6/Kconfig | 11 ++ arch/arm/cpu/armv7/mx6/clock.c | 59 +++--- arch/arm/cpu/armv7/mx6/soc.c | 57 ++++-- arch/arm/cpu/armv7/vf610/Makefile | 5 + arch/arm/cpu/armv7/vf610/generic.c | 2 +- arch/arm/dts/Makefile | 7 +- arch/arm/dts/bk4r1.dts | 48 +++++ arch/arm/dts/imx6ul-pinfunc.h | 938 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6ull-14x14-evk.dts | 527 ++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6ull-pinfunc-snvs.h | 29 +++ arch/arm/dts/imx6ull-pinfunc.h | 57 ++++++ arch/arm/dts/imx6ull.dtsi | 1161 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx7-colibri.dts | 97 ++++++++++ arch/arm/dts/imx7.dtsi | 194 ++++++++++++++++++++ arch/arm/dts/imx7d-pinfunc.h | 1151 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/vf.dtsi | 4 +- arch/arm/imx-common/cpu.c | 2 + arch/arm/imx-common/init.c | 2 +- arch/arm/imx-common/iomux-v3.c | 13 +- arch/arm/imx-common/timer.c | 7 +- arch/arm/include/asm/arch-imx/cpu.h | 3 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 60 +++++- arch/arm/include/asm/arch-mx6/imx-regs.h | 18 +- arch/arm/include/asm/arch-mx6/mx6-pins.h | 2 + arch/arm/include/asm/arch-mx6/mx6ull_pins.h | 1065 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 19 +- arch/arm/include/asm/imx-common/sys_proto.h | 1 + board/freescale/mx6sabresd/mx6sabresd.c | 351 +++++++++++++++++++---------------- board/freescale/mx6ullevk/Kconfig | 12 ++ board/freescale/mx6ullevk/MAINTAINERS | 6 + board/freescale/mx6ullevk/Makefile | 6 + board/freescale/mx6ullevk/imximage.cfg | 116 ++++++++++++ board/freescale/mx6ullevk/mx6ullevk.c | 99 ++++++++++ board/phytec/pcm052/Kconfig | 24 +++ board/phytec/pcm052/pcm052.c | 206 +++++++++++++++------ board/toradex/colibri_imx7/colibri_imx7.c | 92 +++++----- board/udoo/README | 21 +++ board/wandboard/spl.c | 6 +- common/image.c | 1 + configs/bk4r1_defconfig | 33 ++++ configs/colibri_imx7_defconfig | 10 +- configs/mx6ull_14x14_evk_defconfig | 30 +++ doc/README.imx6 | 2 +- doc/device-tree-bindings/pmic/rn5t567.txt | 17 ++ doc/device-tree-bindings/serial/mxc-serial.txt | 8 + drivers/misc/mxc_ocotp.c | 52 +++++- drivers/mmc/fsl_esdhc.c | 1 + drivers/pinctrl/nxp/pinctrl-imx.c | 2 +- drivers/pinctrl/nxp/pinctrl-imx6.c | 5 + drivers/power/pmic/Kconfig | 8 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/rn5t567.c | 64 +++++++ drivers/serial/serial_mxc.c | 32 +++- drivers/watchdog/imx_watchdog.c | 2 +- include/configs/bk4r1.h | 33 ++++ include/configs/colibri_imx7.h | 2 - include/configs/ge_bx50v3.h | 7 +- include/configs/mx6ullevk.h | 180 ++++++++++++++++++ include/configs/pcm052.h | 78 +++++--- include/configs/tbs2910.h | 4 +- include/configs/wandboard.h | 26 --- include/dt-bindings/clock/imx6ul-clock.h | 253 +++++++++++++++++++++++++ include/fsl_wdog.h | 1 + include/image.h | 1 + include/power/rn5t567_pmic.h | 113 ++++++++++++ tools/Makefile | 1 + tools/vybridimage.c | 164 +++++++++++++++++ 70 files changed, 7233 insertions(+), 389 deletions(-) create mode 100644 arch/arm/dts/bk4r1.dts create mode 100644 arch/arm/dts/imx6ul-pinfunc.h create mode 100644 arch/arm/dts/imx6ull-14x14-evk.dts create mode 100644 arch/arm/dts/imx6ull-pinfunc-snvs.h create mode 100644 arch/arm/dts/imx6ull-pinfunc.h create mode 100644 arch/arm/dts/imx6ull.dtsi create mode 100644 arch/arm/dts/imx7-colibri.dts create mode 100644 arch/arm/dts/imx7.dtsi create mode 100644 arch/arm/dts/imx7d-pinfunc.h create mode 100644 arch/arm/include/asm/arch-mx6/mx6ull_pins.h create mode 100644 board/freescale/mx6ullevk/Kconfig create mode 100644 board/freescale/mx6ullevk/MAINTAINERS create mode 100644 board/freescale/mx6ullevk/Makefile create mode 100644 board/freescale/mx6ullevk/imximage.cfg create mode 100644 board/freescale/mx6ullevk/mx6ullevk.c create mode 100644 board/udoo/README create mode 100644 configs/bk4r1_defconfig create mode 100644 configs/mx6ull_14x14_evk_defconfig create mode 100644 doc/device-tree-bindings/pmic/rn5t567.txt create mode 100644 doc/device-tree-bindings/serial/mxc-serial.txt create mode 100644 drivers/power/pmic/rn5t567.c create mode 100644 include/configs/bk4r1.h create mode 100644 include/configs/mx6ullevk.h create mode 100644 include/dt-bindings/clock/imx6ul-clock.h create mode 100644 include/power/rn5t567_pmic.h create mode 100644 tools/vybridimage.c -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[U-Boot] [PATCH v3 0/3] ARM: TI: Enable DISPLAY_{CPU/BOARD}INFO
by Lokesh Vutla 08 Oct '16

08 Oct '16

This series adds ID code detection support for AM437x and enables CONFIG_DISPLAY_{CPU/BOARD}INFO on all TI platforms. This series is based on top of Andrew's (Kconfig: Separate AM33XX SOC config from target board config) patch[1] I specifically did not use tools/moveconfig.py as Tom suggested to select these configs from targets instead of enabling it in defconfigs. Changes since v2: - Rebased on top of latest master: "53fec16 - Prepare v2016.11-rc1" Lokesh Vutla (3): ARM: AM437X: Add Silicon ID support ARM: TI: Enable DISPLAY_CPUINFO on all SoCs ARM: TI: Enable DISPLAY_BOARDINFO on all boards arch/arm/Kconfig | 6 ++++++ arch/arm/cpu/armv7/am33xx/Kconfig | 11 +++++++++++ arch/arm/cpu/armv7/am33xx/sys_info.c | 5 ++++- arch/arm/cpu/armv7/omap3/Kconfig | 8 ++++++++ arch/arm/cpu/armv7/omap5/Kconfig | 4 ++++ arch/arm/include/asm/arch-am33xx/cpu.h | 3 ++- arch/arm/mach-keystone/Kconfig | 4 ++++ arch/powerpc/cpu/ppc4xx/Kconfig | 14 ++++++++++++++ board/amcc/acadia/Kconfig | 4 ---- board/amcc/bamboo/Kconfig | 4 ---- board/amcc/bubinga/Kconfig | 4 ---- board/amcc/canyonlands/Kconfig | 4 ---- board/amcc/katmai/Kconfig | 4 ---- board/amcc/kilauea/Kconfig | 4 ---- board/amcc/luan/Kconfig | 4 ---- board/amcc/makalu/Kconfig | 4 ---- board/amcc/redwood/Kconfig | 4 ---- board/amcc/sequoia/Kconfig | 4 ---- board/amcc/walnut/Kconfig | 4 ---- board/amcc/yosemite/Kconfig | 4 ---- board/amcc/yucca/Kconfig | 4 ---- board/liebherr/lwmon5/Kconfig | 4 ---- common/Kconfig | 16 ++++++++++++++++ include/configs/ti_armv7_keystone2.h | 1 - include/configs/ti_omap4_common.h | 2 -- include/configs/ti_omap5_common.h | 3 --- 26 files changed, 69 insertions(+), 64 deletions(-) -- 2.9.3

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[U-Boot] [PATCH v1] spl: saveenv: adding saveenv support in SPL
by Ravi Babu 08 Oct '16

08 Oct '16

By default saveenv option is not supported for SPL. This patch enable the support for save environment variable for SPL build. Enable save environment support in SPL after setenv. By default the saveenv option is not provided in SPL, but some boards need this support in 'Falcon' boot, where SPL need to boot from different images based on environment variable set by OS. For example OS may set "reboot_image" environment variable to "recovery" inorder to boot recovery image by SPL. The SPL read "reboot_image" and act accordingly and change the reboot_image to default mode using setenv and save the environemnt. Signed-off-by: Ravi Babu <ravibabu(a)ti.com> Reviewed-by: Simon Glass <sig(a)chromium.org> change in v1: - dropped SUPPORT, use CONFIG_SPL_SAVEENV - updates the comments in mmc_private.h --- common/spl/Kconfig | 13 +++++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/mmc_private.h | 7 +++---- lib/Makefile | 1 + lib/hashtable.c | 2 +- 5 files changed, 19 insertions(+), 5 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2a8ddbc..605cf66 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -163,6 +163,19 @@ config SPL_ENV_SUPPORT starting U-Boot first. Enabling this option will make getenv() and setenv() available in SPL. +config SPL_SAVEENV + bool "Support save environment" + depends on SPL && SPL_ENV_SUPPORT + help + Enable save environment support in SPL after setenv. By default + the saveenv option is not provided in SPL, but some boards need + this support in 'Falcon' boot, where SPL need to boot from + different images based on environment variable set by OS. For + example OS may set "reboot_image" environment variable to + "recovery" inorder to boot recovery image by SPL. The SPL read + "reboot_image" and act accordingly and change the reboot_image + to default mode using setenv and save the environemnt. + config SPL_ETH_SUPPORT bool "Support Ethernet" depends on SPL_ENV_SUPPORT diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 18351fb..d850758 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o +obj-$(CONFIG_SPL_SAVEENV) += mmc_write.o else obj-$(CONFIG_GENERIC_MMC) += mmc_write.o endif diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index 49ec022..d8b399e 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h @@ -28,8 +28,7 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, void *dst); #endif -#ifndef CONFIG_SPL_BUILD - +#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV)) unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt); @@ -41,9 +40,9 @@ ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, const void *src); #endif -#else /* CONFIG_SPL_BUILD */ +#else /* CONFIG_SPL_BUILD and CONFIG_SPL_SAVEENV is not defined */ -/* SPL will never write or erase, declare dummies to reduce code size. */ +/* declare dummies to reduce code size. */ #ifdef CONFIG_BLK static inline unsigned long mmc_berase(struct udevice *dev, diff --git a/lib/Makefile b/lib/Makefile index c81bfeb..e3383f4 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_$(SPL_)RSA) += rsa/ obj-$(CONFIG_$(SPL_)SHA1) += sha1.o obj-$(CONFIG_$(SPL_)SHA256) += sha256.o +obj-$(CONFIG_SPL_SAVEENV) += qsort.o obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/ ifneq ($(CONFIG_SPL_BUILD)$(CONFIG_SPL_OF_PLATDATA),yy) obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o diff --git a/lib/hashtable.c b/lib/hashtable.c index 4e52b36..07c437c 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -477,11 +477,11 @@ int hdelete_r(const char *key, struct hsearch_data *htab, int flag) return 1; } +#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV)) /* * hexport() */ -#ifndef CONFIG_SPL_BUILD /* * Export the data stored in the hash table in linearized form. * -- 1.9.1

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