October 2016 - U-Boot

[U-Boot] [PATCH] Various, accumulated typos collected from around the tree.
by Robert P. J. Day 08 Oct '16

08 Oct '16

Fix various misspellings of: * deprecated * partition * preceding,preceded * preparation * its versus it's * export * existing * scenario * redundant * remaining * value * architecture Signed-off-by: Robert P. J. Day <rpjday(a)crashcourse.ca> --- just rebased against master so it should apply, tried to CC various relevant people depending on location of typos. diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 1864ab9..6b46078 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -45,7 +45,7 @@ static inline void *phys_to_virt(unsigned long x) /* * Virtual <-> DMA view memory address translations * Again, these are *only* valid on the kernel direct mapped RAM - * memory. Use of these is *depreciated*. + * memory. Use of these is *deprecated*. */ #define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) #define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) @@ -127,7 +127,7 @@ static inline void *phys_to_virt(unsigned long x) #endif /* - * We should really eliminate virt_to_bus() here - it's depreciated. + * We should really eliminate virt_to_bus() here - it's deprecated. */ #define page_to_bus(page) (virt_to_bus(page_address(page))) diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 78a7fac..3a4e902 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -132,7 +132,7 @@ struct tag_ramdisk { /* describes where the compressed ramdisk image lives (virtual address) */ /* * this one accidentally used virtual addresses - as such, - * its depreciated. + * it's deprecated. */ #define ATAG_INITRD 0x54410005 diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index ef08489..cabf64c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -489,7 +489,7 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR); - puts("SPD data of all dimms (zero vaule is omitted)...\n"); + puts("SPD data of all dimms (zero value is omitted)...\n"); puts("Byte (hex) "); k = 1; for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { @@ -543,7 +543,7 @@ static void dump_spd_ddr_reg(void) } } printf("DDR registers dump for all controllers " - "(zero vaule is omitted)...\n"); + "(zero value is omitted)...\n"); puts("Offset (hex) "); for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index 48d207f..4a3d094 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -140,7 +140,7 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_SPL_OS_BOOT /* - * Do board specific preperation before SPL + * Do board specific preparation before SPL * Linux boot */ void spl_board_prepare_for_linux(void) diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 965252f..f785dbe 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -157,7 +157,7 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_SPL_OS_BOOT /* - * Do board specific preperation before SPL + * Do board specific preparation before SPL * Linux boot */ void spl_board_prepare_for_linux(void) diff --git a/cmd/nvedit.c b/cmd/nvedit.c index b67563b..9ca5cb5 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -15,7 +15,7 @@ * * The "environment" is stored on external storage as a list of '\0' * terminated "name=value" strings. The end of the list is marked by - * a double '\0'. The environment is preceeded by a 32 bit CRC over + * a double '\0'. The environment is preceded by a 32 bit CRC over * the data part and, in case of redundant environment, a byte of * flags. * @@ -838,7 +838,7 @@ static int do_env_delete(cmd_tbl_t *cmdtp, int flag, * With "-c" and size is NOT given, then the export command will * format the data as currently used for the persistent storage, * i. e. it will use CONFIG_ENV_SECT_SIZE as output block size and - * prepend a valid CRC32 checksum and, in case of resundant + * prepend a valid CRC32 checksum and, in case of redundant * environment, a "current" redundancy flag. If size is given, this * value will be used instead of CONFIG_ENV_SECT_SIZE; again, CRC32 * checksum and redundancy flag will be inserted. @@ -847,12 +847,12 @@ static int do_env_delete(cmd_tbl_t *cmdtp, int flag, * terminating '\0' byte) will be written; here the optional size * argument will be used to make sure not to overflow the user * provided buffer; the command will abort if the size is not - * sufficient. Any remainign space will be '\0' padded. + * sufficient. Any remaining space will be '\0' padded. * * On successful return, the variable "filesize" will be set. * Note that filesize includes the trailing/terminating '\0' byte(s). * - * Usage szenario: create a text snapshot/backup of the current settings: + * Usage scenario: create a text snapshot/backup of the current settings: * * => env export -t 100000 * => era ${backup_addr} +${filesize} @@ -970,7 +970,7 @@ sep_err: /* * env import [-d] [-t [-r] | -b | -c] addr [size] * -d: delete existing environment before importing; - * otherwise overwrite / append to existion definitions + * otherwise overwrite / append to existing definitions * -t: assume text format; either "size" must be given or the * text data must be '\0' terminated * -r: handle CRLF like LF, that means exported variables with diff --git a/common/board_f.c b/common/board_f.c index da381db..a93a4ba 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -1052,7 +1052,7 @@ void board_init_f(ulong boot_flags) { #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA /* - * For some archtectures, global data is initialized and used before + * For some architectures, global data is initialized and used before * calling this function. The data should be preserved. For others, * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack * here to host global data until relocation. @@ -1064,7 +1064,7 @@ void board_init_f(ulong boot_flags) /* * Clear global data before it is accessed at debug print * in initcall_run_list. Otherwise the debug print probably - * get the wrong vaule of gd->have_console. + * get the wrong value of gd->have_console. */ zero_global_data(); #endif diff --git a/common/env_common.c b/common/env_common.c index 560cad0..7fb62e8 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -226,7 +226,7 @@ int env_import(const char *buf, int check) return 0; } -/* Emport the environment and generate CRC for it. */ +/* Export the environment and generate CRC for it. */ int env_export(env_t *env_out) { char *res; diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index 5752fee..ba18135 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -41,7 +41,7 @@ * to the 256 byte-"opcodes" found on the 8086. The table which * dispatches this is found in the files optab.[ch]. * -* Each opcode proc has a comment preceeding it which gives it's table +* Each opcode proc has a comment preceding it which gives it's table * address. Several opcodes are missing (undefined) in the table. * * Each proc includes information for decoding (DECODE_PRINTF and diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index fd0c4f7..6125bbb 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -41,7 +41,7 @@ uint32_t secmem_set_cmd(uint32_t sec_mem_cmd) /*! * CAAM page allocation: * Allocates a partition from secure memory, with the id - * equal to partion_num. This will de-allocate the page + * equal to partition_num. This will de-allocate the page * if it is already allocated. The partition will have * full access permissions. The permissions are set before, * running a job descriptor. A memory page of secure RAM diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 80ef050..7e0749f 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -1302,7 +1302,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, } if (mem_mask != 0) { - /* motib redundent in KW28 */ + /* motib redundant in KW28 */ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, CS_ENABLE_REG, 0, 0x8)); diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index b718481..ca11396 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -899,7 +899,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) * current transfer) have got the time to arrived before * netloop calls eth_halt */ - printf ("About preceeding transfer (eth%d):\n" + printf ("About preceding transfer (eth%d):\n" "- Sent packet number %d\n" "- Received packet number %d\n" "- Handled packet number %d\n", diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index c8dcb27..f213587 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -594,7 +594,7 @@ static int fsl_dspi_claim_bus(struct udevice *dev) priv = dev_get_priv(bus); - /* processor special prepartion work */ + /* processor special preparation work */ cpu_dspi_claim_bus(bus->seq, slave_plat->cs); /* configure transfer mode */ diff --git a/include/environment.h b/include/environment.h index 1fdbdad..b602e8a 100644 --- a/include/environment.h +++ b/include/environment.h @@ -16,10 +16,9 @@ * shifts the remaining entries to the front. Replacing an entry is a * combination of deleting the old value and adding the new one. * - * The environment is preceeded by a 32 bit CRC over the data part. + * The environment is preceded by a 32 bit CRC over the data part. * - ************************************************************************** - */ + *************************************************************************/ #if defined(CONFIG_ENV_IS_IN_FLASH) # ifndef CONFIG_ENV_ADDR diff --git a/include/s_record.h b/include/s_record.h index 6db7174..81245ba 100644 --- a/include/s_record.h +++ b/include/s_record.h @@ -29,7 +29,7 @@ * 2 data record with 24-bit address * 3 data record with 32-bit address * 4 symbol record (LSI extension) - * 5 number of data records in preceeding block + * 5 number of data records in preceding block * 6 unused * 7 ending record for S3 records * 8 ending record for S2 records diff --git a/lib/hashtable.c b/lib/hashtable.c index 4e52b36..afd2305 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -499,7 +499,7 @@ int hdelete_r(const char *key, struct hsearch_data *htab, int flag) * * If the separator character is different from NUL, then any * separator characters and backslash characters in the values will - * be escaped by a preceeding backslash in output. This is needed for + * be escaped by a preceding backslash in output. This is needed for * example to enable multi-line values, especially when the output * shall later be parsed (for example, for re-import). * diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 24831b3..84f5756 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -4263,7 +4263,7 @@ sub process { } } -# check for case / default statements not preceeded by break/fallthrough/switch +# check for case / default statements not preceded by break/fallthrough/switch if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) { my $has_break = 0; my $has_statement = 0; @@ -4284,7 +4284,7 @@ sub process { } if (!$has_break && $has_statement) { WARN("MISSING_BREAK", - "Possible switch case/default not preceeded by break or fallthrough comment\n" . $herecurr); + "Possible switch case/default not preceded by break or fallthrough comment\n" . $herecurr); } } diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index 8d3fef4..b907827 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -405,7 +405,7 @@ static int display_fdt_by_regions(struct display_info *disp, const void *blob, * The output of this function may or may not be a valid FDT. To ensure it * is, these disp->flags must be set: * - * FDT_REG_SUPERNODES: ensures that subnodes are preceeded by their + * FDT_REG_SUPERNODES: ensures that subnodes are preceded by their * parents. Without this option, fragments of subnode data may be * output without the supernodes above them. This is useful for * hashing but cannot produce a valid FDT. -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH] ARMv8/sec-firmware: fix a compile error
by Zhiqiang Hou 08 Oct '16

08 Oct '16

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> When enabled sec firmware framework, but lack of definition of the marco SEC_FIRMWARE_FIT_IMAGE, SEC_FIRMEWARE_FIT_CNF_NAME and SEC_FIRMWARE_TARGET_EL, there will be some build errors, so give a default definition. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- arch/arm/cpu/armv8/sec_firmware.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index e21e199..2ddd67e 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -19,12 +19,22 @@ extern void c_runtime_cpu_setup(void); #define SEC_FIRMWARE_LOADED 0x1 #define SEC_FIRMWARE_RUNNING 0x2 #define SEC_FIRMWARE_ADDR_MASK (~0x3) - /* - * Secure firmware load addr - * Flags used: 0x1 secure firmware has been loaded to secure memory - * 0x2 secure firmware is running - */ - phys_addr_t sec_firmware_addr; +/* + * Secure firmware load addr + * Flags used: 0x1 secure firmware has been loaded to secure memory + * 0x2 secure firmware is running + */ +phys_addr_t sec_firmware_addr; + +#ifndef SEC_FIRMWARE_FIT_IMAGE +#define SEC_FIRMWARE_FIT_IMAGE "firmware" +#endif +#ifndef SEC_FIRMEWARE_FIT_CNF_NAME +#define SEC_FIRMEWARE_FIT_CNF_NAME "config@1" +#endif +#ifndef SEC_FIRMWARE_TARGET_EL +#define SEC_FIRMWARE_TARGET_EL 2 +#endif static int sec_firmware_get_data(const void *sec_firmware_img, const void **data, size_t *size) -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] ARM: Respect CONFIG_SPL_STACK define in lowlevel_init.S
by Siarhei Siamashka 08 Oct '16

08 Oct '16

The SPL and U-Boot proper may use different initial stack locations, which are configured via CONFIG_SPL_STACK and CONFIG_SYS_INIT_SP_ADDR defines. The lowlevel_init.S code needs to handle this in the same way as crt0.S Without this fix, setting the U-Boot stack location to some place, which is not safely accessible by the SPL (such as the DRAM), causes a very early SPL deadlock. Signed-off-by: Siarhei Siamashka <siarhei.siamashka(a)gmail.com> --- arch/arm/cpu/armv7/lowlevel_init.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 1872c57..658934d 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -19,7 +19,11 @@ ENTRY(lowlevel_init) /* * Setup a temporary stack. Global data is not available yet. */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) + ldr sp, =CONFIG_SPL_STACK +#else ldr sp, =CONFIG_SYS_INIT_SP_ADDR +#endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #ifdef CONFIG_SPL_DM mov r9, #0 -- 2.7.3

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[U-Boot] [PATCH 0/6] tools/env: refactor flash read/write function
by Andreas Fenkart 08 Oct '16

08 Oct '16

Take advantage of the environment being block aligned block alignment is enforced since 183923d3e4 Andreas Fenkart (6): tools/env: factor out environment_end function tools/env: pass bad block offset by value tools/env: lookup dev_type directly from flash_read_buf/flash_write_buf tools/env: flash_write_buf: enforce offset to be start of environment tools/env: flash_write_buf: remove block alignment calculations tools/env: flash_read_buf: enforce offset to be start of environment tools/env/fw_env.c | 121 ++++++++++++++++++++--------------------------------- 1 file changed, 45 insertions(+), 76 deletions(-) -- 2.8.1

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[U-Boot] [PATCH] gunzip: cache-align write buffer memory
by Clemens Gruber 08 Oct '16

08 Oct '16

When using gzwrite to eMMC on an i.MX6Q board, the following warning occurs repeatedly: CACHE: Misaligned operation at range [4fd63318, 4fe63318] This patch cache-aligns the memory allocation for the gzwrite writebuf, therefore avoiding the misaligned dcache flush and the warning from check_cache_range. Signed-off-by: Clemens Gruber <clemens.gruber(a)pqgruber.com> --- lib/gunzip.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/gunzip.c b/lib/gunzip.c index bc746d6..832b306 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -11,6 +11,7 @@ #include <console.h> #include <image.h> #include <malloc.h> +#include <memalign.h> #include <u-boot/zlib.h> #include <div64.h> @@ -193,7 +194,7 @@ int gzwrite(unsigned char *src, int len, s.next_in = src + i; s.avail_in = payload_size+8; - writebuf = (unsigned char *)malloc(szwritebuf); + writebuf = (unsigned char *)malloc_cache_aligned(szwritebuf); /* decompress until deflate stream ends or end of file */ do { -- 2.9.3

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Re: [U-Boot] [PATCH] arm: ls102xa: Remove reduplicate definition for Generic Timer frequency
by Alison Wang 08 Oct '16

08 Oct '16

Hi, York, > On 09/23/2016 01:15 AM, Alison Wang wrote: > > GENERIC_TIMER_CLK and CONFIG_TIMER_CLK_FREQ are both used to define > > Generic Timer frequency. It is reduplicate. This patch will remove > > GENERIC_TIMER_CLK macro. > > > > Signed-off-by: Alison Wang <alison.wang(a)nxp.com> > > --- > > arch/arm/cpu/armv7/ls102xa/psci.S | 2 +- > > arch/arm/cpu/armv7/ls102xa/timer.c | 2 +- > > include/configs/ls1021aqds.h | 5 ----- > > include/configs/ls1021atwr.h | 5 ----- > > 4 files changed, 2 insertions(+), 12 deletions(-) > > > > diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S > > b/arch/arm/cpu/armv7/ls102xa/psci.S > > index 8f38680..9efb6d8 100644 > > --- a/arch/arm/cpu/armv7/ls102xa/psci.S > > +++ b/arch/arm/cpu/armv7/ls102xa/psci.S > > @@ -36,7 +36,7 @@ > > > > .align 5 > > > > -#define ONE_MS (GENERIC_TIMER_CLK / 1000) > > +#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000) > > #define RESET_WAIT (30 * ONE_MS) > > > > Alison, > > Can you use GENERIC_TIMER_CLK? Recent change in U-Boot doesn't favor > using CONFIG_* macros. [Alison Wang] If GENERIC_TIMER_CLK is used and CONFIG_TIMER_CLK_FREQ is removed, I need to modify the generic codes which use CONFIG_TIMER_CLK_FREQ in arch/arm/cpu/armv7/nonsec_virt.S. Some other platforms may be affected. So I remove GENERIC_TIMER_CLK in v1. What's your idea? Best Regards, Alison Wang

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[U-Boot] Unable to boot from QSPI (u-boot 2016.11-rc1)
by Teoh Choon Zone 08 Oct '16

08 Oct '16

Hi all, I have a custom board based on Altera Cyclone V SoC, when I tried to boot from QSPI, it stuck in a boot loop, I try to enable some debug message, and here it is: U-Boot SPL 2016.09.01 (Oct 03 2016 - 18:14:42) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete bind node soc - found match at 'generic_simple_bus' bind node dwmmc0@ff704000 - found match at 'socfpga_dwmmc' Bound device dwmmc0@ff704000 to soc bind node spi@ff705000 - found match at 'cadence_spi' bind node n25q00@0 No match for node 'n25q00@0' Bound device spi@ff705000 to soc Bound device soc to root_driver Trying to boot from SPI Bound device spi_flash to spi@ff705000 SF: Got idcodes 00000000x: x x x x x .!.D u-boot from Altera working fine, but I plan to use the mainline u-boot. Any idea why it does not work?

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[U-Boot] [PATCH] arm: psci: save and restore registers from r4 to r12
by Chenhui Zhao 08 Oct '16

08 Oct '16

Save and restore core registers from r4 to r12 so that PSCI code won't break their value. Signed-off-by: Chenhui Zhao <chenhui.zhao(a)nxp.com> Signed-off-by: Alison Wang <alison.wang(a)nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> --- arch/arm/cpu/armv7/psci.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 6a36208..746297c 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -152,7 +152,7 @@ _psci_table: .word 0 _smc_psci: - push {r4-r7,lr} + push {r4-r12,lr} @ Switch to secure mrc p15, 0, r7, c1, c1, 0 @@ -175,7 +175,7 @@ _smc_psci: @ Switch back to non-secure 2: mcr p15, 0, r7, c1, c1, 0 - pop {r4-r7, lr} + pop {r4-r12, lr} movs pc, lr @ Return to the kernel @ Requires dense and single-cluster CPU ID space -- 1.9.1

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Re: [U-Boot] [PATCH v6 0/2] armv8: Support loading 32-bit OS in AArch32 execution state
by Alison Wang 08 Oct '16

08 Oct '16

> -----邮件原件----- > 发件人: york sun [mailto:york.sun@nxp.com] > 发送时间: Thursday, October 06, 2016 3:00 AM > 收件人: Alison Wang <b18965(a)freescale.com>; agraf(a)suse.de; Scott Wood > <scott.wood(a)nxp.com>; Stuart Yoder <stuart.yoder(a)nxp.com>; Leo Li > <leoyang.li(a)nxp.com>; fenghua(a)phytium.com.cn; linus.walleij(a)linaro.org; > ryan.harkin(a)linaro.org; monstr(a)monstr.eu; thomas.ab(a)samsung.com; > mk7.kang(a)samsung.com; u-boot(a)lists.denx.de > 抄送: Jason Jin <jason.jin(a)nxp.com> > 主题: Re: [PATCH v6 0/2] armv8: Support loading 32-bit OS in AArch32 > execution state > > On 09/09/2016 01:56 AM, Alison Wang wrote: > > This series is to support loading a 32-bit OS, the execution state > > will change from > > AArch64 to AArch32 when jumping to kernel. The architecture > > information will be got through checking FIT image, then U-Boot will > load 32-bit OS or 64-bit OS automatically. > > > > Spin-table method is used for secondary cores to load 32-bit OS. The > > architecture information will be got through checking FIT image and > > saved in the os_arch element of spin-table, then the secondary cores > > will check os_arch and jump to 32-bit OS or 64-bit OS automatically. > > > > --------------------------------------- > > Changes in v6: > > - Modified armv8_switch_to_el1(). It will always jump to ep when > switching to AArch64 or AArch32 modes. > > - Make other platforms compatible with the new armv8_switch_to_el2() > and armv8_switch_to_el1(). > > > > Changes in v5: > > - Modified armv8_switch_to_el2(). It will always jump to ep when > switching to AArch64 or AArch32 modes. > > - Make secondary_switch_to_el2() always jump to ep when switching to > AArch64 or AArch32 modes. > > > > Changes in v4: > > - Correct config ARM64_SUPPORT_AARCH32. > > - Omit arch and ftaddr arguments. > > - Rename "xreg5" to "tmp". > > - Use xxx_RES1 to combine all RES1 fields in xxx register. > > - Use an immediate cmp directly. > > - Use #ifdef for CONFIG_ARM64_SUPPORT_AARCH32. > > > > Changes in v3: > > - Comments the functions and the arguments. > > - Rename the real parameters. > > - Use the macros instead of the magic values. > > - Remove the redundant codes. > > - Clean up all of the mess in boot_jump_linux(). > > - Add CONFIG_ARM64_SUPPORT_AARCH32 to detect for some ARM64 system > doesn't support AArch32 state. > > - Adjust the arguments for armv8_switch_to_el2_m and > armv8_switch_to_el1_m. > > > > Changes in v2: > > - armv8_switch_to_el2_aarch32() is removed. armv8_switch_to_el2_m is > used > > to switch to AArch64 EL2 or AArch32 Hyp. > > - armv8_switch_to_el1_aarch32() is removed. armv8_switch_to_el1_m is > used > > to switch to AArch64 EL1 or AArch32 SVC. > > - Support to call armv8_switch_to_el2_m and armv8_switch_to_el1_m. > > > > ---------------------------------------------------------------- > > Alison Wang (2): > > armv8: Support loading 32-bit OS in AArch32 execution state > > armv8: fsl-layerscape: SMP support for loading 32-bit OS > > Alison, > > The change overall is OK, but the way you split the patches is not. If > you apply the first patch and then compile, you will see all our armv8 > platforms are broken. You changed the definition of macro > armv8_switch_to_el2_m in the first patch, but you change the call in > the second patch. [Alison Wang] Sorry for the mistake. I will split the patches correctly in v7. Thanks. Best Regards, Alison Wang

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[U-Boot] [PATCHv2 1/2] armv8/fsl-lsch2: refactor the clock system initialization
by Zhiqiang Hou 08 Oct '16

08 Oct '16

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Up to now, there are 3 kinds of SoC under Layerscape Chassis 2, such as LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of difference, for instance the IP modules have different divisors to get clock from Platform PLL. And the core cluster and platform PLL maybe have different reference clock, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Chissis 2. This patch is to map the sys_info->freq_systembus to the Platform PLL, and handle the different divisor of IP modules separately between different SoCs. And separate cluster and platform PLL reference clock. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- V2: - Generate the patch set base on the latest git://git.denx.de/u-boot-fsl-qoriq.git. - Show Platform clock as Bus frequency. - Add Platform clock and IPs' input clock divisors. arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 71 ++++++++++++++++------ arch/arm/include/asm/arch-fsl-layerscape/config.h | 26 ++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + include/configs/ls1012a_common.h | 6 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- 7 files changed, 87 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 5fbd848..4811f1f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -315,8 +315,9 @@ int print_cpuinfo(void) (type == TY_ITYP_VER_A72 ? "A72" : " "))), strmhz(buf, sysinfo.freq_processor[core])); } + /* Display platform clock as Bus frequency. */ printf("\n Bus: %-4s MHz ", - strmhz(buf, sysinfo.freq_systembus)); + strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV)); printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); #ifdef CONFIG_SYS_DPAA_FMAN printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 8922197..4b6863d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info) uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + unsigned long cluster_clk; sys_info->freq_systembus = sysclk; +#ifndef CONFIG_CLUSTER_CLK_FREQ +#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ +#endif + cluster_clk = CONFIG_CLUSTER_CLK_FREQ; + #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; #else sys_info->freq_ddrbus = sysclk; #endif -#ifdef CONFIG_LS1012A - sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; -#else + /* The freq_systembus is used to record frequency of platform PLL */ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; + +#ifdef CONFIG_LS1012A + sys_info->freq_ddrbus = 2 * sys_info->freq_systembus; +#else sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; @@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info) for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; if (ratio[i] > 4) - freq_c_pll[i] = sysclk * ratio[i]; + freq_c_pll[i] = cluster_clk * ratio[i]; else freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } @@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#ifdef CONFIG_LS1012A - sys_info->freq_systembus = sys_info->freq_ddrbus / 2; - sys_info->freq_ddrbus *= 2; -#endif - #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 #ifdef CONFIG_SYS_DPAA_FMAN @@ -148,7 +149,8 @@ void get_sys_info(struct sys_info *sys_info) break; } #else - sys_info->freq_sdhc = sys_info->freq_systembus; + sys_info->freq_sdhc = sys_info->freq_systembus / + CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif #endif @@ -156,7 +158,8 @@ void get_sys_info(struct sys_info *sys_info) ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus / + CONFIG_SYS_FSL_PCLK_DIV / ccr; #endif } @@ -166,7 +169,7 @@ int get_clocks(void) get_sys_info(&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; - gd->bus_clk = sys_info.freq_systembus; + gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV; gd->mem_clk = sys_info.freq_ddrbus; #ifdef CONFIG_FSL_ESDHC @@ -179,41 +182,73 @@ int get_clocks(void) return 1; } +/******************************************** + * get_bus_freq + * return platform clock in Hz + *********************************************/ ulong get_bus_freq(ulong dummy) { + if (!gd->bus_clk) + get_clocks(); + return gd->bus_clk; } ulong get_ddr_freq(ulong dummy) { + if (!gd->mem_clk) + get_clocks(); + return gd->mem_clk; } #ifdef CONFIG_FSL_ESDHC int get_sdhc_freq(ulong dummy) { + if (!gd->arch.sdhc_clk) + get_clocks(); + return gd->arch.sdhc_clk; } #endif int get_serial_clock(void) { - return gd->bus_clk; + return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; +} + +int get_i2c_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV; +} + +int get_dspi_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; } +#ifdef CONFIG_FSL_LPUART +int get_uart_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV; +} +#endif + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { case MXC_I2C_CLK: - return get_bus_freq(0); + return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: - return get_bus_freq(0); + return get_dspi_freq(0); +#ifdef CONFIG_FSL_LPUART case MXC_UART_CLK: - return get_bus_freq(0); + return get_uart_freq(0); +#endif default: printf("Unsupported clock\n"); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 81a5e7c..bc0af99 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -183,6 +183,15 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +/* Platform PLL frequency divisor for platform clock */ +#define CONFIG_SYS_FSL_PCLK_DIV 1 +/* Platform clock divisor for IPs' input clock */ +#define CONFIG_SYS_FSL_DUART_CLK_DIV 1 +#define CONFIG_SYS_FSL_I2C_CLK_DIV 1 +#define CONFIG_SYS_FSL_DSPI_CLK_DIV 1 +#define CONFIG_SYS_FSL_LPUART_CLK_DIV 1 +#define CONFIG_SYS_FSL_SDHC_CLK_DIV 1 + #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -211,6 +220,14 @@ #define CONFIG_MAX_CPUS 1 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 +/* Platform PLL frequency divisor for platform clock */ +#define CONFIG_SYS_FSL_PCLK_DIV 2 +/* Platform clock divisor for IPs' input clock */ +#define CONFIG_SYS_FSL_DUART_CLK_DIV 2 +#define CONFIG_SYS_FSL_I2C_CLK_DIV 2 +#define CONFIG_SYS_FSL_DSPI_CLK_DIV 2 +#define CONFIG_SYS_FSL_SDHC_CLK_DIV 2 + #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 #elif defined(CONFIG_LS1046A) @@ -224,6 +241,15 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +/* Platform PLL frequency divisor for platform clock */ +#define CONFIG_SYS_FSL_PCLK_DIV 1 +/* Platform clock divisor for IPs' input clock */ +#define CONFIG_SYS_FSL_DUART_CLK_DIV 2 +#define CONFIG_SYS_FSL_I2C_CLK_DIV 2 +#define CONFIG_SYS_FSL_DSPI_CLK_DIV 2 +#define CONFIG_SYS_FSL_LPUART_CLK_DIV 2 +#define CONFIG_SYS_FSL_SDHC_CLK_DIV 2 + #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_SFP_VER_3_2 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 95a4293..ee10765 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -136,6 +136,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; + /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus; diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index fba2fac..928fd76 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -24,8 +24,8 @@ #define CONFIG_SYS_TEXT_BASE 0x40100000 #define CONFIG_SYS_FSL_CLK -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 125000000 +#define CONFIG_SYS_CLK_FREQ 125000000 +#define CONFIG_CLUSTER_CLK_FREQ 100000000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 @@ -86,7 +86,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e55fcb2..3b55699 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -50,7 +50,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 5856de8..a538742 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -46,7 +46,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -- 2.1.0.27.g96db324

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