October 2016 - U-Boot

[U-Boot] [PATCH] ARM: tegra: reduce DRAM size mapped into MMU on ARM64
by Stephen Warren 10 Oct '16

10 Oct '16

From: Stephen Warren <swarren(a)nvidia.com> ARM CPUs can architecturally (speculatively) prefetch completely arbitrary normal memory locations, as defined by the current translation tables. The current MMU configuration for 64-bit Tegras maps an extremely large range of addresses as DRAM, well beyond the actual physical maximum DRAM window, even though U-Boot only needs access to the first 2GB of DRAM; the Tegra port of U-Boot deliberately limits itself to 2GB of RAM since some HW modules on at least some 64-bit Tegra SoCs can only access a 32-bit physical address space. This change reduces the amount of RAM mapped via the MMU to disallow the CPU from ever speculatively accessing RAM that U-Boot will definitely not access. This avoids the possibility of the HW raising SError due to accesses to always-invalid physical addresses. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/mach-tegra/arm64-mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index 7b1d258ed84f..a79a5192e076 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -23,7 +23,7 @@ static struct mm_region tegra_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0xff80000000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { -- 2.10.1

1 0

[U-Boot] AHCI controller not found
by Ding, ChiX 10 Oct '16

10 Oct '16

Hi there I'm testing U-boot as Coreboot payload on Intel board. It boots into U-boot shell but fails to detect AHCI controller. SCSI: Error: SCSI Controller(s) 8086:19B2 8086:19C2 not found AHCI SCSI devices are defined in coreboot.h, #define CONFIG_SCSI_AHCI #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ 0x19b2}, \ {PCI_VENDOR_ID_INTEL, \ 0x19c2} I debug into scsi_init(void). It goes through a loop to try to find PCI device for the AHCI controllers defined above in coreboot.h . I tried the new code "enable driver mode for PCI" and the old code using pci_find_device() function, but both fail to find the devices. #ifdef CONFIG_DM_PCI struct udevice *dev; int ret; ret = dm_pci_find_device(scsi_device_list[i].vendor, scsi_device_list[i].device, 0, &dev); if (!ret) { busdevfunc = dm_pci_get_bdf(dev); break; } #else busdevfunc = pci_find_device(scsi_device_list[i].vendor, scsi_device_list[i].device, 0); #endif My device tree file below is a barebone which only defines serial port, keyboard, timer. They work fine. I wonder that in order to find AHCI controller, shall I add some definition for PCI device into the device tree file? What's the minimum definition shall I add? /include/ "skeleton.dtsi" /include/ "keyboard.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" / { #address-cells = <1>; #size-cells = <1>; model = "Google Alex"; compatible = "google,alex", "intel,atom-pineview"; config { silent_console = <0>; }; gpio: gpio {}; serial { reg = <0x1000 8>; clock-frequency = <115200>; }; tsc-timer { clock-frequency = <1000000000>; }; chosen { stdout-path = "/serial"; }; memory { device_type = "memory"; reg = <0 0>; }; }; Thanks a lot, Chi -------------------------------------------------------------- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.

1 0

[U-Boot] [PATCH 0/6] Add support for the BK4R1 variant of PCM052
by Albert ARIBAUD (3ADEV) 10 Oct '16

10 Oct '16

BK4R1 is basically PCM052 with the following differences or quirks: 1) it has 512MB of DDR using MT41K256M16HA_125IT, while the PCM052 has 256MB using MT41J128M16HA_15EIT; 2) it has 1GB of NAND. The size increase is supported by the env directly; 3) its Ethernet ports are physicaly tied together until GPIO 122 is raised. As this is a safety feature U-Boot does not untie the ports except if it needs networking, for instance when doing NAND updates via TFTP; 4) it has a USB hub which may remain in reset if GPIO 130 is not raised. This is done unconditionally at boot; 5) It has two NOR SPI flash chips on QSPI. This series has been run through checkpatch and has no errors or warning except the following one: warning: arch/arm/Kconfig,681: please write a paragraph that describes the config symbol fully Which I believe does not apply, as target configs in this file never have descriptions. Albert ARIBAUD (3ADEV) (6): pcm052: fix MTD partitioning pcm052: remove target-specific dtb name from env pcm052: add 'm4go' command tools: mkimage: add support for Vybrid image format pcm052: allow specifying onboard DDR size in configs pcm052: add new BK4r1 target based on PCM052 SoM Makefile | 6 ++ arch/arm/Kconfig | 4 + arch/arm/config.mk | 3 + arch/arm/cpu/armv7/vf610/Makefile | 5 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/bk4r1.dts | 48 +++++++++ arch/arm/dts/vf.dtsi | 4 +- board/phytec/pcm052/Kconfig | 24 +++++ board/phytec/pcm052/pcm052.c | 206 ++++++++++++++++++++++++++++---------- common/image.c | 1 + configs/bk4r1_defconfig | 32 ++++++ include/configs/bk4r1.h | 33 ++++++ include/configs/pcm052.h | 78 ++++++++++----- include/image.h | 1 + tools/Makefile | 1 + tools/vybridimage.c | 164 ++++++++++++++++++++++++++++++ 16 files changed, 535 insertions(+), 78 deletions(-) create mode 100644 arch/arm/dts/bk4r1.dts create mode 100644 configs/bk4r1_defconfig create mode 100644 include/configs/bk4r1.h create mode 100644 tools/vybridimage.c -- 2.9.3

3 10

[U-Boot] [PATCH v2] board: ge: bx50v3: Pass video bootargs for b850v3
by Akshay Bhat 10 Oct '16

10 Oct '16

From: Ken Lin <ken.lin(a)advantech.com.tw> Due to clock source restrictions on i.MX6, certain pixel clock rates can not be supported. Hence default the resolution/frame rate during boot to a supported value by passing video bootargs 1024x768@60 for HDMI (Display Port1) and LVDS (Display Port2) on B850v3. Signed-off-by: Ken Lin <ken.lin(a)advantech.com.tw> Signed-off-by: Akshay Bhat <akshay.bhat(a)timesys.com> --- v1 -> v2: Rename CONFIG_BOOTARGS_EXTRA to BX50V3_BOOTARGS_EXTRA since CONFIG_* is reserved for defines added via Kconfig include/configs/ge_bx50v3.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 52f096e..c77fef6 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -15,6 +15,7 @@ #include <asm/arch/imx-regs.h> #include <asm/imx-common/gpio.h> +#define BX50V3_BOOTARGS_EXTRA #if defined(CONFIG_TARGET_GE_B450V3) #define CONFIG_BOARD_NAME "General Electric B450v3" #define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b450v3.dtb" @@ -24,6 +25,9 @@ #elif defined(CONFIG_TARGET_GE_B850V3) #define CONFIG_BOARD_NAME "General Electric B850v3" #define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b850v3.dtb" +#undef BX50V3_BOOTARGS_EXTRA +#define BX50V3_BOOTARGS_EXTRA "video=DP-1:1024x768@60 " \ + "video=HDMI-A-1:1024x768@60 " #else #define CONFIG_BOARD_NAME "General Electric BA16 Generic" #define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-ba16.dtb" @@ -166,7 +170,8 @@ "echo 'U-Boot upgraded. Please reset'; " \ "fi\0" \ "setargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${rootdev} rw rootwait cma=128M\0" \ + "root=/dev/${rootdev} rw rootwait cma=128M " \ + BX50V3_BOOTARGS_EXTRA "\0" \ "loadbootscript=" \ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \ -- 2.8.1

2 1

[U-Boot] [PATCH] sunxi: Fix H3 DRAM impedance calibration on rev. A chips
by Jens Kuske 10 Oct '16

10 Oct '16

H3 seems to have a silicon bug breaking the impedance calibration. This is currently worked around in software by multiple steps combining the results to replace the wrong values. Revision A chips need a different workaround, which is present in the vendor bootloader too, but got overlooked in lack of information and affected boards till now. This commit adds a simplified version without correction factor, which would be 1.00 for all known boards anyway. Signed-off-by: Jens Kuske <jenskuske(a)gmail.com> --- Hi, This has been tested by an Armbian user: http://forum.armbian.com/index.php/topic/872-beelink-x2-with-armbian-possib… It looks like only few boards have revision A chips, probably only non-development boards, otherwise we would have found this earlier. The idea that these are different chip revision is based on: https://github.com/igorpecovnik/linux/blob/sun8i/arch/arm/mach-sunxi/sunxi-… Regards, Jens --- arch/arm/mach-sunxi/dram_sun8i_h3.c | 64 +++++++++++++++++++++++++------------ 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c index 2020d75..b08b8e6 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c @@ -217,35 +217,57 @@ static void mctl_zq_calibration(struct dram_para *para) struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - int i; - u16 zq_val[6]; - u8 val; + if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 && + (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) { + u32 reg_val; - writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); - - for (i = 0; i < 6; i++) { - u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; - - writel((zq << 20) | (zq << 16) | (zq << 12) | - (zq << 8) | (zq << 4) | (zq << 0), - &mctl_ctl->zqcr); + clrsetbits_le32(&mctl_ctl->zqcr, 0xffff, + CONFIG_DRAM_ZQ & 0xffff); writel(PIR_CLRSR, &mctl_ctl->pir); mctl_phy_init(PIR_ZCAL); - zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; - writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); + reg_val = readl(&mctl_ctl->zqdr[0]); + reg_val &= (0x1f << 16) | (0x1f << 0); + reg_val |= reg_val << 8; + writel(reg_val, &mctl_ctl->zqdr[0]); - writel(PIR_CLRSR, &mctl_ctl->pir); - mctl_phy_init(PIR_ZCAL); + reg_val = readl(&mctl_ctl->zqdr[1]); + reg_val &= (0x1f << 16) | (0x1f << 0); + reg_val |= reg_val << 8; + writel(reg_val, &mctl_ctl->zqdr[1]); + writel(reg_val, &mctl_ctl->zqdr[2]); + } else { + int i; + u16 zq_val[6]; + u8 val; - val = readl(&mctl_ctl->zqdr[0]) >> 24; - zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; - } + writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); + + for (i = 0; i < 6; i++) { + u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; + + writel((zq << 20) | (zq << 16) | (zq << 12) | + (zq << 8) | (zq << 4) | (zq << 0), + &mctl_ctl->zqcr); - writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); - writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); - writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); + writel(PIR_CLRSR, &mctl_ctl->pir); + mctl_phy_init(PIR_ZCAL); + + zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; + writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); + + writel(PIR_CLRSR, &mctl_ctl->pir); + mctl_phy_init(PIR_ZCAL); + + val = readl(&mctl_ctl->zqdr[0]) >> 24; + zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; + } + + writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); + writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); + writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); + } } static void mctl_set_cr(struct dram_para *para) -- 2.10.0

3 6

[U-Boot] Patch for OLinuXino Lime boards: default DRAM settings
by Josh Marshall 10 Oct '16

10 Oct '16

We have a number of OlinuXino Lime2 boards (both NAND and eMMC versions) which were experiencing sporadic hangs. After testing with some heavy benchmarking and help from the Armbian forum, it was pinned down as the DRAM settings for the board. The default is 480MHz, but this is unstable, and even the build instructions from the vendor Olimex themselves say to set the DRAM clock to 384. (See line 96 at: https://github.com/OLIMEX/OLINUXINO/blob/master/SOFTWARE/A20/A20-build-3.4.… ) I’ve attached a patch against master to change this default: diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index 54343de..21c792a 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=480 +CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_USB0_VBUS_PIN="PC17" CONFIG_USB0_VBUS_DET="PH5" diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index c4f6e1a..024dc2d 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=480 +CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

2 1

[U-Boot] [PATCH] ARM: sun7i: dts: add support for Sinovoip/Bananapi BPI-R1
by Stephen Arnold 10 Oct '16

10 Oct '16

From: Steve Arnold <stephen.arnold42(a)gmail.com> * needs different GMAC_TX_DELAY than lamobo-r1 (not compatible) * tested with 4.8_rc6 b53-mdio and kernel dts switch nodes Signed-off-by: Stephen Arnold <stephen.arnold42(a)gmail.com> Cc: Ian Campbell <ijc(a)hellion.org.uk> Cc: Hans De Goede <hdegoede(a)redhat.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun7i-a20-bananapi-r1.dts | 321 +++++++++++++++++++++++++++++++++ configs/Bananapi_R1_defconfig | 19 ++ 3 files changed, 341 insertions(+) create mode 100644 arch/arm/dts/sun7i-a20-bananapi-r1.dts create mode 100644 configs/Bananapi_R1_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 032c5ae..0cbae00 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -216,6 +216,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-ainol-aw1.dtb \ sun7i-a20-bananapi.dtb \ sun7i-a20-bananapi-m1-plus.dtb \ + sun7i-a20-bananapi-r1.dtb \ sun7i-a20-bananapro.dtb \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ diff --git a/arch/arm/dts/sun7i-a20-bananapi-r1.dts b/arch/arm/dts/sun7i-a20-bananapi-r1.dts new file mode 100644 index 0000000..30a827f --- /dev/null +++ b/arch/arm/dts/sun7i-a20-bananapi-r1.dts @@ -0,0 +1,321 @@ +/* + * Copyright 2015 Hans de Goede <hdegoede(a)redhat.com> + * + * Changes copyright 2016 Stephen Arnold <nerdboy(a)gentoo.org> + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Banana Pi BPI-R1"; + compatible = "sinovoip,bpi-r1", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_bpi_r1>; + + green { + label = "bpi-r1:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ + linux,default-trigger = "heartbeat"; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_bpi_r1>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + }; + +}; + +&ahci { + target-supply = <&reg_ahci_5v>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&reg_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <&reg_gmac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +#include "axp209.dtsi" + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_r1>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_vbus_pin_bpi_r1: usb0_vbus_pin@0 { + allwinner,pins = "PB9"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb2_vbus_pin_bpi_r1: usb2_vbus_pin@0 { + allwinner,pins = "PH3"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_cd_pin_bpi_r1: mmc0_cd_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + gmac_power_pin_bpi_r1: gmac_power_pin@0 { + allwinner,pins = "PH23"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + led_pins_bpi_r1: led_pins@0 { + allwinner,pins = "PH24"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&reg_ahci_5v { + status = "okay"; +}; + +&reg_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +&reg_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +&reg_ldo1 { + regulator-name = "vdd-rtc"; +}; + +&reg_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +&reg_usb0_vbus { + pinctrl-0 = <&usb0_vbus_pin_bpi_r1>; + gpio = <&pio 1 9 GPIO_ACTIVE_HIGH>; /* PB9 */ + status = "okay"; +}; + +&reg_usb1_vbus { + status = "okay"; +}; + +&reg_usb2_vbus { + pinctrl-0 = <&usb2_vbus_pin_bpi_r1>; + gpio = <&pio 7 3 GPIO_ACTIVE_HIGH>; /* PH3 */ + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>, + <&spi0_cs0_pins_a>, + <&spi0_cs1_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_b>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <&reg_usb0_vbus>; + usb1_vbus-supply = <&reg_usb1_vbus>; + usb2_vbus-supply = <&reg_usb2_vbus>; + status = "okay"; +}; diff --git a/configs/Bananapi_R1_defconfig b/configs/Bananapi_R1_defconfig new file mode 100644 index 0000000..e5341ee --- /dev/null +++ b/configs/Bananapi_R1_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=432 +CONFIG_GMAC_TX_DELAY=3 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi-r1" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +# CONFIG_RTL8211X_PHY_FORCE_MASTER=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y -- 2.8.1

3 10

[U-Boot] [PATCH v2] mmc: sdhci: Add the programmable clock mode support
by Wenyou Yang 10 Oct '16

10 Oct '16

Add the programmable clock mode for the clock generator. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- Changes in v2: - Rebase on the latest u-boot-mmc. - Fix the typo Muliplier->Multiplier. drivers/mmc/sdhci.c | 50 ++++++++++++++++++++++++++++++++++++++++---------- include/sdhci.h | 2 ++ 2 files changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 504f2d2..b2bf5a0 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -294,7 +294,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) { struct sdhci_host *host = mmc->priv; - unsigned int div, clk, timeout, reg; + unsigned int div, clk = 0, timeout, reg; /* Wait max 20 ms */ timeout = 200; @@ -318,14 +318,36 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) return 0; if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { - /* Version 3.00 divisors must be a multiple of 2. */ - if (mmc->cfg->f_max <= clock) - div = 1; - else { - for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { - if ((mmc->cfg->f_max / div) <= clock) + /* + * Check if the Host Controller supports Programmable Clock + * Mode. + */ + if (host->clk_mul) { + for (div = 1; div <= 1024; div++) { + if ((mmc->cfg->f_max * host->clk_mul / div) + <= clock) break; } + + /* + * Set Programmable Clock Mode in the Clock + * Control register. + */ + clk = SDHCI_PROG_CLOCK_MODE; + div--; + } else { + /* Version 3.00 divisors must be a multiple of 2. */ + if (mmc->cfg->f_max <= clock) { + div = 1; + } else { + for (div = 2; + div < SDHCI_MAX_DIV_SPEC_300; + div += 2) { + if ((mmc->cfg->f_max / div) <= clock) + break; + } + } + div >>= 1; } } else { /* Version 2.00 divisors must be a power of 2. */ @@ -333,13 +355,13 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if ((mmc->cfg->f_max / div) <= clock) break; } + div >>= 1; } - div >>= 1; if (host->set_clock) host->set_clock(host->index, div); - clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; + clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; clk |= SDHCI_CLOCK_INT_EN; @@ -513,7 +535,7 @@ static const struct mmc_ops sdhci_ops = { int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, u32 max_clk, u32 min_clk) { - u32 caps; + u32 caps, caps_1; caps = sdhci_readl(host, SDHCI_CAPABILITIES); @@ -577,6 +599,14 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + /* + * In case of Host Controller v3.00, find out whether clock + * multiplier is supported. + */ + caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); + host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> + SDHCI_CLOCK_MUL_SHIFT; + return 0; } diff --git a/include/sdhci.h b/include/sdhci.h index 6844c73..144570f 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -97,6 +97,7 @@ #define SDHCI_DIV_MASK 0xFF #define SDHCI_DIV_MASK_LEN 8 #define SDHCI_DIV_HI_MASK 0x300 +#define SDHCI_PROG_CLOCK_MODE 0x0020 #define SDHCI_CLOCK_CARD_EN 0x0004 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 @@ -242,6 +243,7 @@ struct sdhci_host { unsigned int quirks; unsigned int host_caps; unsigned int version; + unsigned int clk_mul; /* Clock Multiplier value */ unsigned int clock; struct mmc *mmc; const struct sdhci_ops *ops; -- 2.7.4

3 4

[U-Boot] [PATCH] mmc: rockchip_sdhci: add clock init for mmc
by Kever Yang 10 Oct '16

10 Oct '16

Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver api. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- drivers/mmc/rockchip_sdhci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index c56e1a3..e787343 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -12,6 +12,7 @@ #include <libfdt.h> #include <malloc.h> #include <sdhci.h> +#include <clk.h> /* 400KHz is max freq for card ID etc. Use that as min */ #define EMMC_MIN_FREQ 400000 @@ -33,7 +34,10 @@ static int arasan_sdhci_probe(struct udevice *dev) struct rockchip_sdhc *prv = dev_get_priv(dev); struct sdhci_host *host = &prv->host; int ret; + struct clk clk; + ret = clk_get_by_index(dev, 0, &clk); + clk_set_rate(&clk, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ); host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ, -- 1.9.1

2 2

[U-Boot] [PATCH 1/2] mmc: sdhci: use the host version value in sdhci_setup_cfg
by Jaehoon Chung 10 Oct '16

10 Oct '16

"host->version" isn't a SoC specific value. It doesn't need to get in each SoC drivers. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/atmel_sdhci.c | 1 - drivers/mmc/bcm2835_sdhci.c | 1 - drivers/mmc/kona_sdhci.c | 5 ----- drivers/mmc/msm_sdhci.c | 3 --- drivers/mmc/mv_sdhci.c | 4 ---- drivers/mmc/s5p_sdhci.c | 1 - drivers/mmc/sdhci.c | 6 +++++- drivers/mmc/spear_sdhci.c | 5 ----- drivers/mmc/zynq_sdhci.c | 2 -- 9 files changed, 5 insertions(+), 23 deletions(-) diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index dd6bd33..c197b09 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -29,7 +29,6 @@ int atmel_sdhci_init(void *regbase, u32 id) host->name = "atmel_sdhci"; host->ioaddr = regbase; host->quirks = 0; - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); max_clk = at91_get_periph_generated_clk(id); if (!max_clk) { printf("%s: Failed to get the proper clock\n", __func__); diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index 680b754..c1d8700 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -184,7 +184,6 @@ int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq) host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; host->ops = &bcm2835_ops; - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); add_sdhci(host, emmc_freq, MIN_FREQ); return 0; diff --git a/drivers/mmc/kona_sdhci.c b/drivers/mmc/kona_sdhci.c index 3653d00..0c4f30e 100644 --- a/drivers/mmc/kona_sdhci.c +++ b/drivers/mmc/kona_sdhci.c @@ -127,11 +127,6 @@ int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks) return -EINVAL; } - if (quirks & SDHCI_QUIRK_REG32_RW) - host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; - else - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - add_sdhci(host, max_clk, min_clk); return ret; } diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 8d4399e..90e90bc 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -140,9 +140,6 @@ static int msm_sdc_probe(struct udevice *dev) writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); } - /* Set host controller version */ - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); host->mmc = &plat->mmc; if (ret) diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 82c695f..ca5f872 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -88,9 +88,5 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) sdhci_mvebu_mbus_config((void __iomem *)regbase); } - if (quirks & SDHCI_QUIRK_REG32_RW) - host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; - else - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); return add_sdhci(host, max_clk, min_clk); } diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 3bace21..7827b28 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -71,7 +71,6 @@ static int s5p_sdhci_core_init(struct sdhci_host *host) SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); host->set_control_reg = &s5p_sdhci_set_control_reg; host->set_clock = set_mmc_clk; diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 504f2d2..7fc11c0 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -524,7 +524,11 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, return -EINVAL; } #endif - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + if (host->quirks & SDHCI_QUIRK_REG32_RW) + host->version = + sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; + else + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); cfg->name = host->name; #ifndef CONFIG_DM_MMC_OPS diff --git a/drivers/mmc/spear_sdhci.c b/drivers/mmc/spear_sdhci.c index 6ca96a2..06179cd 100644 --- a/drivers/mmc/spear_sdhci.c +++ b/drivers/mmc/spear_sdhci.c @@ -22,11 +22,6 @@ int spear_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) host->ioaddr = (void *)regbase; host->quirks = quirks; - if (quirks & SDHCI_QUIRK_REG32_RW) - host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; - else - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - add_sdhci(host, max_clk, min_clk); return 0; } diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 3815b94..299d820 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -36,8 +36,6 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; #endif - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, CONFIG_ZYNQ_SDHCI_MIN_FREQ); host->mmc = &plat->mmc; -- 1.9.1

3 5