October 2016 - U-Boot

[U-Boot] [PATCH] mmc: sdhci: assign to clk_mul when host version is upper than SD3.0
by Jaehoon Chung 26 Oct '16

26 Oct '16

To prevent the wrong value check the SD version. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/sdhci.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 10ff57e..766e9ee 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -608,9 +608,11 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, * In case of Host Controller v3.00, find out whether clock * multiplier is supported. */ - caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); - host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> - SDHCI_CLOCK_MUL_SHIFT; + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { + caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); + host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> + SDHCI_CLOCK_MUL_SHIFT; + } return 0; } -- 2.10.1

1 1

[U-Boot] [PATCH] mmc: add the device name in debugging message for supplying vmmc
by Jaehoon Chung 26 Oct '16

26 Oct '16

If vmmc didn't supply, we didn't know which card didn't supply vmmc. And changed from "put" to "debug". Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 320413a..4380c7c 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1595,7 +1595,7 @@ static int mmc_power_init(struct mmc *mmc) ret = device_get_supply_regulator(mmc->dev, "vmmc-supply", &vmmc_supply); if (ret) { - puts("No vmmc supply\n"); + debug("%s: No vmmc supply\n", mmc->dev->name); return 0; } -- 2.10.1

2 2

[U-Boot] [RFC PATCH v2 00/10] pxa3xx_nand updates
by Chris Packham 26 Oct '16

26 Oct '16

I'm looking into the NAND support for the db-88f6820-amc board. There are a number of changes in the pxa3xx_nand driver in Linux that are relevant (not specifically to this boards but to Armada boards in general). Some of these changes are cleanups and some are actual bug fixes. I'd really appreciate some testing on this. This gives me enough so I can mount and read files out of a ubifs volume created by Linux on the DB-88F6820-AMC board but I don't have access to any other Armada boards to test with. Where applicable I'll Cc the author of the equivalent Linux patch. I've had to tweak a few of them to make them fit u-boot (e.g. to handle platform data) but they should still look pretty close to their Linux counterparts. Note this series is dependent on http://lists.denx.de/pipermail/u-boot/2016-October/270967.html Changes in v2: - Add references to Linux commit sha1. - Remove spurious change in 1/10 - Drop irrelevant Cc from 2/10 - 6/10 to 9/10 are new Chris Packham (10): mtd: nand: pxa3xx_nand: Increase initial buffer size mtd: nand: pxa3xx_nand: use nand_to_mtd() mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing() mtd: nand: pxa3xx_nand: fix early spurious interrupt mtd: nand: pxa3xx-nand: fix random command timeouts nand: pxa3xx: Increase READ_ID buffer and make the size static mtd: pxa3xx_nand: Increase the initial chunk size mtd: pxa3xx_nand: Fix initial controller configuration mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan mtd: nand: pxa3xx_nand: add support for partial chunks drivers/mtd/nand/pxa3xx_nand.c | 294 ++++++++++++++++++++++++----------------- 1 file changed, 175 insertions(+), 119 deletions(-) -- 2.10.1

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[U-Boot] [PATCH v2] tpm: tpm_tis_lpc: Add support for AT97SC3204
by George McCollister 25 Oct '16

25 Oct '16

The Atmel AT97SC3204 is also TIS compliant. Modify the tpm_tis_lpc driver to check for the vid/did used by the Atmel AT97SC3204 and report an appropriate description. Signed-off-by: George McCollister <george.mccollister(a)gmail.com> --- Changes in v2: - Reorganized didvid check to make it more consistent with the original code - Return -ENODEV instead of -ENOENT when didvid doesn't match the expected value for the device drivers/tpm/tpm_tis_lpc.c | 37 ++++++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c index b4efbb5..d2b3783 100644 --- a/drivers/tpm/tpm_tis_lpc.c +++ b/drivers/tpm/tpm_tis_lpc.c @@ -21,6 +21,21 @@ #define PREFIX "lpc_tpm: " +enum i2c_chip_type { + SLB9635, + AT97SC3204, +}; + +static const char * const chip_name[] = { + [SLB9635] = "Infineon SLB9635 TT 1.2", + [AT97SC3204] = "Atmel AT97SC3204", +}; + +static const u32 chip_didvid[] = { + [SLB9635] = 0xb15d1, + [AT97SC3204] = 0x32041114, +}; + struct tpm_locality { u32 access; u8 padding0[4]; @@ -146,9 +161,9 @@ static int tis_wait_reg(struct tpm_tis_lpc_priv *priv, u32 *reg, u8 mask, static int tpm_tis_lpc_probe(struct udevice *dev) { struct tpm_tis_lpc_priv *priv = dev_get_priv(dev); - u32 vid, did; fdt_addr_t addr; u32 didvid; + ulong chip_type = dev_get_driver_data(dev); addr = dev_get_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -156,14 +171,15 @@ static int tpm_tis_lpc_probe(struct udevice *dev) priv->regs = map_sysmem(addr, 0); didvid = tpm_read_word(priv, &priv->regs[0].did_vid); - vid = didvid & 0xffff; - did = (didvid >> 16) & 0xffff; - if (vid != 0x15d1 || did != 0xb) { + if (didvid != chip_didvid[chip_type]) { + u32 vid, did; + vid = didvid & 0xffff; + did = (didvid >> 16) & 0xffff; debug("Invalid vendor/device ID %04x/%04x\n", vid, did); - return -ENOSYS; + return -ENODEV; } - debug("Found TPM %s by %s\n", "SLB9635 TT 1.2", "Infineon"); + debug("Found TPM: %s\n", chip_name[chip_type]); return 0; } @@ -421,11 +437,13 @@ static int tpm_tis_lpc_close(struct udevice *dev) static int tpm_tis_get_desc(struct udevice *dev, char *buf, int size) { + ulong chip_type = dev_get_driver_data(dev); + if (size < 50) return -ENOSPC; - return snprintf(buf, size, "1.2 TPM (vendor %s, chip %s)", - "Infineon", "SLB9635 TT 1.2"); + return snprintf(buf, size, "1.2 TPM (%s)", + chip_name[chip_type]); } @@ -438,7 +456,8 @@ static const struct tpm_ops tpm_tis_lpc_ops = { }; static const struct udevice_id tpm_tis_lpc_ids[] = { - { .compatible = "infineon,slb9635lpc" }, + { .compatible = "infineon,slb9635lpc", .data = SLB9635 }, + { .compatible = "atmel,at97sc3204", .data = AT97SC3204 }, { } }; -- 2.9.3

2 2

[U-Boot] [PATCH] sandboxfs: Fix resource leak
by Tom Rini 25 Oct '16

25 Oct '16

Now that we free resources in sandbox_fs_ls Coverity is letting us know that in some cases we might leak. So in case of error we should still let os_dirent_free free anything that was allocated. Fixes: 86167089b71c ("sandbox/fs: Free memory allocated by os_dirent_ls") Reported-by: Coverity (CID: 153450) Cc: Stefan Brüns <stefan.bruens(a)rwth-aachen.de> Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- fs/sandbox/sandboxfs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c index cd10fd6845fb..ca8026133708 100644 --- a/fs/sandbox/sandboxfs.c +++ b/fs/sandbox/sandboxfs.c @@ -88,15 +88,16 @@ int sandbox_fs_ls(const char *dirname) ret = os_dirent_ls(dirname, &head); if (ret) - return ret; + goto out; for (node = head; node; node = node->next) { printf("%s %10lu %s\n", os_dirent_get_typename(node->type), node->size, node->name); } +out: os_dirent_free(head); - return 0; + return ret; } int sandbox_fs_exists(const char *filename) -- 1.9.1

2 2

[U-Boot] [PATCH] cmd/tpm_test: Fix misleading code indentation
by Stefan Brüns 25 Oct '16

25 Oct '16

GCC 6.2 reasonably complains about the current code: ../cmd/tpm_test.c: In function ‘do_tpmtest’: ../cmd/tpm_test.c:540:3: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation] for (i = 0; i < argc; i++) ^~~ ../cmd/tpm_test.c:542:4: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’ printf("\n------\n"); ^~~~~~ Signed-off-by: Stefan Brüns <stefan.bruens(a)rwth-aachen.de> --- cmd/tpm_test.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c index 65332d1..4af4d71 100644 --- a/cmd/tpm_test.c +++ b/cmd/tpm_test.c @@ -534,13 +534,12 @@ static int do_tpmtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) cmd_tbl_t *c; printf("argc = %d, argv = ", argc); - do { - int i = 0; - for (i = 0; i < argc; i++) - printf(" %s", argv[i]); - printf("\n------\n"); - } while (0); + for (int i = 0; i < argc; i++) + printf(" %s", argv[i]); + + printf("\n------\n"); + argc--; argv++; c = find_cmd_tbl(argv[0], cmd_cros_tpm_sub, -- 2.10.1

2 2

[U-Boot] [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to config.h
by Prabhakar Kushwaha 25 Oct '16

25 Oct '16

Migration of IFC_BANK_COUNT from Kconfig to config.h avoids adding SoC name in Kconfig as Dependencies. It will help in having all SoC related defines in config.h - easy to maintain. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- This patch provide base for defining SYS_FSL_IFC_CLK_DIV required for v3 version of below patch-set http://patchwork.ozlabs.org/patch/666844/ http://patchwork.ozlabs.org/patch/666849/ http://patchwork.ozlabs.org/patch/666848/ README | 3 +++ arch/arm/cpu/armv7/ls102xa/Kconfig | 5 ----- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ------- arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 18 +++++++++--------- drivers/misc/fsl_ifc.c | 2 +- drivers/mtd/nand/fsl_ifc_nand.c | 6 +++--- include/fsl_ifc.h | 20 ++++++++++---------- 9 files changed, 31 insertions(+), 35 deletions(-) diff --git a/README b/README index 68d6a49..c83171a 100644 --- a/README +++ b/README @@ -507,6 +507,9 @@ The following options need to be configured: Board config to use DDR4. It can be enabled for SoCs with DDR4 controllers. + SYS_FSL_IFC_BANK_COUNT + Maximum banks of Integrated flash controller + CONFIG_SYS_FSL_IFC_BE Defines the IFC controller register space as Big Endian diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 28bf778..68d03ab 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -81,9 +81,4 @@ config SYS_FSL_DDR4 help Enable Freescale DDR4 controller. -config SYS_FSL_IFC_BANK_COUNT - int "Maximum banks of Integrated flash controller" - depends on ARCH_LS1021A - default 8 - endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 94ec8d5..0587559 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -71,13 +71,6 @@ config NUM_DDR_CONTROLLERS default 3 if ARCH_LS2080A default 1 -config SYS_FSL_IFC_BANK_COUNT - int "Maximum banks of Integrated flash controller" - depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A - default 4 if ARCH_LS1043A - default 4 if ARCH_LS1046A - default 8 if ARCH_LS2080A - config SYS_FSL_HAS_DP_DDR bool diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 4201e0f..28d3974 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -27,6 +27,8 @@ #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) #endif +#define SYS_FSL_IFC_BANK_COUNT 8 + #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ @@ -150,6 +152,7 @@ /* SoC related */ #ifdef CONFIG_LS1043A +#define SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 @@ -187,6 +190,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 #elif defined(CONFIG_ARCH_LS1046A) +#define SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ec65cc0..d65f5bf 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -120,6 +120,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#define SYS_FSL_IFC_BANK_COUNT 8 #else #error SoC not defined #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6d845e8..073a7b5 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -150,7 +150,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -590,7 +590,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 +#define SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -612,7 +612,7 @@ #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 +#define SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -667,7 +667,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM1_CLK 3 #define CONFIG_SYS_FM2_CLK 3 @@ -714,7 +714,7 @@ #define CONFIG_SYS_ULB_CLK 4 #define CONFIG_SYS_ETVPE_CLK 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -786,7 +786,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FSL_ERRATUM_A008044 #define CONFIG_SYS_FMAN_V3 #define CONFIG_FM_PLAT_CLK_DIV 1 @@ -838,7 +838,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 per rcw field value */ @@ -895,7 +895,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) per rcw field value */ #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -924,7 +924,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index a33efdb..c3e59f0 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -13,7 +13,7 @@ void print_ifc_regs(void) int i, j; printf("IFC Controller Registers\n"); - for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) { + for (i = 0; i < SYS_FSL_IFC_BANK_COUNT; i++) { printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", i, get_ifc_cspr(i), i, get_ifc_amask(i), i, get_ifc_csor(i)); diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index bc6bdc9..d3ad210 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -19,11 +19,11 @@ #include <linux/errno.h> #include <fsl_ifc.h> -#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#ifndef SYS_FSL_IFC_BANK_COUNT +#define SYS_FSL_IFC_BANK_COUNT 4 #endif -#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT +#define MAX_BANKS SYS_FSL_IFC_BANK_COUNT #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index a86f216..29c98a1 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -939,21 +939,21 @@ struct fsl_ifc_gpcm { u32 gpcm_stat; }; -#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT -#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) +#ifdef SYS_FSL_IFC_BANK_COUNT +#if (SYS_FSL_IFC_BANK_COUNT <= 8) #define IFC_CSPR_REG_LEN 148 #define IFC_AMASK_REG_LEN 144 #define IFC_CSOR_REG_LEN 144 #define IFC_FTIM_REG_LEN 576 #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT + SYS_FSL_IFC_BANK_COUNT #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT + SYS_FSL_IFC_BANK_COUNT #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT + SYS_FSL_IFC_BANK_COUNT #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT + SYS_FSL_IFC_BANK_COUNT #else #error IFC BANK count not vaild #endif @@ -991,13 +991,13 @@ struct fsl_ifc_ftim { struct fsl_ifc_fcm { u32 ifc_rev; u32 res1[0x2]; - struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + struct fsl_ifc_cspr cspr_cs[SYS_FSL_IFC_BANK_COUNT]; u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; - struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + struct fsl_ifc_amask amask_cs[SYS_FSL_IFC_BANK_COUNT]; u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; - struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + struct fsl_ifc_csor csor_cs[SYS_FSL_IFC_BANK_COUNT]; u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; - struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + struct fsl_ifc_ftim ftim_cs[SYS_FSL_IFC_BANK_COUNT]; u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; u32 rb_stat; u32 rb_map; -- 2.7.4

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[U-Boot] Loading kernel from SD card slow on MinnowBoard Turbot since v2016.09
by Raschen Josef 25 Oct '16

25 Oct '16

Hi, Reading a kernel image from an SD card via the fatload command on the MinnowBoard Turbot seems to be significantly slower since v2016.09 compared to v2016.07: v2016.07 => fatload mmc 1:1 ${loadaddr} bzImage ; zboot ${loadaddr} reading bzImage 5749232 bytes read in 129 ms (42.5 MiB/s) v2016.09 => fatload mmc 1:1 ${loadaddr} bzImage ; zboot ${loadaddr} reading bzImage 5749232 bytes read in 249 ms (22 MiB/s) The same for v2016.11-rc1. I am using U-Boot in bare mode on the board. Any idea what causes this? Thanks, Josef

3 7

Re: [U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores
by york sun 25 Oct '16

25 Oct '16

On 10/24/2016 08:49 AM, york.sun(a)nxp.com wrote: > On 10/24/2016 01:33 AM, Priyanka Jain wrote: >> NXP ARMv8 SoC LS2080A release all secondary cores in one-go. >> But other new SoCs like LS2088A, LS1088A release secondary >> cores one by one to avoid power spike. >> >> Update code to release secondary cores based on SoC SVR >> Add code to release cores one by one for non LS2080A SoCs >> >> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> >> Signed-off-by: Raghav Dogra <raghav.dogra(a)nxp.com> >> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> >> --- >> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- >> arch/arm/cpu/armv8/fsl-layerscape/cpu.h | 1 + >> arch/arm/cpu/armv8/fsl-layerscape/mp.c | 59 >> ++++++++++++++++++++++++++++-- >> 3 files changed, 57 insertions(+), 5 deletions(-) >> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c >> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c >> index ce04e48..15d157c 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c >> @@ -190,7 +190,7 @@ void enable_caches(void) >> } >> #endif >> >> -static inline u32 initiator_type(u32 cluster, int init_id) >> +inline u32 initiator_type(u32 cluster, int init_id) >> { >> struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); >> u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h >> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h >> index 8072f3c..a05f8aa 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h >> @@ -5,4 +5,5 @@ >> */ >> >> int fsl_qoriq_core_to_cluster(unsigned int core); >> +u32 initiator_type(u32 cluster, int init_id); >> u32 cpu_mask(void); >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c >> b/arch/arm/cpu/armv8/fsl-layerscape/mp.c >> index f607c39..5cf080f 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c >> @@ -9,6 +9,8 @@ >> #include <asm/system.h> >> #include <asm/arch/mp.h> >> #include <asm/arch/soc.h> >> +#include "cpu.h" >> +#include <asm/arch-fsl-layerscape/soc.h> >> >> DECLARE_GLOBAL_DATA_PTR; >> >> @@ -22,11 +24,30 @@ phys_addr_t determine_mp_bootpg(void) >> return (phys_addr_t)&secondary_boot_code; >> } >> >> +#ifdef CONFIG_FSL_LSCH3 >> +void wake_secondary_core_n(int cluster, int core, int cluster_cores) >> +{ >> + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); >> + struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); >> + u32 mpidr = 0; >> + >> + mpidr = ((cluster << 8) | core); >> + gur_out32(&gur->scratchrw[6], mpidr); > > What's the definition of each bit for scratchrw[6]? Before this patch, > secondary cores only check if it is zero. > >> + asm volatile("dsb st" : : : "memory"); >> + rst->brrl |= 1 << ((cluster * cluster_cores) + core); >> + asm volatile("dsb st" : : : "memory"); >> + while (gur_in32(&gur->scratchrw[6]) != 0) >> + ; > > Does each secondary core clear this register after it starts to run? > Priyanka, I got hold of the architect for the bootrom. I understand the story behind the release one-by-one now. It would be better if you can add some comments for scratchrw[6] for its expected behaviour. York

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[U-Boot] [PATCH v7 00/21] imx6: Add Engicam i.CoreM6 QDL support
by Jagan Teki 25 Oct '16

25 Oct '16

From: Jagan Teki <jagan(a)amarulasolutions.com> This series supports Engicam i.CoreM6 QDL modules on top of u-boot-imx/master and test on the respective starter kits as well. Tested both MMC and NAND boot. Changes for v7: - Add patch to CONFIG_DEFAULT_FDT_FILE to defconfigs - Rebase on u-boot-imx/master Changes for v6: - Rebase to u-boot-imx/master - Move few SPL configs to defconfigs Changes for v5: - Add NAND support Changes for v4: - Add 'net: Kconfig: Add FEC_MXC entry' patch - Updated ENV configs along with comments - Restructured configs for more readability - Add CONFIG_ENV_OVERWRITE - Rename icorem6qdl_defconfig with icorem6qdl_mmc_defconfig Changes for v3: - Remove "v2 01/17 imx: iomux-v3: Fix build error with snvs base" patch - Remove 'default n' on Kconfig DEFAULT_FDT_FILE patch - Add minimal devicetree support for Engicam i.CoreM6 QDL - Add is_mx6dl() - Add is_mx6solo() - Use is_mx6dq() - Add last commit sha1 and header in pull devicetree files from Linux Changes for v2: - Make static to local iomux structure in board file - Corrected rowaddr in mx6_ddr3_cfg - Used imx_ddr_size - Add FEC support and tested the same - Add DM_GPIO, DM_MMC support - Add pinctrl support - Add devicetree support Jagan Teki (21): serial: Kconfig: Add MXC_UART entry thermal: Kconfig: Add IMX_THERMAL entry config: Move CONFIG_DEFAULT_FDT_FILE to defconfigs arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support net: Kconfig: Add FEC_MXC entry imx6: icorem6: Add ENET support imx: s/docs\/README.imximage/doc\/README.imximage/g arm: dts: Add devicetree for i.MX6DL arm: dts: Add devicetree for i.MX6DQL arm: dts: imx6dl: Add pinctrl defines dt-bindings: clock: imx6qdl: Add clock defines arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/Solo imx6q: icorem6: Enable pinctrl driver engicam: icorem6: Add DM_GPIO, DM_MMC support arm: dts: Add devicetree for i.MX6Q arm: dts: imx6q: Add pinctrl defines arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/Dual mtd: nand: Kconfig: Add NAND_MXS entry imx6: icorem6: Add NAND support imx6: icorem6: Enable MTD device support imx6: icorem6: Add default mtd nand partition table arch/arm/cpu/armv7/mx6/Kconfig | 11 + arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6dl-icore.dts | 59 ++ arch/arm/dts/imx6dl-pinfunc.h | 1091 +++++++++++++++++++++++ arch/arm/dts/imx6dl.dtsi | 133 +++ arch/arm/dts/imx6q-icore.dts | 59 ++ arch/arm/dts/imx6q-pinfunc.h | 1047 ++++++++++++++++++++++ arch/arm/dts/imx6q.dtsi | 300 +++++++ arch/arm/dts/imx6qdl-icore.dtsi | 196 ++++ arch/arm/dts/imx6qdl.dtsi | 1281 +++++++++++++++++++++++++++ arch/arm/include/asm/imx-common/sys_proto.h | 2 + board/barco/titanium/imximage.cfg | 2 +- board/ccv/xpress/imximage.cfg | 2 +- board/denx/m53evk/imximage.cfg | 2 +- board/engicam/icorem6/Kconfig | 12 + board/engicam/icorem6/MAINTAINERS | 6 + board/engicam/icorem6/Makefile | 6 + board/engicam/icorem6/README | 38 + board/engicam/icorem6/icorem6.c | 537 +++++++++++ board/freescale/mx6sabresd/mx6dlsabresd.cfg | 2 +- board/freescale/mx6slevk/imximage.cfg | 2 +- board/freescale/mx6ullevk/imximage.cfg | 2 +- board/freescale/mx7dsabresd/imximage.cfg | 2 +- board/freescale/s32v234evb/s32v234evb.cfg | 2 +- board/freescale/vf610twr/imximage.cfg | 2 +- board/phytec/pcm052/imximage.cfg | 2 +- board/technexion/pico-imx6ul/imximage.cfg | 2 +- board/toradex/colibri_imx7/imximage.cfg | 2 +- board/toradex/colibri_vf/imximage.cfg | 2 +- board/warp/imximage.cfg | 2 +- board/warp7/imximage.cfg | 2 +- common/Kconfig | 5 + configs/dms-ba16-1g_defconfig | 1 + configs/dms-ba16_defconfig | 1 + configs/ge_b450v3_defconfig | 1 + configs/ge_b650v3_defconfig | 1 + configs/ge_b850v3_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 42 + configs/imx6qdl_icore_nand_defconfig | 37 + configs/mx25pdk_defconfig | 1 + configs/mx53ard_defconfig | 1 + configs/pico-imx6ul_defconfig | 1 + configs/tqma6q_mba6_mmc_defconfig | 1 + configs/tqma6q_mba6_spi_defconfig | 1 + configs/tqma6s_mba6_mmc_defconfig | 1 + configs/tqma6s_mba6_spi_defconfig | 1 + configs/tqma6s_wru4_mmc_defconfig | 1 + configs/zc5202_defconfig | 1 + configs/zc5601_defconfig | 1 + drivers/mtd/nand/Kconfig | 7 + drivers/net/Kconfig | 7 + drivers/serial/Kconfig | 7 + drivers/thermal/Kconfig | 13 + include/configs/advantech_dms-ba16.h | 1 - include/configs/ge_bx50v3.h | 4 - include/configs/imx6qdl_icore.h | 167 ++++ include/configs/mx25pdk.h | 2 - include/configs/mx53ard.h | 2 - include/configs/pico-imx6ul.h | 2 - include/configs/tqma6_mba6.h | 6 - include/configs/tqma6_wru4.h | 2 - include/configs/zc5202.h | 2 - include/configs/zc5601.h | 2 - include/dt-bindings/clock/imx6qdl-clock.h | 274 ++++++ 64 files changed, 5370 insertions(+), 39 deletions(-) create mode 100644 arch/arm/dts/imx6dl-icore.dts create mode 100644 arch/arm/dts/imx6dl-pinfunc.h create mode 100644 arch/arm/dts/imx6dl.dtsi create mode 100644 arch/arm/dts/imx6q-icore.dts create mode 100644 arch/arm/dts/imx6q-pinfunc.h create mode 100644 arch/arm/dts/imx6q.dtsi create mode 100644 arch/arm/dts/imx6qdl-icore.dtsi create mode 100644 arch/arm/dts/imx6qdl.dtsi create mode 100644 board/engicam/icorem6/Kconfig create mode 100644 board/engicam/icorem6/MAINTAINERS create mode 100644 board/engicam/icorem6/Makefile create mode 100644 board/engicam/icorem6/README create mode 100644 board/engicam/icorem6/icorem6.c create mode 100644 configs/imx6qdl_icore_mmc_defconfig create mode 100644 configs/imx6qdl_icore_nand_defconfig create mode 100644 include/configs/imx6qdl_icore.h create mode 100644 include/dt-bindings/clock/imx6qdl-clock.h -- 2.7.4

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