October 2016 - U-Boot

[U-Boot] [PATCH] nand: arasan_nfc: Clear ecc on bit while sending read command
by Michal Simek 26 Oct '16

26 Oct '16

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Clear ecc ON bit while sending read command as all types of read command(like reading spare) doesnt need ECC to be enabled. It has been anyway taken care in other places whereever required using arasan_nand_enable_ecc(). Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/mtd/nand/arasan_nfc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c index 86f7526a84e8..a8f795d957ff 100644 --- a/drivers/mtd/nand/arasan_nfc.c +++ b/drivers/mtd/nand/arasan_nfc.c @@ -853,6 +853,8 @@ static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT); } + reg_val &= ~ARASAN_NAND_CMD_ECC_ON_MASK; + reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; addr_cycles = arasan_nand_get_addrcycle(mtd); -- 1.9.1

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[U-Boot] [PATCH 1/2] ARM: zynq: Add support for Zynq 7000S 7007s/7012s/7014s devices
by Michal Simek 26 Oct '16

26 Oct '16

Zynq 7000S (Single A9 core) devices is using different ID code. This patch adds this new codes and assign them. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/xilinx/zynq/board.c | 12 ++++++++++++ include/zynqpl.h | 18 ++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 183f64275349..2c86940957ec 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -19,7 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; static xilinx_desc fpga; /* It can be done differently */ +static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); +static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); @@ -37,9 +40,18 @@ int board_init(void) idcode = zynq_slcr_get_idcode(); switch (idcode) { + case XILINX_ZYNQ_7007S: + fpga = fpga007s; + break; case XILINX_ZYNQ_7010: fpga = fpga010; break; + case XILINX_ZYNQ_7012S: + fpga = fpga012s; + break; + case XILINX_ZYNQ_7014S: + fpga = fpga014s; + break; case XILINX_ZYNQ_7015: fpga = fpga015; break; diff --git a/include/zynqpl.h b/include/zynqpl.h index 1d37a51a04ef..5a34a17daefe 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -19,7 +19,10 @@ extern struct xilinx_fpga_op zynq_op; # define FPGA_ZYNQPL_OPS NULL #endif +#define XILINX_ZYNQ_7007S 0x3 #define XILINX_ZYNQ_7010 0x2 +#define XILINX_ZYNQ_7012S 0x1c +#define XILINX_ZYNQ_7014S 0x8 #define XILINX_ZYNQ_7015 0x1b #define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_7030 0xc @@ -28,7 +31,10 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_ZYNQ_7100 0x16 /* Device Image Sizes */ +#define XILINX_XC7Z007S_SIZE 16669920/8 #define XILINX_XC7Z010_SIZE 16669920/8 +#define XILINX_XC7Z012S_SIZE 28085344/8 +#define XILINX_XC7Z014S_SIZE 32364512/8 #define XILINX_XC7Z015_SIZE 28085344/8 #define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z030_SIZE 47839328/8 @@ -37,10 +43,22 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_XC7Z100_SIZE 139330784/8 /* Descriptor Macros */ +#define XILINX_XC7Z007S_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z007s" } + #define XILINX_XC7Z010_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ "7z010" } +#define XILINX_XC7Z012S_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z012s" } + +#define XILINX_XC7Z014S_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z014s" } + #define XILINX_XC7Z015_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ "7z015" } -- 1.9.1

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[U-Boot] [PATCH 1/5] ARM64: zynqmp: Adjust to new SMC interface to get silicon version
by Michal Simek 26 Oct '16

26 Oct '16

From: Soren Brinkmann <soren.brinkmann(a)xilinx.com> The new FW interface returns the IDCODE and version register, leaving extracting bitfields to the caller. Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/xilinx/zynqmp/zynqmp.c | 11 +++++++++++ include/zynqmppl.h | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index ba4dfbb47625..b0acaa5b7721 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -86,6 +86,17 @@ static int chip_id(void) smc_call(&regs); + /* + * SMC returns: + * regs[0][31:0] = status of the operation + * regs[0][63:32] = CSU.IDCODE register + * regs[1][31:0] = CSU.version register + */ + regs.regs[0] = upper_32_bits(regs.regs[0]); + regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | + ZYNQMP_CSU_IDCODE_SVD_MASK; + regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; + return regs.regs[0]; } diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 542ace9a03b9..fb5200ec84a6 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -16,6 +16,12 @@ #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2) +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ + ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) +#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 +#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xe << ZYNQMP_CSU_IDCODE_SVD_SHIFT) + extern struct xilinx_fpga_op zynqmp_op; #define XILINX_ZYNQMP_DESC \ -- 1.9.1

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[U-Boot] [PATCH] power: regulator: Add limits checking while setting voltage and current
by Keerthy 26 Oct '16

26 Oct '16

Currently the specific set ops functions are directly called without any check for voltage/current limits for a regulator. Check for them and proceed. Signed-off-by: Keerthy <j-keerthy(a)ti.com> --- drivers/power/regulator/regulator-uclass.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4434e36..089455e 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -41,6 +41,11 @@ int regulator_get_value(struct udevice *dev) int regulator_set_value(struct udevice *dev, int uV) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (uV < uc_pdata->min_uV || uV > uc_pdata->max_uV) + return -EINVAL; if (!ops || !ops->set_value) return -ENOSYS; @@ -61,6 +66,11 @@ int regulator_get_current(struct udevice *dev) int regulator_set_current(struct udevice *dev, int uA) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (uA < uc_pdata->min_uA || uA > uc_pdata->max_uA) + return -EINVAL; if (!ops || !ops->set_current) return -ENOSYS; -- 1.9.1

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[U-Boot] [PATCH v1 0/8] board: sama5d4: convert boards to support DM/DT
by Wenyou Yang 26 Oct '16

26 Oct '16

The purpose of patch set is to convert the board to support Device Tree and Driver Model. They are based on the following patches: 1./ [PATCH v3 0/2] pinctrl: at91: Add pinctrl driver http://lists.denx.de/pipermail/u-boot/2016-October/270991.html 2./ [PATCH v1 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D4 http://lists.denx.de/pipermail/u-boot/2016-October/271004.html 3./ [PATCH v3 0/2] serial: atmel_usart: Support to enable an early debug UART http://lists.denx.de/pipermail/u-boot/2016-October/270250.html 4./ [PATCH v1 0/3] gpio: at91_gpio: Add option and clock support http://lists.denx.de/pipermail/u-boot/2016-October/270687.html 5./ [PATCH v10] dm: at91: Add driver model support for the spi driver http://lists.denx.de/pipermail/u-boot/2016-October/270516.html Wenyou Yang (8): configs: at91-sama5_common: fix for CONFIG_AT91_GPIO board: sama5d4_xplained: move config options to *_defconfig board: sama5d4_xplained: clean up code board: sama5d4_xplained: enable early debug UART board: sama5d4ek: move config options to *_defconfig board: sama5d4ek: clean up code board: sama5d4ek: enable early debug UART configs: sama5d4: move CONFIG_SYS_NO_FLASH to *defconfig board/atmel/sama5d4_xplained/sama5d4_xplained.c | 122 +++-------------------- board/atmel/sama5d4ek/sama5d4ek.c | 124 +++--------------------- configs/sama5d4_xplained_mmc_defconfig | 31 +++++- configs/sama5d4_xplained_nandflash_defconfig | 33 ++++++- configs/sama5d4_xplained_spiflash_defconfig | 31 +++++- configs/sama5d4ek_mmc_defconfig | 31 +++++- configs/sama5d4ek_nandflash_defconfig | 31 +++++- configs/sama5d4ek_spiflash_defconfig | 31 +++++- include/configs/at91-sama5_common.h | 2 + include/configs/sama5d4_xplained.h | 33 +------ include/configs/sama5d4ek.h | 38 +------- 11 files changed, 216 insertions(+), 291 deletions(-) -- 2.7.4

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[U-Boot] [PATCH v1 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D4
by Wenyou Yang 26 Oct '16

26 Oct '16

The purpose of the patchset is add the dts files for boards, sama5d4 Xplained board and sama5d4ek board. Wenyou Yang (2): ARM: dts: at91: add dts file for sama5d4 Xplained board ARM: dts: at91: add dts file for sama5d4ek board arch/arm/dts/Makefile | 6 + arch/arm/dts/at91-sama5d4_xplained.dts | 285 +++++ arch/arm/dts/at91-sama5d4ek.dts | 340 ++++++ arch/arm/dts/sama5d4.dtsi | 1910 ++++++++++++++++++++++++++++++++ 4 files changed, 2541 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d4_xplained.dts create mode 100644 arch/arm/dts/at91-sama5d4ek.dts create mode 100644 arch/arm/dts/sama5d4.dtsi -- 2.7.4

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[U-Boot] [PATCH] dm: mmc: socfpga: fix MMC_OPS support
by Sylvain Lesne 26 Oct '16

26 Oct '16

Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at runtime. This adds the missing fields in the driver declaration. Signed-off-by: Sylvain Lesne <lesne(a)alse-fr.com> --- Hi, I might be missing something, but with the latest master, on a socfpga board, I get the following failure: U-Boot SPL 2016.11-rc2-00072-g869588d-dirty (Oct 24 2016 - 17:18:22) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC1 spl: partition error MMC: block number 0xx exceeds max(0xx) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### After some digging, it seems that the socfpga_dw_mmc driver slipped through the cracks during some steps of the DM conversion, so I added the missing fields of the driver declaration, mimicking what's done in the other dw_mmc_* drivers, and it works on my board. (Also, this is kind of unrelated, but it looks like the error message 'MMC: block number 0xx exceeds max(0xx)' has a formatting issue!) --- drivers/mmc/socfpga_dw_mmc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 5a3a4ff..0a22e58 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -151,7 +151,9 @@ U_BOOT_DRIVER(socfpga_dwmmc_drv) = { .id = UCLASS_MMC, .of_match = socfpga_dwmmc_ids, .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata, + .ops = &dm_dwmci_ops, .bind = socfpga_dwmmc_bind, .probe = socfpga_dwmmc_probe, .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data), + .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat), }; -- 1.9.1

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[U-Boot] [PATCH v3 0/2] pinctrl: at91: Add pinctrl driver
by Wenyou Yang 26 Oct '16

26 Oct '16

The purpose of this patch set is to add the pinctrl driver for AT91 PIO controller. Changes in v3: - Add support for OUTPUT config Changes in v2: - Add more information for the PINCTRL_AT91 option's help. - Add more comments for the callback of struct at91_pinctrl_mux_ops. - Use clrsetbits_le32() in set_drive_strength(). - Add the brackets for readability. - Use debug() to print the message to debug, instead of printf(). - Remove not veryuseful at91_bank_base(). - Add Reviewed-by tag. Wenyou Yang (2): gpio: at91_gpio: Remove CPU_HAS_PIO3 macro pinctrl: at91: Add pinctrl driver arch/arm/mach-at91/include/mach/at91_pio.h | 67 ++-- arch/arm/mach-at91/include/mach/at91sam9x5.h | 1 - arch/arm/mach-at91/include/mach/sama5d3.h | 1 - arch/arm/mach-at91/include/mach/sama5d4.h | 1 - board/atmel/sama5d3xek/sama5d3xek.c | 64 ++-- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 148 ++++---- board/atmel/sama5d4ek/sama5d4ek.c | 136 +++---- board/denx/ma5d4evk/ma5d4evk.c | 178 +++++----- board/l+g/vinco/vinco.c | 70 ++-- drivers/gpio/at91_gpio.c | 142 +++++--- drivers/pinctrl/Kconfig | 14 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-at91.c | 453 ++++++++++++++++++++++++ include/dt-bindings/pinctrl/at91.h | 2 + 14 files changed, 902 insertions(+), 376 deletions(-) create mode 100644 drivers/pinctrl/pinctrl-at91.c -- 2.7.4

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[U-Boot] [PATCH 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node
by Vignesh R 26 Oct '16

26 Oct '16

Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz. Signed-off-by: Vignesh R <vigneshr(a)ti.com> --- arch/arm/dts/dra7-evm.dts | 2 +- arch/arm/dts/dra72-evm-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index fe755c05841d..be36d456206d 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -505,7 +505,7 @@ spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1","spi-flash"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi index b0993e5bf7e0..1e1ca725577f 100644 --- a/arch/arm/dts/dra72-evm-common.dtsi +++ b/arch/arm/dts/dra72-evm-common.dtsi @@ -441,7 +441,7 @@ spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1", "spi-flash"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; -- 2.10.1

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[U-Boot] [PATCH v3 0/3]spi: Add ZynqMP QSPI driver support
by Siva Durga Prasad Paladugu 26 Oct '16

26 Oct '16

This series adds the qspi driver support for zynqmp Also sent a patch for not setting quad enable bit in the series as zynqmp qspi series wont work for micron devices with out that patch. Siva Durga Prasad Paladugu (3): spi: spi_flash: Dont set quad enable for micron in all cases spi: zynqmp_qspi: Add QSPI driver support for ZynqMP spi: zynqmp_qspi: Add qspi driver support for ZynqMP boards configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 4 + configs/xilinx_zynqmp_zcu102_defconfig | 4 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 4 + drivers/mtd/spi/spi_flash.c | 13 +- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/zynqmp_qspi.c | 705 +++++++++++++++++++++++ include/spi.h | 2 +- 8 files changed, 740 insertions(+), 2 deletions(-) create mode 100644 drivers/spi/zynqmp_qspi.c -- 2.7.4

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