October 2016 - U-Boot

[U-Boot] [PATCH v2] efi_loader: console: Correctly report modes
by Emmanuel Vadot 27 Oct '16

27 Oct '16

Add support for EFI console modes. Mode 0 is always 80x25 and present by EFI specification. Mode 1 is always 80x50 and not mandatory. Mode 2 and above is freely usable. If the terminal can handle mode 1, we mark it as supported. If the terminal size is greater than mode 0 and different than mode 1, we install it as mode 2. Modes can be switch with cout_set_mode. Changes in V2: Add mode switch Report only the modes that we support Signed-off-by: Emmanuel Vadot <manu(a)bidouilliste.com> --- lib/efi_loader/efi_console.c | 78 ++++++++++++++++++++++++++++++++++++-------- 1 file changed, 64 insertions(+), 14 deletions(-) diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c index 2e0228c..f4adc9e 100644 --- a/lib/efi_loader/efi_console.c +++ b/lib/efi_loader/efi_console.c @@ -9,11 +9,41 @@ #include <common.h> #include <efi_loader.h> -/* If we can't determine the console size, default to 80x24 */ -static int console_columns = 80; -static int console_rows = 24; static bool console_size_queried; +#define EFI_MAX_COUT_MODE 2 + +struct cout_mode { + unsigned long number; + unsigned long columns; + unsigned long rows; + int present; +}; + +static struct cout_mode efi_cout_modes[] = { + /* EFI Mode 0 is 80x25 and always present */ + { + .number = 0, + .columns = 80, + .rows = 25, + .present = 1, + }, + /* EFI Mode 1 is always 80x50 */ + { + .number = 1, + .columns = 80, + .rows = 50, + .present = 0, + }, + /* Value are unknown until we query the console */ + { + .number = 2, + .columns = 0, + .rows = 0, + .present = 0, + }, +}; + const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID; #define cESC '\x1b' @@ -56,6 +86,7 @@ const struct efi_console_control_protocol efi_console_control = { .lock_std_in = efi_cin_lock_std_in, }; +/* Default to mode 0 */ static struct simple_text_output_mode efi_con_mode = { .max_mode = 0, .mode = 0, @@ -140,12 +171,12 @@ static efi_status_t EFIAPI efi_cout_output_string( if (ch == '\n') { efi_con_mode.cursor_column = 1; efi_con_mode.cursor_row++; - } else if (efi_con_mode.cursor_column > console_columns) { + } else if (efi_con_mode.cursor_column > efi_cout_modes[efi_con_mode.mode].columns) { efi_con_mode.cursor_column = 1; efi_con_mode.cursor_row++; } - if (efi_con_mode.cursor_row > console_rows) { - efi_con_mode.cursor_row = console_rows; + if (efi_con_mode.cursor_row > efi_cout_modes[efi_con_mode.mode].rows) { + efi_con_mode.cursor_row = efi_cout_modes[efi_con_mode.mode].rows; } } @@ -191,15 +222,32 @@ static efi_status_t EFIAPI efi_cout_query_mode( goto out; } - console_columns = n[2]; - console_rows = n[1]; + /* Test if we can have Mode 1 */ + if (n[2] >= 80 && n[1] >= 50) { + efi_cout_modes[1].present = 1; + efi_con_mode.max_mode = 1; + } + + /* Install our mode as mode 2 if it is different than mode 0 or 1 and set it to the default one */ + if ((n[2] != 80 && n[1] != 25) || (n[2] != 80 && n[1] != 50)) { + efi_cout_modes[EFI_MAX_COUT_MODE].columns = n[2]; + efi_cout_modes[EFI_MAX_COUT_MODE].rows = n[1]; + efi_cout_modes[EFI_MAX_COUT_MODE].present = 1; + efi_con_mode.max_mode = EFI_MAX_COUT_MODE; + efi_con_mode.mode = EFI_MAX_COUT_MODE; + } } + if (mode_number > efi_con_mode.max_mode) + return EFI_EXIT(EFI_UNSUPPORTED); + if (efi_cout_modes[mode_number].present != 1) + return EFI_EXIT(EFI_UNSUPPORTED); + out: if (columns) - *columns = console_columns; + *columns = efi_cout_modes[mode_number].columns; if (rows) - *rows = console_rows; + *rows = efi_cout_modes[mode_number].rows; return EFI_EXIT(EFI_SUCCESS); } @@ -210,11 +258,13 @@ static efi_status_t EFIAPI efi_cout_set_mode( { EFI_ENTRY("%p, %ld", this, mode_number); - /* We only support text output for now */ - if (mode_number == EFI_CONSOLE_MODE_TEXT) - return EFI_EXIT(EFI_SUCCESS); - return EFI_EXIT(EFI_UNSUPPORTED); + if (mode_number > efi_con_mode.max_mode) + return EFI_EXIT(EFI_UNSUPPORTED); + + efi_con_mode.mode = mode_number; + + return EFI_EXIT(EFI_SUCCESS); } static efi_status_t EFIAPI efi_cout_set_attribute( -- 2.9.2

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[U-Boot] [PATCH V2 1/4] ARM: tegra: ensure nvtboot_boot_x0 alignment
by Stephen Warren 27 Oct '16

27 Oct '16

From: Stephen Warren <swarren(a)nvidia.com> nvtboot_boot_x0 is a 64-bit variable and hence must be 64-bit aligned. So far this has happened by accident! Fix the code so this is guaranteed. This fixes the following build error: ... relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC against symbol `nvtboot_boot_x0' ... Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- v2: New patch. --- arch/arm/mach-tegra/tegra186/nvtboot_ll.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S index 1eab890958c7..899c9cccbe84 100644 --- a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S +++ b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S @@ -9,6 +9,7 @@ #include <config.h> #include <linux/linkage.h> +.align 8 .globl nvtboot_boot_x0 nvtboot_boot_x0: .dword 0 -- 2.10.1

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[U-Boot] [PATCH v3 00/10] sunxi: sun5/7i: add the psci suspend function
by Antoine Tenart 27 Oct '16

27 Oct '16

Hi all, This series adds an implementation of the psci suspend function for both sun5i and sun7i. This was tested on Nextthing's CHIP and on a A20, using cpuidle in Linux. My tests showed a power consumption reduced by nearly a factor 2 on the CHIP when the system was idle. It went from ~1W without cpuidle enabled to ~0.6W. As the sun5i does not have a GIC, I needed to remove some code from the generic psci code. To do this I added an ARM_GIC Kconfig option which needs to be selected by each SoC having a GIC. I already added the relevant lines for SoCs using the PSCI ARMv7 code. As this Kconfig option is currently only used in the psci code, it should be safe to add it even if all the SoCs having a GIC do not select it, as long as they don't have psci functions. On multi-core systems, we need to ensure all CPU are in psci suspend function to switch the cpu clk source. Likewise, the first CPU to exit the psci suspend function should restore the cpu clk source; and only the first one. This series adds a few atomic operation (with return support) in order to solve this problem. Please review them carefully as I'm not sure about the implementation of such functions. Thanks! Antoine Since v2: - Stopped putting the dram into self-refresh. - Removed pll2-7 disabling. - Added an atomic variable to only change the cpuclk source when all CPUs are in idle. - Did a similar implementation to be sure the first CPU to leave the idle mode switches back the cpuclk source to pll1. - Rebased on the latest master and updated the patches. Since v1: - Rebased on the latest master and updated the patches. - Fixed a compile warning I introduced in virt-v7.c - Added the missing ARM_GIC Kconfig options. - Fixed a commit message (removed 'HYP'). Antoine Tenart (10): arm: add atomic functions with return support ARM: add the ARM_GIC configuration option sunxi: select ARM_GIC for sun[6789]i ARM: select ARM_GIC for SoCs having a psci implementation exynos: select ARM_GIC for TARGET_ARNDALE tegra: select ARM_GIC for Tegra TK1s ARM: PSCI: protect GIC specific code with ARM_GIC sun5/7i: add an implementation of the psci suspend function sun5i: add defines used by the PSCI code sun5i: boot in non-secure mode by default arch/arm/Kconfig | 11 +++ arch/arm/cpu/armv7/nonsec_virt.S | 6 ++ arch/arm/cpu/armv7/sunxi/Makefile | 9 ++- arch/arm/cpu/armv7/sunxi/psci.c | 2 +- arch/arm/cpu/armv7/sunxi/psci_suspend.c | 108 ++++++++++++++++++++++++++ arch/arm/cpu/armv7/virt-v7.c | 42 ++++++---- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 6 ++ arch/arm/include/asm/atomic.h | 34 ++++++++ arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-tegra/tegra124/Kconfig | 2 + board/sunxi/Kconfig | 10 +++ include/configs/sun5i.h | 3 + 12 files changed, 218 insertions(+), 16 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/psci_suspend.c -- 2.10.1

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[U-Boot] [PATCH] axs10x: Introduce UART clk device
by Vlad Zakharov 27 Oct '16

27 Oct '16

This commit introduces UART clock device for AXS10x boards. It provides a fixed clock rate of 33,333333 MHz. It is used as an input clock by uart0 driver, so we add corresponding reference to uart0 node in device tree. Also we removing legacy clock specifications via CONFIG_SYS_NS16550_CLK which we finally may get rid of. Signed-off-by: Vlad Zakharov <vzakhar(a)synopsys.com> --- arch/arc/dts/axs10x.dts | 8 ++++++++ include/configs/axs10x.h | 1 - 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arc/dts/axs10x.dts b/arch/arc/dts/axs10x.dts index 391d067..0b0e2bb 100644 --- a/arch/arc/dts/axs10x.dts +++ b/arch/arc/dts/axs10x.dts @@ -23,9 +23,17 @@ }; }; + uartclk: uartclk { + compatible = "fixed-clock"; + clock-frequency = <33333333>; + #clock-cells = <0>; + u-boot,dm-pre-reloc; + }; + uart0: serial0@e0022000 { compatible = "snps,dw-apb-uart"; reg = <0xe0022000 0x1000>; + clocks = <&uartclk>; reg-shift = <2>; reg-io-width = <4>; }; diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index b99248e..3546c8d 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -52,7 +52,6 @@ */ #define CONFIG_DW_SERIAL #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 33333333 #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_BAUDRATE 115200 -- 2.7.4

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[U-Boot] [PATCH] spi: kirkwood_spi: implement mvebu_spi_set_mode()
by Chris Packham 27 Oct '16

27 Oct '16

Set the appropriate bits in the interface config register based on the SPI_ mode flags. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- arch/arm/include/asm/arch-mvebu/spi.h | 4 ++++ drivers/spi/kirkwood_spi.c | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h index 78869a253d1f..3545aed17347 100644 --- a/arch/arm/include/asm/arch-mvebu/spi.h +++ b/arch/arm/include/asm/arch-mvebu/spi.h @@ -52,6 +52,10 @@ struct kwspi_registers { #define KWSPI_ADRLEN_3BYTE (2 << 8) #define KWSPI_ADRLEN_4BYTE (3 << 8) #define KWSPI_ADRLEN_MASK (3 << 8) +#define KWSPI_CPOL (1 << 11) +#define KWSPI_CPHA (1 << 12) +#define KWSPI_TXLSBF (1 << 13) +#define KWSPI_RXLSBF (1 << 14) #define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ #define KWSPI_IRQMASK 0 /* mask SPI interrupt */ diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 6851ba942f51..69a0be9ea5b2 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -271,6 +271,19 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz) static int mvebu_spi_set_mode(struct udevice *bus, uint mode) { + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + struct kwspi_registers *reg = plat->spireg; + u32 data = readl(&reg->cfg); + + if (mode & SPI_CPHA) + data |= KWSPI_CPHA; + if (mode & SPI_CPOL) + data |= KWSPI_CPOL; + if (mode & SPI_LSB_FIRST) + data |= (KWSPI_RXLSBF | KWSPI_TXLSBF); + + writel(data, &reg->cfg); + return 0; } -- 2.10.0.479.g7c56b16

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[U-Boot] Unable to decompress files greater than 500 MB
by Zakir Ahmed 27 Oct '16

27 Oct '16

Hi, We are using u-boot source code which has the support for most of the compressions like bz2, lzma, gz etc. We tried uncompressing bz2, lzma and gz images and most of them either fail or data abort or hang indefinitely for large sized uncompressed data > 500 MB. This is for the arm port. Could you please provide us any pointers for the same? signature

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[U-Boot] [PATCH 2/2] armv8: ls1046aqds: add lpuart support
by shh.xie＠gmail.com 27 Oct '16

27 Oct '16

From: Shaohui Xie <Shaohui.Xie(a)nxp.com> LPUART0 is used by default, and it's using platform clock, if a different clock is preferred, user can define CONFIG_LPUART_CLK. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)nxp.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1046a-qds-lpuart.dts | 16 ++++++++++ arch/arm/dts/fsl-ls1046a-qds.dtsi | 4 +++ arch/arm/dts/fsl-ls1046a.dtsi | 54 +++++++++++++++++++++++++++++++++ board/freescale/ls1046aqds/ls1046aqds.c | 21 +++++++++++++ configs/ls1046aqds_lpuart_defconfig | 29 ++++++++++++++++++ include/configs/ls1046aqds.h | 8 +++++ 7 files changed, 133 insertions(+) create mode 100644 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts create mode 100644 configs/ls1046aqds_lpuart_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 715e9bd..4a7d53b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -144,6 +144,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ fsl-ls1046a-qds-duart.dtb \ + fsl-ls1046a-qds-lpuart.dtb \ fsl-ls1046a-rdb.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts new file mode 100644 index 0000000..21243d0 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1046a-qds.dtsi" + +/ { + chosen { + stdout-path = &lpuart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index c512293..a49ca08 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -75,3 +75,7 @@ &duart1 { status = "okay"; }; + +&lpuart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 87dd997..359a9d1 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -151,6 +151,60 @@ clocks = <&clockgen 4 0>; }; + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <0 48 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <0 49 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <0 50 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <0 51 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <0 52 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <0 53 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + qspi: quadspi@1550000 { compatible = "fsl,vf610-qspi"; #address-cells = <1>; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 8c18538..96d929d 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -120,6 +120,16 @@ unsigned long get_board_ddr_clk(void) return 66666666; } +#ifdef CONFIG_LPUART +u32 get_lpuart_clk(void) +{ +#ifdef CONFIG_LPUART_CLK + return CONFIG_LPUART_CLK; +#endif + return gd->bus_clk; +} +#endif + int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -157,6 +167,9 @@ int board_early_init_f(void) struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; #endif +#ifdef CONFIG_LPUART + u8 uart; +#endif #ifdef CONFIG_SYS_I2C_EARLY_INIT i2c_early_init_f(); @@ -175,6 +188,14 @@ int board_early_init_f(void) out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif +#ifdef CONFIG_LPUART + /* We use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[14]); + uart &= ~CFG_UART_MUX_MASK; + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; + QIXIS_WRITE(brdcfg[14], uart); +#endif + return 0; } diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig new file mode 100644 index 0000000..8e5b45d --- /dev/null +++ b/configs/ls1046aqds_lpuart_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" +CONFIG_BOOTDELAY=10 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_FSL_DSPI=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 2e5c2f1..bc71770 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -132,6 +132,14 @@ unsigned long get_board_ddr_clk(void); #endif #endif +/* LPUART */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#define CFG_UART_MUX_MASK 0x6 +#define CFG_UART_MUX_SHIFT 1 +#define CFG_LPUART_EN 0x2 +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/5] arm: dts: exynos4x12: fix the minor things
by Jaehoon Chung 27 Oct '16

27 Oct '16

Fixed the minor things. 1. Removed '`' thing in comments 2. Fix the wrong interrupts value from 77 to 131 Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- arch/arm/dts/exynos4x12.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/exynos4x12.dtsi b/arch/arm/dts/exynos4x12.dtsi index 5d58c6e..b83a0d3 100644 --- a/arch/arm/dts/exynos4x12.dtsi +++ b/arch/arm/dts/exynos4x12.dtsi @@ -14,7 +14,7 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as -` * published by the Free Software Foundation. + * published by the Free Software Foundation. */ #include "exynos4.dtsi" @@ -104,7 +104,7 @@ mshc_0: mmc@12550000 { compatible = "samsung,exynos4412-dw-mshc"; reg = <0x12550000 0x1000>; - interrupts = <0 77 0>; + interrupts = <0 131 0>; #address-cells = <1>; #size-cells = <0>; fifo-depth = <0x80>; -- 2.10.1

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[U-Boot] [Resend RFC PATCH 0/2] Fix armv8 cache flushing
by York Sun 26 Oct '16

26 Oct '16

I have been puzzled by the need to flush external L3 cache for Freescale Layerscape series SoCs. Flushing L3 requires EL3. It is the case now, but this may change in the future. Implementing a SMC call to perform this task is possible but only if necessary. Recent investigation shows we can flush by virtual address most of the time. The only exception is when dcache_disable() is called. I think this can be addressed by flushing the stack U-Boot is using and skip flushing L3 totally. Once this is proved to work, we can drop flushing L3 all together. During this investigation, I found the procedure of turning off d-cache seems wrong. The data is lost if d-cache is off first. I am not sure if this only happens to Freescale Layerscape SoCs. Wondering why no one else reports any issue, expecially those SoCs without L3 cache. York Sun (2): armv8: Fix dcache disable function armv8: Fix flush_dcache_all function arch/arm/cpu/armv8/cache_v8.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) -- 2.7.4

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Re: [U-Boot] [Resend RFC PATCH 1/2] armv8: Fix dcache disable function
by york sun 26 Oct '16

26 Oct '16

On 10/26/2016 12:54 PM, york.sun(a)nxp.com wrote: > On 10/26/2016 12:47 PM, Stephen Warren wrote: >> >> There are two data structures in ARM U-Boot that describe memory layout: >> >> 1) A list of RAM memory regions. U-Boot uses these to know where to >> relocate itself to (it relocates itself to the top of RAM at boot), and >> to fill in the /memory node when booting an OS using DT (and other >> equivalent mechanisms when not using DT.) >> >> 2) For AArch64 specifically, there's a memory map table that defines all >> RAM and MMIO regions, and the translation table attributes required for >> those regions. >> >> Judging by your comments later in the original message, it sounds like >> it'd be fine to read from these structures during any dcache clean >> routine provided the table has already been cleaned. That makes using >> the tables much more tractable:-) >> > > I think we need to benchmark walking through the MMU tables. It can map > huge amount of memory. For our case, it is more than 16GB. I have been > reluctant to do so for the size. I am now back testing to revert _this_ > patch, hoping to confirm what I learned from this discussion. I came back from my testing and I have more questions than answers. For _this_ patch, I proposed to flush cache before disabling them, noting once the dcache is disabled, the staled data in dirty cache is not visible to the core. My argument was if we flush L1/L2, they could end up in L3 (I don't know for sure). If I want to skip flushing L3, I have to fix it. During this discussion, I thought I made a mistake by flushing L1/L2 by way/set first, then flushing by VA. Actually I didn't. I flushed by VA first. With my today's test, the baseline (working in the sense of booting Linux) is PATCH 1/2 armv8: Fix dcache disable function PATCH 2/2 armv8: Fix flush_dcache_all function With these two patches, I flush the stack up to top of U-Boot by VA, followed by flush by set/way. L3 is not flushed. Then d-cache is disabled. I know this is not a real "flush all" procedure. With this modified procedure, I can continue to boot Linux. If I revert patch 1, i.e. to disable dcache before flushing, I can see the data is not visible from the core (debug with JTAG tool). My hope was the staled data should be flushed to main memory if flushed by VA. That's not the case. The main memory doesn't have the correct data. So my new question is, why flushing by VA doesn't flush the data to main memory? Do I need to flush the cache while cache is enabled? York

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