January 2016 - U-Boot

[U-Boot] [PATCH v3] powerpc/SECURE_BOOT: Add PAMU driver
by Aneesh Bansal 17 Jan '16

17 Jan '16

PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)nxp.com> --- Changes in v3: Replace the Debug printf() call with debug() Merged the two commits into a single commit Changes in v2: Replace the Debug printf() call with debug() arch/powerpc/cpu/mpc85xx/cpu_init.c | 18 +- arch/powerpc/cpu/mpc8xxx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 433 ++++++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/pamu_table.c | 55 +++++ arch/powerpc/include/asm/fsl_pamu.h | 169 +++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 19 +- drivers/crypto/fsl/jr.c | 23 ++ 7 files changed, 709 insertions(+), 9 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c create mode 100644 arch/powerpc/cpu/mpc8xxx/pamu_table.c create mode 100644 arch/powerpc/include/asm/fsl_pamu.h diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 13a7d0f..50bb86a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -30,6 +30,10 @@ #ifdef CONFIG_FSL_CAAM #include <fsl_sec.h> #endif +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) +#include <asm/fsl_pamu.h> +#include <fsl_secboot_err.h> +#endif #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include <nand.h> #include <errno.h> @@ -425,8 +429,7 @@ void fsl_erratum_a007212_workaround(void) ulong cpu_init_f(void) { extern void m8560_cpm_reset (void); -#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \ - (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)) +#ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_SECURE_BOOT) @@ -458,12 +461,6 @@ ulong cpu_init_f(void) #if defined(CONFIG_SYS_CPC_REINIT_F) disable_cpc_sram(); #endif - -#if defined(CONFIG_FSL_CORENET) - /* Put PAMU in bypass mode */ - out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS); -#endif - #endif #ifdef CONFIG_CPM2 @@ -940,6 +937,11 @@ int cpu_init_r(void) fman_enet_init(); #endif +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) + if (pamu_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#endif + #ifdef CONFIG_FSL_CAAM sec_init(); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index ac45e0e..c5592cd 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -24,5 +24,6 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_FSL_LBC) += fsl_lbc.o obj-$(CONFIG_SYS_SRIO) += srio.o obj-$(CONFIG_FSL_LAW) += law.o +obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o endif diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c new file mode 100644 index 0000000..8ad3b7c --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -0,0 +1,433 @@ +/* + * FSL PAMU driver + * + * Copyright 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/log2.h> +#include <malloc.h> +#include <asm/fsl_pamu.h> + +struct paace *ppaact; +struct paace *sec; +unsigned long fspi; + +static inline int __ilog2_roundup_64(uint64_t val) +{ + if ((val & (val - 1)) == 0) + return __ilog2_u64(val); + else + return __ilog2_u64(val) + 1; +} + + +static inline int count_lsb_zeroes(unsigned long val) +{ + return ffs(val) - 1; +} + +static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size) +{ + /* window size is 2^(WSE+1) bytes */ + return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) + + PAMU_PAGE_SHIFT - 1; +} + +static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt) +{ + /* window count is 2^(WCE+1) bytes */ + return count_lsb_zeroes(subwindow_cnt) - 1; +} + +static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace) +{ + set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY); + set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR, + PAACE_M_COHERENCE_REQ); +} + +static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace) +{ + set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY); + set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR, + PAACE_M_COHERENCE_REQ); +} + +/** Sets up PPAACE entry for specified liodn + * + * @param[in] liodn Logical IO device number + * @param[in] win_addr starting address of DSA window + * @param[in] win-size size of DSA window + * @param[in] omi Operation mapping index -- if ~omi == 0 then omi + not defined + * @param[in] stashid cache stash id for associated cpu -- if ~stashid == 0 + then stashid not defined + * @param[in] snoopid snoop id for hardware coherency -- if ~snoopid == 0 + then snoopid not defined + * @param[in] subwin_cnt number of sub-windows + * + * @return Returns 0 upon success else error code < 0 returned + */ +static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr, + uint64_t win_size, uint32_t omi, + uint32_t snoopid, uint32_t stashid, + uint32_t subwin_cnt) +{ + struct paace *ppaace; + + if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE) + return -1; + + if (win_addr & (win_size - 1)) + return -2; + + if (liodn > NUM_PPAACT_ENTRIES) { + printf("Entries in PPACT not sufficient\n"); + return -3; + } + + ppaace = &ppaact[liodn]; + + /* window size is 2^(WSE+1) bytes */ + set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE, + map_addrspace_size_to_wse(win_size)); + + pamu_setup_default_xfer_to_host_ppaace(ppaace); + + if (sizeof(phys_addr_t) > 4) + ppaace->wbah = (u64)win_addr >> (PAMU_PAGE_SHIFT + 20); + else + ppaace->wbah = 0; + + set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, + (win_addr >> PAMU_PAGE_SHIFT)); + + /* set up operation mapping if it's configured */ + if (omi < OME_NUMBER_ENTRIES) { + set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED); + ppaace->op_encode.index_ot.omi = omi; + } else if (~omi != 0) { + return -3; + } + + /* configure stash id */ + if (~stashid != 0) + set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid); + + /* configure snoop id */ + if (~snoopid != 0) + ppaace->domain_attr.to_host.snpid = snoopid; + + if (subwin_cnt) { + /* window count is 2^(WCE+1) bytes */ + set_bf(ppaace->impl_attr, PAACE_IA_WCE, + map_subwindow_cnt_to_wce(subwin_cnt)); + set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1); + ppaace->fspi = fspi; + fspi = fspi + DEFAULT_NUM_SUBWINDOWS - 1; + } else { + set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL); + } + + asm volatile("sync" : : : "memory"); + /* Mark the ppace entry valid */ + ppaace->addr_bitfields |= PAACE_V_VALID; + asm volatile("sync" : : : "memory"); + + return 0; +} + +static int pamu_config_spaace(uint32_t liodn, + uint64_t subwin_size, uint64_t subwin_addr, uint64_t size, + uint32_t omi, uint32_t snoopid, uint32_t stashid) +{ + struct paace *paace; + /* Align start addr of subwin to subwindoe size */ + uint64_t sec_addr = subwin_addr & ~(subwin_size - 1); + uint64_t end_addr = subwin_addr + size; + int size_shift = __ilog2_u64(subwin_size); + uint64_t win_size = 0; + uint32_t index, swse; + unsigned long fspi_idx; + + /* Recalculate the size */ + size = end_addr - sec_addr; + + if (!subwin_size) + return -1; + + if (liodn > NUM_PPAACT_ENTRIES) { + printf("LIODN No programmed %d > no. of PPAACT entries %d\n", + liodn, NUM_PPAACT_ENTRIES); + return -1; + } + + while (sec_addr < end_addr) { + debug("sec_addr < end_addr is %llx < %llx\n", sec_addr, + end_addr); + paace = &ppaact[liodn]; + if (!paace) + return -1; + fspi_idx = paace->fspi; + + /* Calculating the win_size here as if we map in index 0, + paace entry woudl need to be programmed for SWSE */ + win_size = end_addr - sec_addr; + win_size = 1 << __ilog2_roundup_64(win_size); + + if (win_size > subwin_size) + win_size = subwin_size; + else if (win_size < PAMU_PAGE_SIZE) + win_size = PAMU_PAGE_SIZE; + + debug("win_size is %x\n", win_size); + + swse = map_addrspace_size_to_wse(win_size); + index = sec_addr >> size_shift; + + if (index == 0) { + set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse); + set_bf(paace->addr_bitfields, PAACE_AF_AP, + PAACE_AP_PERMS_ALL); + sec_addr += subwin_size; + continue; + } + + paace = sec + fspi_idx + index - 1; + + debug("SPAACT:Writing at location %p, index %d\n", paace, + index); + + pamu_setup_default_xfer_to_host_spaace(paace); + set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn); + set_bf(paace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL); + + /* configure snoop id */ + if (~snoopid != 0) + paace->domain_attr.to_host.snpid = snoopid; + + if (paace->addr_bitfields & PAACE_V_VALID) { + debug("Reached overlap condition\n"); + debug("%d < %d\n", get_bf(paace->win_bitfields, + PAACE_WIN_SWSE), swse); + if (get_bf(paace->win_bitfields, PAACE_WIN_SWSE) < swse) + set_bf(paace->win_bitfields, PAACE_WIN_SWSE, + swse); + } else { + set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse); + } + + paace->addr_bitfields |= PAACE_V_VALID; + sec_addr += subwin_size; + } + + return 0; +} + +int pamu_init(void) +{ + u32 base_addr = CONFIG_SYS_PAMU_ADDR; + struct ccsr_pamu *regs; + u32 i = 0; + u64 ppaact_phys, ppaact_lim, ppaact_size; + u64 spaact_phys, spaact_lim, spaact_size; + + ppaact_size = sizeof(struct paace) * NUM_PPAACT_ENTRIES; + spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES; + + /* Allocate space for Primary PAACT Table */ + ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size); + if (!ppaact) + return -1; + memset(ppaact, 0, ppaact_size); + + /* Allocate space for Secondary PAACT Table */ + sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size); + if (!sec) + return -1; + memset(sec, 0, spaact_size); + + ppaact_phys = virt_to_phys((void *)ppaact); + ppaact_lim = ppaact_phys + ppaact_size; + + spaact_phys = (uint64_t)virt_to_phys((void *)sec); + spaact_lim = spaact_phys + spaact_size; + + /* Configure all PAMU's */ + for (i = 0; i < CONFIG_NUM_PAMU; i++) { + regs = (struct ccsr_pamu *)base_addr; + + out_be32(&regs->ppbah, ppaact_phys >> 32); + out_be32(&regs->ppbal, (uint32_t)ppaact_phys); + + out_be32(&regs->pplah, (ppaact_lim) >> 32); + out_be32(&regs->pplal, (uint32_t)ppaact_lim); + + if (sec != NULL) { + out_be32(&regs->spbah, spaact_phys >> 32); + out_be32(&regs->spbal, (uint32_t)spaact_phys); + out_be32(&regs->splah, spaact_lim >> 32); + out_be32(&regs->splal, (uint32_t)spaact_lim); + } + asm volatile("sync" : : : "memory"); + + base_addr += PAMU_OFFSET; + } + + return 0; +} + +void pamu_enable(void) +{ + u32 i = 0; + u32 base_addr = CONFIG_SYS_PAMU_ADDR; + for (i = 0; i < CONFIG_NUM_PAMU; i++) { + setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, + PAMU_PCR_PE); + asm volatile("sync" : : : "memory"); + base_addr += PAMU_OFFSET; + } +} + +void pamu_reset(void) +{ + u32 i = 0; + u32 base_addr = CONFIG_SYS_PAMU_ADDR; + struct ccsr_pamu *regs; + + for (i = 0; i < CONFIG_NUM_PAMU; i++) { + regs = (struct ccsr_pamu *)base_addr; + /* Clear PPAACT Base register */ + out_be32(&regs->ppbah, 0); + out_be32(&regs->ppbal, 0); + out_be32(&regs->pplah, 0); + out_be32(&regs->pplal, 0); + out_be32(&regs->spbah, 0); + out_be32(&regs->spbal, 0); + out_be32(&regs->splah, 0); + out_be32(&regs->splal, 0); + + clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE); + asm volatile("sync" : : : "memory"); + base_addr += PAMU_OFFSET; + } +} + +void pamu_disable(void) +{ + u32 i = 0; + u32 base_addr = CONFIG_SYS_PAMU_ADDR; + + + for (i = 0; i < CONFIG_NUM_PAMU; i++) { + clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); + asm volatile("sync" : : : "memory"); + base_addr += PAMU_OFFSET; + } +} + + +static uint64_t find_max(uint64_t arr[], int num) +{ + int i = 0; + int max = 0; + for (i = 1 ; i < num; i++) + if (arr[max] < arr[i]) + max = i; + + return arr[max]; +} + +static uint64_t find_min(uint64_t arr[], int num) +{ + int i = 0; + int min = 0; + for (i = 1 ; i < num; i++) + if (arr[min] > arr[i]) + min = i; + + return arr[min]; +} + +static uint32_t get_win_cnt(uint64_t size) +{ + uint32_t win_cnt = DEFAULT_NUM_SUBWINDOWS; + + while (win_cnt && (size/win_cnt) < PAMU_PAGE_SIZE) + win_cnt >>= 1; + + return win_cnt; +} + +int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn) +{ + int i = 0; + int ret = 0; + uint32_t num_sec_windows = 0; + uint32_t num_windows = 0; + uint64_t min_addr, max_addr; + uint64_t size; + uint64_t subwin_size; + int sizebit; + + min_addr = find_min(tbl->start_addr, num_entries); + max_addr = find_max(tbl->end_addr, num_entries); + size = max_addr - min_addr + 1; + + if (!size) + return -1; + + sizebit = __ilog2_roundup_64(size); + size = 1 << sizebit; + debug("min start_addr is %llx\n", min_addr); + debug("max end_addr is %llx\n", max_addr); + debug("size found is %llx\n", size); + + if (size < PAMU_PAGE_SIZE) + size = PAMU_PAGE_SIZE; + + while (1) { + min_addr = min_addr & ~(size - 1); + if (min_addr + size > max_addr) + break; + size <<= 1; + if (!size) + return -1; + } + debug("PAACT :Base addr is %llx\n", min_addr); + debug("PAACT : Size is %llx\n", size); + num_windows = get_win_cnt(size); + /* For a single window, no spaact entries are required + * sec_sub_window count = 0 */ + if (num_windows > 1) + num_sec_windows = num_windows; + else + num_sec_windows = 0; + + ret = pamu_config_ppaace(liodn, min_addr, + size , -1, -1, -1, num_sec_windows); + + if (ret < 0) + return ret; + + debug("configured ppace\n"); + + if (num_sec_windows) { + subwin_size = size >> count_lsb_zeroes(num_sec_windows); + debug("subwin_size is %llx\n", subwin_size); + + for (i = 0; i < num_entries; i++) { + ret = pamu_config_spaace(liodn, + subwin_size, tbl->start_addr[i] - min_addr, + tbl->size[i], -1, -1, -1); + + if (ret < 0) + return ret; + } + } + + return ret; +} diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c new file mode 100644 index 0000000..26c5ea4 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -0,0 +1,55 @@ +/* + * Copyright 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_pamu.h> + +DECLARE_GLOBAL_DATA_PTR; + +void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) +{ + int i = 0; + int j; + + tbl->start_addr[i] = + (uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE); + tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); + tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; + + i++; +#ifdef CONFIG_SYS_FLASH_BASE_PHYS + tbl->start_addr[i] = + (uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS); + tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */ + tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; + + i++; +#endif + debug("PAMU address\t\t\tsize\n"); + for (j = 0; j < i ; j++) + debug("%llx \t\t\t%llx\n", tbl->start_addr[j], tbl->size[j]); + + *num_entries = i; +} + +int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s) +{ + struct pamu_addr_tbl tbl; + int num_entries = 0; + int ret = 0; + + construct_pamu_addr_table(&tbl, &num_entries); + + ret = config_pamu(&tbl, num_entries, liodn_ns); + if (ret) + return ret; + + ret = config_pamu(&tbl, num_entries, liodn_s); + if (ret) + return ret; + + return ret; +} diff --git a/arch/powerpc/include/asm/fsl_pamu.h b/arch/powerpc/include/asm/fsl_pamu.h new file mode 100644 index 0000000..93a7cae --- /dev/null +++ b/arch/powerpc/include/asm/fsl_pamu.h @@ -0,0 +1,169 @@ +/* + * Copyright 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PAMU_H +#define __PAMU_H + +#define CONFIG_NUM_PAMU 16 +#define NUM_PPAACT_ENTRIES 512 +#define NUM_SPAACT_ENTRIES 256 + +/* PAMU_OFFSET to the next pamu space in ccsr */ +#define PAMU_OFFSET 0x1000 + +#define PAMU_TABLE_ALIGNMENT 0x00001000 + +#define PAMU_PAGE_SHIFT 12 +#define PAMU_PAGE_SIZE 4096U + +#define PAACE_M_COHERENCE_REQ 0x01 + +#define PAACE_DA_HOST_CR 0x80 +#define PAACE_DA_HOST_CR_SHIFT 7 + +#define PAACE_AF_PT 0x00000002 +#define PAACE_AF_PT_SHIFT 1 + +#define PAACE_PT_PRIMARY 0x0 +#define PAACE_PT_SECONDARY 0x1 + +#define PPAACE_AF_WBAL 0xfffff000 +#define PPAACE_AF_WBAL_SHIFT 12 + +#define OME_NUMBER_ENTRIES 16 /* based on P4080 2.0 silicon plan */ + +#define PAACE_IA_CID 0x00FF0000 +#define PAACE_IA_CID_SHIFT 16 +#define PAACE_IA_WCE 0x000000F0 +#define PAACE_IA_WCE_SHIFT 4 +#define PAACE_IA_ATM 0x0000000C +#define PAACE_IA_ATM_SHIFT 2 +#define PAACE_IA_OTM 0x00000003 +#define PAACE_IA_OTM_SHIFT 0 + +#define PAACE_OTM_NO_XLATE 0x00 +#define PAACE_OTM_IMMEDIATE 0x01 +#define PAACE_OTM_INDEXED 0x02 +#define PAACE_OTM_RESERVED 0x03 +#define PAACE_ATM_NO_XLATE 0x00 +#define PAACE_ATM_WINDOW_XLATE 0x01 +#define PAACE_ATM_PAGE_XLATE 0x02 +#define PAACE_ATM_WIN_PG_XLATE \ + (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE) +#define PAACE_WIN_TWBAL 0xfffff000 +#define PAACE_WIN_TWBAL_SHIFT 12 +#define PAACE_WIN_SWSE 0x00000fc0 +#define PAACE_WIN_SWSE_SHIFT 6 + +#define PAACE_AF_AP 0x00000018 +#define PAACE_AF_AP_SHIFT 3 +#define PAACE_AF_DD 0x00000004 +#define PAACE_AF_DD_SHIFT 2 +#define PAACE_AF_PT 0x00000002 +#define PAACE_AF_PT_SHIFT 1 +#define PAACE_AF_V 0x00000001 +#define PAACE_AF_V_SHIFT 0 +#define PPAACE_AF_WSE 0x00000fc0 +#define PPAACE_AF_WSE_SHIFT 6 +#define PPAACE_AF_MW 0x00000020 +#define PPAACE_AF_MW_SHIFT 5 + +#define PAACE_AP_PERMS_DENIED 0x0 +#define PAACE_AP_PERMS_QUERY 0x1 +#define PAACE_AP_PERMS_UPDATE 0x2 +#define PAACE_AP_PERMS_ALL 0x3 + +#define SPAACE_AF_LIODN 0xffff0000 +#define SPAACE_AF_LIODN_SHIFT 16 +#define PAACE_V_VALID 0x1 + +#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << \ + (m##_SHIFT)) & (m))) +#define get_bf(v, m) (((v) & (m)) >> (m##_SHIFT)) + +#define DEFAULT_NUM_SUBWINDOWS 128 +#define PAMU_PCR_OFFSET 0xc10 +#define PAMU_PCR_PE 0x40000000 + +struct pamu_addr_tbl { + phys_addr_t start_addr[10]; + phys_addr_t end_addr[10]; + phys_size_t size[10]; +}; + +struct paace { + /* PAACE Offset 0x00 */ + uint32_t wbah; /* only valid for Primary PAACE */ + uint32_t addr_bitfields; /* See P/S PAACE_AF_* */ + + /* PAACE Offset 0x08 */ + /* Interpretation of first 32 bits dependent on DD above */ + union { + struct { + /* Destination ID, see PAACE_DID_* defines */ + uint8_t did; + /* Partition ID */ + uint8_t pid; + /* Snoop ID */ + uint8_t snpid; + /* coherency_required : 1 reserved : 7 */ + uint8_t coherency_required; /* See PAACE_DA_* */ + } to_host; + struct { + /* Destination ID, see PAACE_DID_* defines */ + uint8_t did; + uint8_t reserved1; + uint16_t reserved2; + } to_io; + } domain_attr; + + /* Implementation attributes + window count + address & operation + * translation modes + */ + uint32_t impl_attr; /* See PAACE_IA_* */ + + /* PAACE Offset 0x10 */ + /* Translated window base address */ + uint32_t twbah; + uint32_t win_bitfields; /* See PAACE_WIN_* */ + + /* PAACE Offset 0x18 */ + /* first secondary paace entry */ + uint32_t fspi; /* only valid for Primary PAACE */ + union { + struct { + uint8_t ioea; + uint8_t moea; + uint8_t ioeb; + uint8_t moeb; + } immed_ot; + struct { + uint16_t reserved; + uint16_t omi; + } index_ot; + } op_encode; + + /* PAACE Offset 0x20 */ + uint32_t reserved1[2]; /* not currently implemented */ + + /* PAACE Offset 0x28 */ + uint32_t reserved2[2]; /* not currently implemented */ + + /* PAACE Offset 0x30 */ + uint32_t reserved3[2]; /* not currently implemented */ + + /* PAACE Offset 0x38 */ + uint32_t reserved4[2]; /* not currently implemented */ + +}; + +int pamu_init(void); +void pamu_enable(void); +void pamu_disable(void); +int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn); +int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s); + +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 101b8db..bc7e5f8 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1933,7 +1933,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) u8 res24[64]; u32 pblsr; /* Preboot loader status */ u32 pamubypenr; /* PAMU bypass enable */ -#define FSL_CORENET_PAMU_BYPASS 0xffff0000 u32 dmacr1; /* DMA control */ u8 res25[4]; u32 gensr1; /* General status */ @@ -2771,6 +2770,21 @@ typedef struct ccsr_pme { u8 res4[0x400]; } ccsr_pme_t; +struct ccsr_pamu { + u32 ppbah; + u32 ppbal; + u32 pplah; + u32 pplal; + u32 spbah; + u32 spbal; + u32 splah; + u32 splal; + u32 obah; + u32 obal; + u32 olah; + u32 olal; +}; + #ifdef CONFIG_SYS_FSL_RAID_ENGINE struct ccsr_raide { u8 res0[0x543]; @@ -2851,6 +2865,7 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 +#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 @@ -3064,6 +3079,8 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) #define CONFIG_SYS_FSL_SRIO_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) +#define CONFIG_SYS_PAMU_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET) #define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b553e3c..b8c0c0a 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -12,6 +12,9 @@ #include "jr.h" #include "jobdesc.h" #include "desc_constr.h" +#ifdef CONFIG_FSL_CORENET +#include <asm/fsl_pamu.h> +#endif #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) @@ -530,18 +533,38 @@ int sec_init(void) uint32_t mcr = sec_in32(&sec->mcfgr); int ret = 0; +#ifdef CONFIG_FSL_CORENET + uint32_t liodnr; + uint32_t liodn_ns; + uint32_t liodn_s; +#endif + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); #ifdef CONFIG_PHYS_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif sec_out32(&sec->mcfgr, mcr); +#ifdef CONFIG_FSL_CORENET + liodnr = sec_in32(&sec->jrliodnr[0].ls); + liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT; + liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; +#endif + ret = jr_init(); if (ret < 0) { printf("SEC initialization failed\n"); return -1; } +#ifdef CONFIG_FSL_CORENET + ret = sec_config_pamu_table(liodn_ns, liodn_s); + if (ret < 0) + return -1; + + pamu_enable(); +#endif + if (get_rng_vid() >= 4) { if (rng_init() < 0) { printf("RNG instantiation failed\n"); -- 1.8.1.4

1 0

[U-Boot] [PATCH] ARM: uniphier: move UMC register macros to umc-regs.h
by Masahiro Yamada 17 Jan '16

17 Jan '16

The umc-proxstream2.c defiens the same macros as in umc-regs.h. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/mach-uniphier/dram/umc-proxstream2.c | 49 +-------------------------- arch/arm/mach-uniphier/dram/umc-regs.h | 26 ++++++++++++++ 2 files changed, 27 insertions(+), 48 deletions(-) diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index 63a84e6..bb7acde 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -16,54 +16,7 @@ #include "../init.h" #include "../soc-info.h" #include "ddrmphy-regs.h" - -/* UM registers */ -#define UMC_MBUS0 0x00080004 -#define UMC_MBUS1 0x00081004 -#define UMC_MBUS2 0x00082004 -#define UMC_MBUS3 0x00083004 - -/* UD registers */ -#define UMC_BITPERPIXELMODE_D0 0x010 -#define UMC_PAIR1DOFF_D0 0x054 - -/* DC registers */ -#define UMC_INITSET 0x014 -#define UMC_INITSTAT 0x018 -#define UMC_CMDCTLA 0x000 -#define UMC_CMDCTLB 0x004 -#define UMC_SPCCTLA 0x030 -#define UMC_SPCCTLB 0x034 -#define UMC_SPCSETB 0x03c -#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ -#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ -#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ -#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ -#define UMC_ACSSETA 0x060 -#define UMC_FLOWCTLA 0x400 -#define UMC_FLOWCTLB 0x404 -#define UMC_FLOWCTLC 0x408 -#define UMC_FLOWCTLG 0x508 -#define UMC_FLOWCTLOB0 0x520 -#define UMC_FLOWCTLOB1 0x524 -#define UMC_RDATACTL_D0 0x600 -#define UMC_RDATACTL_RADLTY_SHIFT 4 -#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) -#define UMC_RDATACTL_RAD2LTY_SHIFT 8 -#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) -#define UMC_WDATACTL_D0 0x604 -#define UMC_RDATACTL_D1 0x608 -#define UMC_WDATACTL_D1 0x60c -#define UMC_DATASET 0x610 -#define UMC_RESPCTL 0x624 -#define UMC_DCCGCTL 0x720 -#define UMC_ERRMASKA 0x958 -#define UMC_ERRMASKB 0x95c -#define UMC_BSICMAPSET 0x988 -#define UMC_DIOCTLA 0xc00 -#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ -#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ -#define UMC_DFICUPDCTLA 0xc20 +#include "umc-regs.h" enum dram_freq { FREQ_1866M, diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h index 6159281..a6957a4 100644 --- a/arch/arm/mach-uniphier/dram/umc-regs.h +++ b/arch/arm/mach-uniphier/dram/umc-regs.h @@ -69,6 +69,10 @@ #define UMC_SPCCTLB 0x00000034 #define UMC_SPCSETA 0x00000038 #define UMC_SPCSETB 0x0000003C +#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ +#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ +#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ +#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ #define UMC_SPCSETC 0x00000040 #define UMC_SPCSETD 0x00000044 #define UMC_SPCSTATA 0x00000050 @@ -79,17 +83,39 @@ #define UMC_FLOWCTLB 0x00000404 #define UMC_FLOWCTLC 0x00000408 #define UMC_FLOWCTLG 0x00000508 +#define UMC_FLOWCTLOB0 0x00000520 +#define UMC_FLOWCTLOB1 0x00000524 #define UMC_RDATACTL_D0 0x00000600 +#define UMC_RDATACTL_RADLTY_SHIFT 4 +#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) +#define UMC_RDATACTL_RAD2LTY_SHIFT 8 +#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) #define UMC_WDATACTL_D0 0x00000604 #define UMC_RDATACTL_D1 0x00000608 #define UMC_WDATACTL_D1 0x0000060C #define UMC_DATASET 0x00000610 +#define UMC_RESPCTL 0x00000624 #define UMC_DCCGCTL 0x00000720 #define UMC_DICGCTLA 0x00000724 #define UMC_DICGCTLB 0x00000728 +#define UMC_ERRMASKA 0x00000958 +#define UMC_ERRMASKB 0x0000095c +#define UMC_BSICMAPSET 0x00000988 #define UMC_DIOCTLA 0x00000C00 +#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ +#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ #define UMC_DFICUPDCTLA 0x00000C20 +/* UM registers */ +#define UMC_MBUS0 0x00080004 +#define UMC_MBUS1 0x00081004 +#define UMC_MBUS2 0x00082004 +#define UMC_MBUS3 0x00083004 + +/* UD registers */ +#define UMC_BITPERPIXELMODE_D0 0x010 +#define UMC_PAIR1DOFF_D0 0x054 + #ifndef __ASSEMBLY__ #include <linux/types.h> -- 1.9.1

1 0

[U-Boot] [GIT PULL] u-boot-mips/master
by Daniel Schwierzeck 17 Jan '16

17 Jan '16

Hi Tom, please pull the first bunch of MIPS updates. There is a possible merge conflict in dts/Makefile due to my patch [1] in this PR and Thomas' patch [2] waiting in u-boot-fdt tree. [1] http://patchwork.ozlabs.org/patch/566695/ [2] http://patchwork.ozlabs.org/patch/563669/ The following changes since commit 782acf7b52db6bec1a796773e3033b4afcd6c9e2: Merge git://git.denx.de/u-boot-rockchip (2016-01-15 08:11:15 -0500) are available in the git repository at: git://git.denx.de/u-boot-mips.git master for you to fetch changes up to 0e0efb40b874633360967f532eb1ed59ad02adbe: MIPS: implement bit manipulating I/O accessors (2016-01-16 21:06:46 +0100) ---------------------------------------------------------------- Daniel Schwierzeck (16): MIPS: fix annotation of _start and relocate_code MIPS: create .text sub-sections for assembler functions MIPS: do not build position-independent executables for SPL MIPS: add initial infrastructure for device-tree files MIPS: Kconfig: refactor machine setup MIPS: au1x00: move SoC header files to arch/mips/mach-au1x00/include/mach/ MIPS: Kconfig: optimize gcc -march and -mtune setup MIPS: malta: do not pull in target header files in config.h MIPS: malta: fix IO accessor call MIPS: vct: fix I/O accessor calls MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT net: pcnet: refactor mapping of virtual addresses to physical ones MIPS: sync I/O related header files with linux-4.4 MIPS: sync processor and register definitions with linux-4.4 MIPS: fix SPDX license identifier in remaining arch header files MIPS: implement bit manipulating I/O accessors Purna Chandra Mandal (1): MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO. arch/Kconfig | 1 + arch/mips/Kconfig | 33 ++- arch/mips/Makefile | 23 +- arch/mips/config.mk | 25 +- arch/mips/cpu/start.S | 12 +- arch/mips/dts/.gitignore | 1 + arch/mips/dts/Makefile | 16 ++ arch/mips/dts/include/dt-bindings | 1 + arch/mips/dts/skeleton.dtsi | 23 ++ arch/mips/include/asm/addrspace.h | 10 +- arch/mips/include/asm/asm.h | 126 +++++----- arch/mips/include/asm/bitops.h | 6 +- arch/mips/include/asm/byteorder.h | 6 +- arch/mips/include/asm/cache.h | 14 +- arch/mips/include/asm/cachectl.h | 6 +- arch/mips/include/asm/cacheops.h | 6 +- arch/mips/include/asm/const.h | 31 +++ arch/mips/include/asm/cpu-features.h | 30 +++ arch/mips/include/asm/gpio.h | 1 + arch/mips/include/asm/io.h | 814 +++++++++++++++++++++++++++++++++---------------------------- arch/mips/include/asm/isadep.h | 6 +- arch/mips/include/asm/mach-generic/cpu-feature-overrides.h | 11 + arch/mips/include/asm/mach-generic/ioremap.h | 32 +++ arch/mips/include/asm/mach-generic/mangle-port.h | 50 ++++ arch/mips/include/asm/mach-generic/spaces.h | 102 ++++++++ arch/mips/include/asm/mipsregs.h | 1495 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------------------------- arch/mips/include/asm/pgtable-bits.h | 283 ++++++++++++++++++++++ arch/mips/include/asm/posix_types.h | 9 +- arch/mips/include/asm/processor.h | 6 +- arch/mips/include/asm/ptrace.h | 99 +++++--- arch/mips/include/asm/reboot.h | 6 +- arch/mips/include/asm/reg.h | 6 +- arch/mips/include/asm/regdef.h | 12 +- arch/mips/include/asm/sgidefs.h | 6 +- arch/mips/include/asm/string.h | 6 +- arch/mips/include/asm/system.h | 6 +- arch/mips/include/asm/types.h | 6 +- arch/mips/include/asm/unaligned.h | 6 +- arch/mips/lib/cache.c | 4 +- arch/mips/lib/cache_init.S | 16 +- arch/mips/mach-au1x00/au1x00_eth.c | 2 +- arch/mips/mach-au1x00/au1x00_serial.c | 2 +- arch/mips/mach-au1x00/au1x00_usb_ohci.c | 2 +- arch/mips/mach-au1x00/config.mk | 8 - arch/mips/{include/asm => mach-au1x00/include/mach}/au1x00.h | 0 board/dbau1x00/dbau1x00.c | 2 +- board/dbau1x00/lowlevel_init.S | 2 +- board/imgtec/malta/malta.c | 3 +- board/micronas/vct/vct.h | 6 +- board/pb1x00/lowlevel_init.S | 2 +- board/pb1x00/pb1x00.c | 2 +- drivers/net/pcnet.c | 28 ++- dts/Makefile | 2 +- include/configs/malta.h | 9 +- 54 files changed, 2396 insertions(+), 1026 deletions(-) create mode 100644 arch/mips/dts/.gitignore create mode 100644 arch/mips/dts/Makefile create mode 120000 arch/mips/dts/include/dt-bindings create mode 100644 arch/mips/dts/skeleton.dtsi create mode 100644 arch/mips/include/asm/const.h create mode 100644 arch/mips/include/asm/cpu-features.h create mode 100644 arch/mips/include/asm/gpio.h create mode 100644 arch/mips/include/asm/mach-generic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-generic/ioremap.h create mode 100644 arch/mips/include/asm/mach-generic/mangle-port.h create mode 100644 arch/mips/include/asm/mach-generic/spaces.h create mode 100644 arch/mips/include/asm/pgtable-bits.h delete mode 100644 arch/mips/mach-au1x00/config.mk rename arch/mips/{include/asm => mach-au1x00/include/mach}/au1x00.h (100%)

2 1

[U-Boot] [PATCH v3 0/8] dm: x86: Convert ICH driver fully to driver model PCI API
by Simon Glass 17 Jan '16

17 Jan '16

This is a small series to move the ICH driver over to use the driver model PCI API. It involves creating PCH drivers which the ICH driver can use to find out its base address. At present irq-router is the 'PCH' node in most device tree files. This is not really correct since the router is just one of the functions of the PCH. Another is the SPI bus. So this series also moves irq-router down a level. This still works with the same irq-router driver, since it just searches for the first compatible node it can find. A driver-model-compatible irq-router driver should be written but that is left for later. This series unfortunately needs testing on each board since each has a separate change. I have tested minnowmax and chromebook_link so far. Changes in v3: - Add a PCH method to enable/disable SPI flash protection - Drop the pch_init() call - Add a new patch to separate out the read/write trace from normal debugging - Use the set_spi_protect() PCH method Changes in v2: - Add more detail to the function comment - Rename the last parameter to 'addr' - Update the comment to explain usable of this function - Update the commit message and header file comments - Use an enum for the PCH version - Replace SBASE with SPI base - Add a TODO to check if the init() method can be removed later - Rename the PCH functions - Update the get_version() handle to use an enum - Add a function to obtain the SPI base address - Add enums for BIOS_CTRL register and bits - Rename the PCH functions - Update the get_version() handle to use an enum - Adjust code for earlier commits - Move the SPI base code into the PCH drivers Simon Glass (8): dm: pci: Move pci_bus_to_hose() to compatibility dm: pci: Add a function to write a BAR dm: pci: Avoid using pci_bus_to_hose() in the uclass dm: Expand the uclass for Platform Controller Hubs (PCH) dm: x86: Add a driver for Intel PCH7 dm: x86: Add a driver for Intel PCH9 spi: ich: Separate out the read/write trace from normal debugging dm: x86: spi: Convert ICH SPI driver to driver model PCI API arch/x86/cpu/coreboot/pci.c | 3 +- arch/x86/cpu/irq.c | 7 +- arch/x86/cpu/ivybridge/bd82x6x.c | 45 +++++++- arch/x86/dts/bayleybay.dts | 160 +++++++++++++------------- arch/x86/dts/broadwell_som-6896.dts | 23 ++-- arch/x86/dts/chromebook_link.dts | 5 +- arch/x86/dts/chromebox_panther.dts | 33 +++--- arch/x86/dts/crownbay.dts | 150 ++++++++++++------------ arch/x86/dts/galileo.dts | 98 ++++++++-------- arch/x86/dts/minnowmax.dts | 158 ++++++++++++++------------ arch/x86/dts/qemu-x86_i440fx.dts | 26 +++-- arch/x86/dts/qemu-x86_q35.dts | 38 ++++--- arch/x86/lib/Makefile | 1 - drivers/Makefile | 1 + drivers/pch/Makefile | 7 ++ {arch/x86/lib => drivers/pch}/pch-uclass.c | 32 ++++++ drivers/pch/pch7.c | 59 ++++++++++ drivers/pch/pch9.c | 43 +++++++ drivers/pci/pci-uclass.c | 24 ++-- drivers/pci/pci_auto.c | 14 +-- drivers/pci/pci_compat.c | 15 +++ drivers/pci/pci_internal.h | 12 ++ drivers/spi/ich.c | 176 +++++++++-------------------- include/pch.h | 83 ++++++++++++++ include/pci.h | 17 ++- 25 files changed, 754 insertions(+), 476 deletions(-) create mode 100644 drivers/pch/Makefile rename {arch/x86/lib => drivers/pch}/pch-uclass.c (50%) create mode 100644 drivers/pch/pch7.c create mode 100644 drivers/pch/pch9.c create mode 100644 include/pch.h -- 2.6.0.rc2.230.g3dd15c0

2 17

[U-Boot] [PATCH v7 7/7] mips: ath79: add AP143 reference board
by Wills Wang 16 Jan '16

16 Jan '16

Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v7: - Use KSEG1 address for debug port in ap143 Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/mips/dts/Makefile | 1 + arch/mips/dts/ap143.dts | 43 ++++++++++++++++++++ arch/mips/dts/qca953x.dtsi | 72 ++++++++++++++++++++++++++++++++++ arch/mips/mach-ath79/Kconfig | 5 +++ board/ath79/ap143/Kconfig | 9 +++++ board/ath79/ap143/MAINTAINERS | 6 +++ board/ath79/ap143/Makefile | 5 +++ board/ath79/ap143/ap143.c | 63 ++++++++++++++++++++++++++++++ configs/ap143_defconfig | 43 ++++++++++++++++++++ include/configs/ap143.h | 91 +++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 338 insertions(+) create mode 100644 arch/mips/dts/ap143.dts create mode 100644 arch/mips/dts/qca953x.dtsi create mode 100644 board/ath79/ap143/Kconfig create mode 100644 board/ath79/ap143/MAINTAINERS create mode 100644 board/ath79/ap143/Makefile create mode 100644 board/ath79/ap143/ap143.c create mode 100644 configs/ap143_defconfig create mode 100644 include/configs/ap143.h diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 3fd49eb..7da06c5 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -3,6 +3,7 @@ # dtb-$(CONFIG_BOARD_AP121) += ap121.dtb +dtb-$(CONFIG_BOARD_AP143) += ap143.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/ap143.dts b/arch/mips/dts/ap143.dts new file mode 100644 index 0000000..f53207e --- /dev/null +++ b/arch/mips/dts/ap143.dts @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "qca953x.dtsi" + +/ { + model = "AP143 Reference Board"; + compatible = "qca,ap143", "qca,qca953x"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&xtal { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + memory-map = <0x9f000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi new file mode 100644 index 0000000..8487fc9 --- /dev/null +++ b/arch/mips/dts/qca953x.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "skeleton.dtsi" + +/ { + compatible = "qca,qca953x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@18020000 { + compatible = "ns16550"; + reg = <0x18020000 0x20>; + reg-shift = <2>; + clock-frequency = <25000000>; + + status = "disabled"; + }; + }; + + spi0: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index 0fcd96a..f61efd2 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -34,8 +34,13 @@ config BOARD_AP121 bool "AP121 Reference Board" select SOC_AR933X +config BOARD_AP143 + bool "AP143 Reference Board" + select SOC_QCA953X + endchoice source "board/ath79/ap121/Kconfig" +source "board/ath79/ap143/Kconfig" endmenu diff --git a/board/ath79/ap143/Kconfig b/board/ath79/ap143/Kconfig new file mode 100644 index 0000000..118b9b5 --- /dev/null +++ b/board/ath79/ap143/Kconfig @@ -0,0 +1,9 @@ +if BOARD_AP143 + +config SYS_BOARD + default "ap143" + +config SYS_CONFIG_NAME + default "ap143" + +endif diff --git a/board/ath79/ap143/MAINTAINERS b/board/ath79/ap143/MAINTAINERS new file mode 100644 index 0000000..d373cf8 --- /dev/null +++ b/board/ath79/ap143/MAINTAINERS @@ -0,0 +1,6 @@ +AP143 BOARD +M: Wills Wang <wills.wang(a)live.com> +S: Maintained +F: board/ath79/ap143/ +F: include/configs/ap143.h +F: configs/ap143_defconfig diff --git a/board/ath79/ap143/Makefile b/board/ath79/ap143/Makefile new file mode 100644 index 0000000..00f7837 --- /dev/null +++ b/board/ath79/ap143/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ap143.o diff --git a/board/ath79/ap143/ap143.c b/board/ath79/ap143/ap143.c new file mode 100644 index 0000000..3be86e6 --- /dev/null +++ b/board/ath79/ap143/ap143.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/ddr.h> +#include <debug_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* + * GPIO9 as input, GPIO10 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val |= QCA953X_GPIO(9); + val &= ~QCA953X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable GPIO10 as UART0_SOUT + */ + val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2); + val &= ~QCA953X_GPIO_OUT_MUX_MASK(16); + val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16; + writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2); + + /* + * Enable GPIO9 as UART0_SIN + */ + val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0); + val &= ~QCA953X_GPIO_OUT_MUX_MASK(8); + val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8; + writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0); + + /* + * Enable GPIO10 output + */ + val = readl(regs + AR71XX_GPIO_REG_OUT); + val |= QCA953X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OUT); + +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + ddr_init(); + return 0; +} +#endif diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig new file mode 100644 index 0000000..ed7e09d --- /dev/null +++ b/configs/ap143_defconfig @@ -0,0 +1,43 @@ +CONFIG_MIPS=y +CONFIG_ARCH_ATH79=y +CONFIG_BOARD_AP143=y +CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_SYS_NS16550=y +CONFIG_DM_SERIAL=y +CONFIG_ATH79_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="ap143" +CONFIG_SYS_PROMPT="ap143 # " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_NS16550=y +CONFIG_DEBUG_UART_BASE=0xb8020000 +CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEBUG_UART_SHIFT=2 diff --git a/include/configs/ap143.h b/include/configs/ap143.h new file mode 100644 index 0000000..6940551 --- /dev/null +++ b/include/configs/ap143.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_TEXT_BASE 0x9f000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 325 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 0x8000 +#define CONFIG_SYS_ICACHE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_CLK 25000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock2 " \ + "rootfstype=squashfs" +#define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f300000" +#define CONFIG_LZMA +#define CONFIG_OF_LIBFDT + +#define MTDIDS_DEFAULT "nor0=spi-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ + "256k(u-boot),64k(u-boot-env)," \ + "2752k(rootfs),896k(uImage)," \ + "64k(NVRAM),64k(ART)" + +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 + +/* + * Command + */ +#define CONFIG_CMD_MTDPARTS + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x83f00000 +#define CONFIG_CMD_MEMTEST + +#endif /* __CONFIG_H */ -- 1.9.1

2 1

[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 16 Jan '16

16 Jan '16

The following changes since commit 782acf7b52db6bec1a796773e3033b4afcd6c9e2: Merge git://git.denx.de/u-boot-rockchip (2016-01-15 08:11:15 -0500) are available in the git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to 217db227df40e29d6a4726272303499a7cd7b904: socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories (2016-01-16 07:07:23 +0100) ---------------------------------------------------------------- Dalon Westergreen (1): socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories Dinh Nguyen (1): arm: socfpga: set the fpga global bit to disable HPS to FPGA signals Marek Vasut (1): ddr: altera: Init the rule ID in debug code arch/arm/mach-socfpga/qts-filter.sh | 76 +++++++++++++++++++++++++++++++++++++++++++++------------------------------- drivers/ddr/altera/sdram.c | 1 + drivers/fpga/socfpga.c | 2 +- 3 files changed, 47 insertions(+), 32 deletions(-)

2 1

[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 16 Jan '16

16 Jan '16

The following changes since commit 782acf7b52db6bec1a796773e3033b4afcd6c9e2: Merge git://git.denx.de/u-boot-rockchip (2016-01-15 08:11:15 -0500) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to 447b9cdf2c4d8d7c6cb1ff64426c1dfaf7396f93: common: usb: fix checking condition (2016-01-16 07:06:55 +0100) ---------------------------------------------------------------- Peng Fan (1): common: usb: fix checking condition Sanchayan Maity (2): usb: host: ehci-vf: Remove hardcoded USB host client configuration usb: host: ehci-vf: Implement board_usb_phy_mode weak function Ye.Li (1): usb:ci_udc: Remove ULPI setting for i.MX OTG controller common/usb.c | 2 +- drivers/usb/gadget/ci_udc.c | 14 +++----------- drivers/usb/host/ehci-vf.c | 15 ++++++++++----- 3 files changed, 14 insertions(+), 17 deletions(-)

2 1

[U-Boot] [PATCH v6 00/10] add support for atheros ath79 based SOCs
by Wills Wang 16 Jan '16

16 Jan '16

These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip. Changes in v6: - Remove useless "else" - Move ar933x as separate patch - Add get_bootstrap in reset.c - Use map_physmem instead of KSEG1ADDR - Add arch_cpu_init for detect SOC type for early - Define magic value in ddr.c - Remove wait loop in putc and getc - Use map_physmem instead of KSEG1ADDR - Add rrw_delay in ath79_spi_priv for more accurate timing - Remove ath79_spi_delay - Calculate delay in ath79_spi_set_speed - Convert SZ_XXX into hex in ap121.h - Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h - Add board_early_init_f for DDR and pin initialization - Select UART and SPI in ap121_defconfig - Add support for qca953x Changes in v5: - Add independent Kconfig - Use SRAM for initial stack - Move DDR initialization into board_early_init_f - Convert DDR tap tunning code to C - Save SOC's version into arch_global_data - remove ar933x_serial_platdata - Import document "qca,ar9330-uart.txt" from kernel - Add support for debug UART - remove ar933x_spi_platdata - Import document "spi-ath79.txt" from kernel - Add delay for bitbang operation - Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk - Remove useless README file - Remove useless checkboard function Changes in v4: - Use global_data to save CPU/DDR/AHB clock - Use arch_global_data to save SOC's type, revison and id - Auto calculate baudrate for serial driver - Move pinctrl code in serial driver into arch/mips/mach-ath79 - Use get_serial_clock to serial clock source - Use get_bus_freq instead of hardcode in SPI driver Changes in v3: - Move SoC specific header files into arch/mips/mach-ath79/include/mach - Optimize assembly code - Same code style convertion - Convert serial driver to driver model - Same code style convertion - Convert spi driver to driver model - Same code style convertion - Add support for device tree Changes in v2: - Move all SoC specific header files into arch/mips/include/asm/arch-ath79 - Check SOC type and extract common code into arch/mips/mach-ath79 - Move serial driver code into drivers/serial - Add a compatible spi driver - Add a reference board implemention Wills Wang (10): mips: implement to access the KSEG0/1 memory range in map_physmem mips: add base support for QCA/Atheros ath79 SOCs mips: ath79: add support for AR933x SOCs mips: ath79: add support for QCA953x SOCs mips: ath79: add serial driver for ar933x SOC ns16550: add support for mips ns16550: map register base address for debug UART mips: ath79: add spi driver mips: ath79: add AP121 reference board mips: ath79: add AP143 reference board arch/mips/Kconfig | 6 + arch/mips/Makefile | 1 + arch/mips/dts/Makefile | 3 +- arch/mips/dts/ap121.dts | 37 + arch/mips/dts/ap143.dts | 37 + arch/mips/dts/ar933x.dtsi | 64 ++ arch/mips/dts/qca953x.dtsi | 66 ++ arch/mips/include/asm/global_data.h | 6 + arch/mips/include/asm/io.h | 6 +- arch/mips/mach-ath79/Kconfig | 46 + arch/mips/mach-ath79/Makefile | 10 + arch/mips/mach-ath79/ar933x/Makefile | 7 + arch/mips/mach-ath79/ar933x/clk.c | 90 ++ arch/mips/mach-ath79/ar933x/ddr.c | 317 ++++++ arch/mips/mach-ath79/ar933x/lowlevel_init.S | 280 +++++ arch/mips/mach-ath79/cpu.c | 204 ++++ arch/mips/mach-ath79/dram.c | 17 + arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1187 ++++++++++++++++++++ arch/mips/mach-ath79/include/mach/ath79.h | 143 +++ arch/mips/mach-ath79/include/mach/ddr.h | 14 + arch/mips/mach-ath79/include/mach/reset.h | 15 + arch/mips/mach-ath79/qca953x/Makefile | 7 + arch/mips/mach-ath79/qca953x/clk.c | 112 ++ arch/mips/mach-ath79/qca953x/ddr.c | 463 ++++++++ arch/mips/mach-ath79/qca953x/lowlevel_init.S | 186 +++ arch/mips/mach-ath79/reset.c | 75 ++ board/ath79/ap121/Kconfig | 9 + board/ath79/ap121/MAINTAINERS | 6 + board/ath79/ap121/Makefile | 5 + board/ath79/ap121/ap121.c | 48 + board/ath79/ap143/Kconfig | 9 + board/ath79/ap143/MAINTAINERS | 6 + board/ath79/ap143/Makefile | 5 + board/ath79/ap143/ap143.c | 64 ++ configs/ap121_defconfig | 42 + configs/ap143_defconfig | 43 + .../serial/qca,ar9330-uart.txt | 24 + doc/device-tree-bindings/spi/spi-ath79.txt | 19 + drivers/serial/Kconfig | 17 + drivers/serial/Makefile | 1 + drivers/serial/ns16550.c | 30 +- drivers/serial/serial_ar933x.c | 264 +++++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 230 ++++ include/configs/ap121.h | 81 ++ include/configs/ap143.h | 86 ++ 47 files changed, 4384 insertions(+), 13 deletions(-) create mode 100644 arch/mips/dts/ap121.dts create mode 100644 arch/mips/dts/ap143.dts create mode 100644 arch/mips/dts/ar933x.dtsi create mode 100644 arch/mips/dts/qca953x.dtsi create mode 100644 arch/mips/mach-ath79/Kconfig create mode 100644 arch/mips/mach-ath79/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/clk.c create mode 100644 arch/mips/mach-ath79/ar933x/ddr.c create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/cpu.c create mode 100644 arch/mips/mach-ath79/dram.c create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h create mode 100644 arch/mips/mach-ath79/include/mach/reset.h create mode 100644 arch/mips/mach-ath79/qca953x/Makefile create mode 100644 arch/mips/mach-ath79/qca953x/clk.c create mode 100644 arch/mips/mach-ath79/qca953x/ddr.c create mode 100644 arch/mips/mach-ath79/qca953x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/reset.c create mode 100644 board/ath79/ap121/Kconfig create mode 100644 board/ath79/ap121/MAINTAINERS create mode 100644 board/ath79/ap121/Makefile create mode 100644 board/ath79/ap121/ap121.c create mode 100644 board/ath79/ap143/Kconfig create mode 100644 board/ath79/ap143/MAINTAINERS create mode 100644 board/ath79/ap143/Makefile create mode 100644 board/ath79/ap143/ap143.c create mode 100644 configs/ap121_defconfig create mode 100644 configs/ap143_defconfig create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/serial/serial_ar933x.c create mode 100644 drivers/spi/ath79_spi.c create mode 100644 include/configs/ap121.h create mode 100644 include/configs/ap143.h -- 1.9.1

2 5

[U-Boot] [PATCH] drivers: uclass: timer: rename timer_init() to dm_timer_init()
by Mugunthan V N 16 Jan '16

16 Jan '16

Rename timer_init() to dm_timer_init() and remove dm_timer_init() in lib/time.c as * timer_init is called from board_f.c or board_r.c on different architectures which may result causes timer devices to be probed twice. * lib/time.c dm_timer_init() does nothing other than calling timer_init(). Also remove reinitializing of ret in timer_init(). Signed-off-by: Mugunthan V N <mugunthanvnm(a)ti.com> --- Tested this patch on dra74x evm. and pushed a branch [2]. [1] - http://pastebin.ubuntu.com/14524076/ [2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-timer-fix --- drivers/timer/timer-uclass.c | 7 +++++-- include/timer.h | 9 +++++++++ lib/time.c | 8 -------- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index 053411f..83d1a35 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -68,13 +68,16 @@ u64 timer_conv_64(u32 count) return ((u64)gd->timebase_h << 32) | gd->timebase_l; } -int timer_init(void) +int notrace dm_timer_init(void) { const void *blob = gd->fdt_blob; struct udevice *dev = NULL; int node; int ret; + if (gd->timer) + return 0; + /* Check for a chosen timer to be used for tick */ node = fdtdec_get_chosen_node(blob, "tick-timer"); if (node < 0) { @@ -92,7 +95,7 @@ int timer_init(void) */ if (node > 0 && !lists_bind_fdt(gd->dm_root, blob, node, &dev)) { - int ret = device_probe(dev); + ret = device_probe(dev); if (ret) return ret; } diff --git a/include/timer.h b/include/timer.h index 7fee17e..f14725c 100644 --- a/include/timer.h +++ b/include/timer.h @@ -8,6 +8,15 @@ #define _TIMER_H_ /* + * dm_timer_init - initialize a timer for time keeping. On success + * initializes gd->timer so that lib/timer can use it for future + * referrence. + * + * @return - 0 on success or error number + */ +int dm_timer_init(void); + +/* * timer_conv_64 - convert 32-bit counter value to 64-bit * * @count: 32-bit counter value diff --git a/lib/time.c b/lib/time.c index d4060f1..e9f6861 100644 --- a/lib/time.c +++ b/lib/time.c @@ -41,14 +41,6 @@ extern unsigned long __weak timer_read_counter(void); #endif #ifdef CONFIG_TIMER -static int notrace dm_timer_init(void) -{ - if (!gd->timer) - return timer_init(); - - return 0; -} - ulong notrace get_tbclk(void) { int ret; -- 2.7.0.rc3

1 0

[U-Boot] [PATCH v6 06/10] ns16550: add support for mips
by Wills Wang 16 Jan '16

16 Jan '16

MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32" macro, but usually define CONFIG_SYS_BIG_ENDIAN, this patch use readl/writel for register operation in mips when define CONFIG_SYS_NS16550_MEM32. Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None drivers/serial/ns16550.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 3fab3f1..3b24af0 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -64,12 +64,16 @@ static inline void serial_out_shift(void *addr, int shift, int value) { #ifdef CONFIG_SYS_NS16550_PORT_MAPPED outb(value, (ulong)addr); -#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) - out_le32(addr, value); -#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) - out_be32(addr, value); #elif defined(CONFIG_SYS_NS16550_MEM32) +#ifdef CONFIG_MIPS writel(value, addr); +#else +#ifndef CONFIG_SYS_BIG_ENDIAN + out_le32(addr, value); +#else + out_be32(addr, value); +#endif +#endif #elif defined(CONFIG_SYS_BIG_ENDIAN) writeb(value, addr + (1 << shift) - 1); #else @@ -81,12 +85,16 @@ static inline int serial_in_shift(void *addr, int shift) { #ifdef CONFIG_SYS_NS16550_PORT_MAPPED return inb((ulong)addr); -#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) - return in_le32(addr); -#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) - return in_be32(addr); #elif defined(CONFIG_SYS_NS16550_MEM32) +#ifdef CONFIG_MIPS return readl(addr); +#else +#ifndef CONFIG_SYS_BIG_ENDIAN + return in_le32(addr); +#else + return in_be32(addr); +#endif +#endif #elif defined(CONFIG_SYS_BIG_ENDIAN) return readb(addr + (1 << shift) - 1); #else -- 1.9.1

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