September 2015 - U-Boot

[U-Boot] [PATCH 1/3] mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5
by Yangbo Lu 15 Sep '15

15 Sep '15

If adapter card type identification is supported for platform, we would enable dat[4:7] for eMMC4.5 card. Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> --- board/freescale/common/qixis.h | 2 ++ drivers/mmc/fsl_esdhc.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 51ce9c3..450cd0d 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -127,6 +127,8 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/ #define QIXIS_SDCLKIN 0x08 #define QIXIS_SDCLKOUT 0x02 +#define QIXIS_DAT5_6_7 0X02 +#define QIXIS_DAT4 0X01 #endif #endif diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0b37002..639ec02 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -747,6 +747,9 @@ void mmc_adapter_card_type_ident(void) switch (card_id) { case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: + value = QIXIS_READ(brdcfg[5]); + value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); + QIXIS_WRITE(brdcfg[5], value); break; case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: break; -- 2.1.0.27.g96db324

3 4

[U-Boot] [PATCH 1/4] imx: mx7: discard unused global variable
by Peng Fan 15 Sep '15

15 Sep '15

Discard unused global variable. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/armv7/mx7/soc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index 8d50149..af16ba7 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -15,8 +15,6 @@ #include <dm.h> #include <imx_thermal.h> -struct src *src_reg = (struct src *)SRC_BASE_ADDR; - #if defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx7_thermal_plat = { .regs = (void *)ANATOP_BASE_ADDR, -- 1.8.4

3 6

[U-Boot] Trouble configuring DHCP vs. BOOTP
by Michael Binder 15 Sep '15

15 Sep '15

Hi, I am brand new to U-Boot, sorry for what may be basic questions. I am also new to my company - 2 months. I am an experienced embedded C/C++ developer. I have never worked with Android. I have some network experience, like configuring my home system, etc. I have some experience with Linux/Unix, but I am finding out how little I know very quickly. We have a custom board based on Freescale Sabre. Boot log shows these lines at the beginning. U-Boot 2009.08-00698-g76526a0-dirty (Aug 18 2015 - 19:42:57) CPU: Freescale i.MX6 family TO1.2 at 792 MHz Boots up fine normally from flash memory. I can: 1) reflash via FASTBOOT over USB. Need to flash system.img, boot.img and recovery.img individually using: fastboot flash boot C:\Projects\Data\Kernel_Binaries\boot.img fastboot flash boot C:\Projects\Data\Kernel_Binaries\recovery.img fastboot flash boot C:\Projects\Data\Kernel_Binaries\system.img Then reboot manually 2) TFTP from my local PC TFTP server, which is "TFTPd64", if I set a static ipaddr, serverip, netmask, etc. 3) DHCP load from my local PC if I disconnect from the company network and turn on DHCP in the TFTP server. Still need to set serverip. I think TFTPd64 must handle BOOTP. I cannot: 1) get DHCP from company network. Appears BOOTP is used and our network is not configured to use BOOTP and I cannot change that. 2) get the loaded files to run/boot after loading. I am loading uImage. Seems like a partial boot. Something is missing or different. 3) set needed IP addresses using DHCP. 4) Find server without setting serverip manually. What I want to do: 1) Connect Ethernet cable to device. 2) Device cold boots and from U-Boot uses DHCP (not BOOTP) to get network information - good ip, netmask, server ip 3) Device checks server for a new file(s) and loads them if found. Flashes new files to memory, so reboot will be new version. 4) Boots from flash. Old files if no updates found or new files if files are found on server. I want to be able to connect to our customer's network without making them change settings and update the SW or just boot if already updated. Device is on line to report data over the Ethernet, so reflash cannot interfere with that. Any help appreciated. Michael (Mike) Binder | Staff Engineer, R&D 6260 Sequence Drive, San Diego, CA 92121 Phone: 858.263.2356 | Mobile: 858.472.4098 | FAX: 858.875.0603 Accriva is now Representing ITC and Accumetrics [Logo-Accriva] [computericon32]<http://accriva.com/> [envelopeicon32] <mailto:mbinder@accriva.com> [linkedinicon32] <http://www.linkedin.com/company/accriva-diagnostics> [facebookicon32] <https://www.facebook.com/accriva>

1 0

[U-Boot] [PATCH 00/13] Implement fastboot over NAND
by Maxime Ripard 14 Sep '15

14 Sep '15

Hi everyone, Here is the first attempt at getting fastboot flashing functions working on top of a NAND. While the NAND support itself was quite easy to do, the support for the Android sparse images was quite difficult to add, and ended up being a quite huge refactoring of the sparse parse already in tree, that was tied to the MMC layer. This serie has been tested on a CHIP and a Cubietruck, two Allwinner devices, the CHIP for the NAND, and the Cubietruck to test the MMC. Let me know what you think, Maxime Maxime Ripard (13): mtd: uboot: Add meaningful error message sparse: Move main header parsing to a function of its own sparse: Refactor chunk parsing function sparse: Simplify multiple logic sparse: Implement storage abstraction fastboot: Move fastboot response functions to fastboot core fastboot: Implement NAND backend fastboot: nand: Add pre erase and write hooks sparse: Rename the file and header sunxi: Make the fastboot buffer larger sunxi: Add support for android boot image sunxi: A13-Olinuxino: Enable the USB OTG controller sunxi: cubietruck: Enable the USB OTG controller common/Makefile | 7 +- common/aboot.c | 244 --------------------------- common/fb_mmc.c | 82 ++++++---- common/fb_nand.c | 219 +++++++++++++++++++++++++ common/sparse.c | 354 ++++++++++++++++++++++++++++++++++++++++ configs/A13-OLinuXino_defconfig | 2 + configs/Cubietruck_defconfig | 5 + drivers/mtd/mtd_uboot.c | 2 +- drivers/usb/gadget/f_fastboot.c | 39 ++++- include/configs/sunxi-common.h | 3 +- include/fastboot.h | 22 +++ include/fb_nand.h | 10 ++ include/{aboot.h => sparse.h} | 15 +- 13 files changed, 714 insertions(+), 290 deletions(-) delete mode 100644 common/aboot.c create mode 100644 common/fb_nand.c create mode 100644 common/sparse.c create mode 100644 include/fastboot.h create mode 100644 include/fb_nand.h rename include/{aboot.h => sparse.h} (61%) -- 2.5.0

8 64

[U-Boot] arm: mvebu: u-boot does not start on db-88f6820-gp
by Stefan Eichenberger 14 Sep '15

14 Sep '15

Hi Stefan, I have a problem with u-boot compiled from master and the db-88f6820-gp evaluation board from Marvell. The problem is the reconfiguration of the base register address (SOC_REGS_PHY_BASE) under u-boot on A38x. Some functions (e.g. mvebu_soc_family) try to access the new SOC_REGS_PHY_BASE address before this address is reconfigured which leads to an exception. U-Boot won't start in this case. I then set the SOC_REGS_PHY_BASE to 0xd0000000 (same as under SPL) and u-boot starts successfully. This was only to verify that this is the problem, with the modification I can't start Linux because Linux expects that the addresses are reconfigured. I have to mention, I try to start from a SD Card. So I have changed the boot configuration of the board with a pull down on DPR6. This is the output of the SPL when I don't add the modification, u-boot won't start: U-Boot SPL 2015.10-rc2-00308-g6679da9-dirty (Sep 04 2015 - 16:01:24) High speed PHY - Version: 2.0 Initialize DB-GP board topology Detected Device ID 6828 Lane 5 detection: USB3.0 Host Port 1 Lane 1 detection: SATA0 Lane 2 detection: SATA1 board SerDes lanes topology details: | Lane # | Speed | Type | -------------------------------- | 0 | 5 | PCIe0 | | 1 | 3 | SATA0 | | 2 | 3 | SATA1 | | 3 | 3 | SATA3 | | 4 | 3 | SATA2 | | 5 | 5 | USB3 HOST1 | -------------------------------- PCIe, Idx 0: detected no link High speed PHY - Ended Successfully DDR3 Training Sequence - Ver TIP-1.29.0 DDR3 Training Sequence - Switching XBAR Window to FastPath Window DDR3 Training Sequence - Ended Successfully >>spl:board_init_r() spl_init() boot device - 1 spl: mmc boot mode: raw read sector 1140, count=1 spl: payload image: U-Bo load addr: 0x7fffc0 size: 336772 read 292 sectors to 7fffc0 Jumping to U-Boot loaded - jumping to U-Boot...image entry point: 0x800000 After I changed SOC_REGS_PHY_BASE u-boot starts correctly: U-Boot 2015.10-rc2-00308-g6679da9-dirty (Sep 04 2015 - 16:19:09 +0200) SoC: MV88F6828-A0 I2C: ready SPI: ready DRAM: 2 GiB (ECC not enabled) MMC: mv_sdh: 0 SF: Detected M25P128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB Board: Marvell DB-88F6820-GP SCSI: MVEBU SATA INIT SATA link 0 timeout. SATA link 1 timeout. AHCI 0001.0000 32 slots 2 ports 6 Gbps 0x3 impl SATA mode flags: 64bit ncq led only pmp fbss pio slum part sxs Net: neta0, neta1 Hit any key to stop autoboot: 0 So it seems that SOC_REGS_PHY_BASE should somehow be changeable during runtime but I don't think this works with the current design. Do you have an idea how this could be fixed? Thanks and best regards, Stefan

2 7

[U-Boot] mx7dsabresd board does not reset
by Fabio Estevam 14 Sep '15

14 Sep '15

Hi Adrian, I noticed that the reset command fails on mx7sabresd board: => reset resetting ... (it gets stuck here). Could you please look at it? Regards, Fabio Estevam

2 2

[U-Boot] [PATCH 1/4] sf: params: Add IS25LP032 part support
by Jagan Teki 14 Sep '15

14 Sep '15

Added support for IS25LP032 flash part. Signed-off-by: Jagan Teki <jteki(a)openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Cc: Michal Simek <michal.simek(a)xilinx.com> --- drivers/mtd/spi/sf_params.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 4a4a3af..184ba9c 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -34,6 +34,9 @@ const struct spi_flash_params spi_flash_params_table[] = { {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, #endif +#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ + {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_NORM, 0}, +#endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0}, {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0}, -- 1.9.1

2 7

[U-Boot] [PATCH] sf: probe: Add support to set Quad enable bit for ISSI
by Siva Durga Prasad Paladugu 14 Sep '15

14 Sep '15

Added support to set the quad enable bit in status register for ISSI parts. Tis would be same as for Macronix parts. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- - This patch is based on u-boot-spi/master --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/sf_probe.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 9c95d56..a995d9b 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -60,6 +60,7 @@ enum { #define SPI_FLASH_CFI_MFR_STMICRO 0x20 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 #define SPI_FLASH_CFI_MFR_WINBOND 0xef +#define SPI_FLASH_CFI_MFR_ISSI 0x9d /* Erase commands */ #define CMD_ERASE_4K 0x20 diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 954376d..b4f8a33 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -32,7 +32,7 @@ static u8 spi_read_cmds_array[] = { CMD_READ_QUAD_IO_FAST, }; -#ifdef CONFIG_SPI_FLASH_MACRONIX +#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI) static int spi_flash_set_qeb_mxic(struct spi_flash *flash) { u8 qeb_status; @@ -79,8 +79,9 @@ static int spi_flash_set_qeb_winspan(struct spi_flash *flash) static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) { switch (idcode0) { -#ifdef CONFIG_SPI_FLASH_MACRONIX +#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI) case SPI_FLASH_CFI_MFR_MACRONIX: + case SPI_FLASH_CFI_MFR_ISSI: return spi_flash_set_qeb_mxic(flash); #endif #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) -- 1.7.1

1 0

[U-Boot] [PATCH 1/4 v2] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600
by Stefan Roese 14 Sep '15

14 Sep '15

This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength. To enable SW BCH4, you need to specify this in your config header: #define CONFIG_NAND_ECC_BCH #define CONFIG_BCH And use the command "nandecc bch4" to select this ECC scheme upon runtime. Tested on SPEAr600 x600 board. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Scott Wood <scottwood(a)freescale.com> Acked-by: Viresh Kumar <viresh.kumar(a)linaro.org> --- v2: - Removed err = 0 initialization as suggested by Viresh - Completed the commit text - Added Viresh's Acked-by drivers/mtd/nand/fsmc_nand.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 567eff0..0976a67 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -13,6 +13,7 @@ #include <asm/io.h> #include <linux/bitops.h> #include <linux/err.h> +#include <linux/mtd/nand_bch.h> #include <linux/mtd/nand_ecc.h> #include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> @@ -390,6 +391,45 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, return 0; } +#ifndef CONFIG_SPL_BUILD +/* + * fsmc_nand_switch_ecc - switch the ECC operation between different engines + * + * @eccstrength - the number of bits that could be corrected + * (1 - HW, 4 - SW BCH4) + */ +int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength) +{ + struct nand_chip *nand; + struct mtd_info *mtd; + int err; + + mtd = &nand_info[nand_curr_device]; + nand = mtd->priv; + + /* Setup the ecc configurations again */ + if (eccstrength == 1) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.bytes = 3; + nand->ecc.strength = 1; + nand->ecc.layout = &fsmc_ecc1_layout; + nand->ecc.correct = nand_correct_data; + } else { + nand->ecc.mode = NAND_ECC_SOFT_BCH; + nand->ecc.calculate = nand_bch_calculate_ecc; + nand->ecc.correct = nand_bch_correct_data; + nand->ecc.bytes = 7; + nand->ecc.strength = 4; + nand->ecc.layout = NULL; + } + + /* Update NAND handling after ECC mode switch */ + err = nand_scan_tail(mtd); + + return err; +} +#endif /* CONFIG_SPL_BUILD */ + int fsmc_nand_init(struct nand_chip *nand) { static int chip_nr; -- 2.5.1

3 10

[U-Boot] [PATCH 3/3] powerpc/t1040qds: enable peripheral clock for eSDHC
by Yangbo Lu 14 Sep '15

14 Sep '15

Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> --- include/configs/T1040QDS.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8353b8f..92bc295 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -593,6 +593,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC -- 2.1.0.27.g96db324

1 0