September 2015 - U-Boot

[U-Boot] Please pull u-boot-x86
by Simon Glass 17 Sep '15

17 Sep '15

Hi Tom, Here are the rest of the quark networkng support, plus fixes for Linux booting, etc. The following changes since commit fa43ce842c3026c2abf19d4234d02cd4c62eeec0: Merge git://git.denx.de/u-boot-fdt (2015-09-16 09:53:37 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git for you to fetch changes up to c6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef: x86: quark: Configure MTRR to enable cache (2015-09-16 19:53:53 -0600) ---------------------------------------------------------------- Bin Meng (13): dm: pci: Add an inline API to test if a device is on a PCI bus net: designware: Add support to PCI designware devices x86: Convert to use driver model eth on quark/galileo x86: quark: Add PCIe/USB static register programming after memory init x86: galileo: Enable random mac address for Quark x86: quark: Add clrbits, setbits, clrsetbits macros for message port access x86: quark: Convert to use clrbits, setbits, clrsetbits macros x86: quark: Lock HMBOUND register before jumping to kernel x86: quark: Initialize thermal sensor properly x86: galileo: Add PCIe root port IRQ routing x86: doc: Document some porting hints about Intel Quark x86: doc: Add DMI to the TODO list x86: quark: Configure MTRR to enable cache arch/x86/cpu/quark/dram.c | 10 ++++++ arch/x86/cpu/quark/quark.c | 249 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------------------- arch/x86/dts/galileo.dts | 12 +++++++ arch/x86/include/asm/arch-quark/msg_port.h | 31 ++++++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 81 +++++++++++++++++++++++++++++++++++++++++ configs/galileo_defconfig | 3 +- doc/README.x86 | 26 ++++++++++++++ drivers/net/designware.c | 42 ++++++++++++++++++++++ drivers/pci/pci-uclass.c | 4 +-- include/configs/galileo.h | 1 + include/dm/device.h | 11 ++++++ 11 files changed, 400 insertions(+), 70 deletions(-) Regards, Simon

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[U-Boot] Please pull u-boot-dm
by Simon Glass 17 Sep '15

17 Sep '15

Hi Tom, The following changes since commit fa43ce842c3026c2abf19d4234d02cd4c62eeec0: Merge git://git.denx.de/u-boot-fdt (2015-09-16 09:53:37 -0400) are available in the git repository at: git://git.denx.de/u-boot-dm.git for you to fetch changes up to 6aa8179f818f04a16e15bc589004de68a6d99a23: dts: do not cut down pinctrl-0 and pinctrl-names for SPL full-pinctrl (2015-09-16 19:45:12 -0600) ---------------------------------------------------------------- Masahiro Yamada (1): dts: do not cut down pinctrl-0 and pinctrl-names for SPL full-pinctrl dts/Kconfig | 1 + 1 file changed, 1 insertion(+) Regards, Simon

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[U-Boot] [PATCH] x86: quark: Configure MTRR to enable cache
by Bin Meng 17 Sep '15

17 Sep '15

Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs are accessed indirectly via the message port and not the traditional MSR mechanism. Only UC, WT and WB cache types are supported. We configure all the fixed range MTRRs with common values (VGA RAM as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as WB, which significantly improves the boot time performance. With this commit, it takes only 2 seconds for U-Boot to boot to shell on Intel Galileo board. Previously it took about 6 seconds. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/quark/dram.c | 10 ++++++ arch/x86/cpu/quark/quark.c | 57 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 44 +++++++++++++++++++++++++ 3 files changed, 111 insertions(+) diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 9cac846..1b89376 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -7,8 +7,10 @@ #include <common.h> #include <errno.h> #include <fdtdec.h> +#include <asm/mtrr.h> #include <asm/post.h> #include <asm/arch/mrc.h> +#include <asm/arch/msg_port.h> #include <asm/arch/quark.h> DECLARE_GLOBAL_DATA_PTR; @@ -111,6 +113,14 @@ int dram_init(void) gd->ram_size = mrc_params.mem_size; post_code(POST_DRAM); + /* variable range MTRR#2: RAM area */ + disable_caches(); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM), + 0 | MTRR_TYPE_WRBACK); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM), + (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID); + enable_caches(); + return 0; } diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 8b78a86..77d644a 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -8,6 +8,7 @@ #include <mmc.h> #include <asm/io.h> #include <asm/irq.h> +#include <asm/mtrr.h> #include <asm/pci.h> #include <asm/post.h> #include <asm/processor.h> @@ -34,6 +35,55 @@ static void unprotect_spi_flash(void) qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); } +static void quark_setup_mtrr(void) +{ + u32 base, mask; + int i; + + disable_caches(); + + /* mark the VGA RAM area as uncacheable */ + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000, + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000, + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); + + /* mark other fixed range areas as cacheable */ + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++) + msg_port_write(MSG_PORT_HOST_BRIDGE, i, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + + /* variable range MTRR#0: ROM area */ + mask = ~(CONFIG_SYS_MONITOR_LEN - 1); + base = CONFIG_SYS_TEXT_BASE & mask; + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM), + base | MTRR_TYPE_WRBACK); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM), + mask | MTRR_PHYS_MASK_VALID); + + /* variable range MTRR#1: eSRAM area */ + mask = ~(ESRAM_SIZE - 1); + base = CONFIG_ESRAM_BASE & mask; + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM), + base | MTRR_TYPE_WRBACK); + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM), + mask | MTRR_PHYS_MASK_VALID); + + /* enable both variable and fixed range MTRRs */ + msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE, + MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN); + + enable_caches(); +} + static void quark_setup_bars(void) { /* GPIO - D31:F0:R44h */ @@ -191,6 +241,13 @@ int arch_cpu_init(void) return ret; /* + * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs + * are accessed indirectly via the message port and not the traditional + * MSR mechanism. Only UC, WT and WB cache types are supported. + */ + quark_setup_mtrr(); + + /* * Quark SoC has some non-standard BARs (excluding PCI standard BARs) * which need be initialized with suggested values */ diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index f6009f6..7a864c7 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -37,6 +37,50 @@ /* Extended Configuration Space */ #define HEC_REG 0x09 +/* MTRR Registers */ +#define MTRR_CAP 0x40 +#define MTRR_DEF_TYPE 0x41 + +#define MTRR_FIX_64K_00000 0x42 +#define MTRR_FIX_64K_40000 0x43 +#define MTRR_FIX_16K_80000 0x44 +#define MTRR_FIX_16K_90000 0x45 +#define MTRR_FIX_16K_A0000 0x46 +#define MTRR_FIX_16K_B0000 0x47 +#define MTRR_FIX_4K_C0000 0x48 +#define MTRR_FIX_4K_C4000 0x49 +#define MTRR_FIX_4K_C8000 0x4a +#define MTRR_FIX_4K_CC000 0x4b +#define MTRR_FIX_4K_D0000 0x4c +#define MTRR_FIX_4K_D4000 0x4d +#define MTRR_FIX_4K_D8000 0x4e +#define MTRR_FIX_4K_DC000 0x4f +#define MTRR_FIX_4K_E0000 0x50 +#define MTRR_FIX_4K_E4000 0x51 +#define MTRR_FIX_4K_E8000 0x52 +#define MTRR_FIX_4K_EC000 0x53 +#define MTRR_FIX_4K_F0000 0x54 +#define MTRR_FIX_4K_F4000 0x55 +#define MTRR_FIX_4K_F8000 0x56 +#define MTRR_FIX_4K_FC000 0x57 + +#define MTRR_SMRR_PHYBASE 0x58 +#define MTRR_SMRR_PHYMASK 0x59 + +#define MTRR_VAR_PHYBASE(n) (0x5a + 2 * (n)) +#define MTRR_VAR_PHYMASK(n) (0x5b + 2 * (n)) + +#ifndef __ASSEMBLY__ + +/* variable range MTRR usage */ +enum { + MTRR_VAR_ROM, + MTRR_VAR_ESRAM, + MTRR_VAR_RAM +}; + +#endif /* __ASSEMBLY__ */ + /* Port 0x04: Remote Management Unit Message Port Registers */ /* ACPI PBLK Base Address Register */ -- 1.8.2.1

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[U-Boot] [PATCH v2 0/8] x86: Support booting Linux kernel on Intel Galileo
by Bin Meng 17 Sep '15

17 Sep '15

Currently U-Boot works great on Intel Galileo board, but it still has some issues when booting a Linux kernel. The issues are mainly with Isolated Memory Region (IMR) and thermal sensor support in the Linux kernel for Intel Quark SoC. For example, kernel just hangs after kernel IMR driver is probed. It turns out U-Boot still misses some key register programming. Add those register initializtion so that Linux kernel can boot succesfully. Tested on Intel Galileo board, with an AHCI mini-PCIe card with an SSD attached (to test PCI IRQ behind the root port), as well as a micro-SD card, a USB flash disk and ethernet under Linux. Note the mainline Linux designware Ethernet driver uses an API dmi_get_system_info() to determine the PHY address. Since U-Boot currently does not support the DMI, to test the Ethernet under Linux we need patch the kernel driver, but in the long term, we should add DMI support in U-Boot. Add a TODO in README.x86 for now. Changes in v2: - Change all macros to use a single msg_port_generic_clrsetbits - Update per review comments from Simon Bin Meng (8): x86: galileo: Enable random mac address for Quark x86: quark: Add clrbits, setbits, clrsetbits macros for message port access x86: quark: Convert to use clrbits, setbits, clrsetbits macros x86: quark: Lock HMBOUND register before jumping to kernel x86: quark: Initialize thermal sensor properly x86: galileo: Add PCIe root port IRQ routing x86: doc: Document some porting hints about Intel Quark x86: doc: Add DMI to the TODO list arch/x86/cpu/quark/quark.c | 115 ++++++++++++++++------------- arch/x86/dts/galileo.dts | 12 +++ arch/x86/include/asm/arch-quark/msg_port.h | 31 ++++++++ arch/x86/include/asm/arch-quark/quark.h | 15 ++++ configs/galileo_defconfig | 1 + doc/README.x86 | 26 +++++++ 6 files changed, 149 insertions(+), 51 deletions(-) -- 1.8.2.1

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[U-Boot] [PATCH v5 1/4] dm: pci: Add an inline API to test if a device is on a PCI bus
by Bin Meng 17 Sep '15

17 Sep '15

Introduce device_is_on_pci_bus() which can be utilized by driver to test if a device is on a PCI bus. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v5: - Move the inline API from include/pci.h to include/dm/device.h to resolve the cyclic dependency Changes in v3: None Changes in v2: - New patch to add an inline API to test if a device is on a PCI bus drivers/pci/pci-uclass.c | 4 ++-- include/dm/device.h | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index ea70853..0756bbe 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -238,7 +238,7 @@ int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, { struct udevice *bus; - for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;) + for (bus = dev; device_is_on_pci_bus(bus);) bus = bus->parent; return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size); } @@ -303,7 +303,7 @@ int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, { struct udevice *bus; - for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;) + for (bus = dev; device_is_on_pci_bus(bus);) bus = bus->parent; return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep, size); diff --git a/include/dm/device.h b/include/dm/device.h index a239be6..8519612 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -485,6 +485,17 @@ bool device_is_last_sibling(struct udevice *dev); */ int device_set_name(struct udevice *dev, const char *name); +/** + * device_is_on_pci_bus - Test if a device is on a PCI bus + * + * @dev: device to test + * @return: true if it is on a PCI bus, false otherwise + */ +static inline bool device_is_on_pci_bus(struct udevice *dev) +{ + return device_get_uclass_id(dev->parent) == UCLASS_PCI; +} + /* device resource management */ typedef void (*dr_release_t)(struct udevice *dev, void *res); typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data); -- 1.8.2.1

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[U-Boot] [PATCH 1/3] cgtqmx6eval: Fit into a single line
by Otavio Salvador 17 Sep '15

17 Sep '15

The printf can be put in a single line of code, so make it simpler Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- board/congatec/cgtqmx6eval/cgtqmx6eval.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 9aff08d..770bc50 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -225,8 +225,7 @@ int power_init_board(void) for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) { if (!strcmp(mipi_levels[i].name, lv_mipi)) { - printf("set MIPI level %s\n", - mipi_levels[i].name); + printf("set MIPI level %s\n", mipi_levels[i].name); ret = pmic_reg_write(p, PFUZE100_VGEN4VOL, mipi_levels[i].value); if (ret) -- 2.5.2

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[U-Boot] [PATCH v5 0/9] Add support for ThunderX 88xx SoC family
by Sergey Temerkhanov 17 Sep '15

17 Sep '15

This patch series adds support for Cavium ThunderX 88xx SoC family (http://cavium.com/ThunderX_ARM_Processors.html) This is the version 5 of the series I posted at http://lists.denx.de/pipermail/u-boot/2015-August/224324.html http://lists.denx.de/pipermail/u-boot/2015-August/223618.html Changes in v5: - Allow setting of different memory attributes in the memory map - Added OF control support - Added FDT for ThunderX 88xx series - Added CONFIG_OF_CONTROL support - Changed memory attributes - Moved dram_init() from a separate file to thunderx.c Changes in v4: - Use ALIGN macro for address alignment - Document FW calls - Fixed build warnings - Moved to DM_SERIAL - Moved CONFIG_SYS_PROMPT to configs/thunderx_88xx_defconfig - Added proper DM_SERIAL definitions Changes in v3: - Reduced code duplication - Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS - Moved 'reset_sctrl' call to the 'reset' label - Rebased to the actual upstream tree - Documented newly added config options - Fixed clobber lists (thanks to Corey) - Added __used keyword - Fixed formatting - Added MAINTAINERS - Moved command definitions to defconfig Changes in v2: - Changed code licensing - Completed the patchset Sergey Temerkhanov (9): armv8: Add read_mpidr() function armv8: New MMU setup code allowing to use 48+ bits PA/VA armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure armv8: Add psci.h from the Linux kernel arm: serial: Add ability to use pre-initialized UARTs armv8: cavium: Add the device tree for ThunderX armv8: cavium: Add ThunderX 88xx board definition armv8: cavium: Add an implementation of ATF calling functions armv8: cavium: Get DRAM size from ATF arch/arm/Kconfig | 5 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/cache_v8.c | 79 +++++++ arch/arm/cpu/armv8/fwcall.c | 75 +++++++ arch/arm/cpu/armv8/start.S | 36 ++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/thunderx-88xx.dts | 27 +++ arch/arm/dts/thunderx-88xx.dtsi | 363 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/armv8/mmu.h | 82 +++++++- arch/arm/include/asm/global_data.h | 1 + arch/arm/include/asm/system.h | 39 ++++ arch/arm/lib/board.c | 6 +- board/cavium/thunderx/Kconfig | 19 ++ board/cavium/thunderx/MAINTAINERS | 6 + board/cavium/thunderx/Makefile | 8 + board/cavium/thunderx/atf.c | 312 +++++++++++++++++++++++++++ board/cavium/thunderx/thunderx.c | 102 +++++++++ configs/thunderx_88xx_defconfig | 29 +++ doc/README.arm64 | 35 ++- drivers/serial/serial_pl01x.c | 13 +- include/cavium/atf.h | 22 ++ include/cavium/atf_part.h | 26 +++ include/cavium/thunderx_svc.h | 67 ++++++ include/configs/thunderx_88xx.h | 148 +++++++++++++ include/dm/platform_data/serial_pl01x.h | 6 + include/linux/psci.h | 90 ++++++++ 26 files changed, 1578 insertions(+), 20 deletions(-) create mode 100644 arch/arm/cpu/armv8/fwcall.c create mode 100644 arch/arm/dts/thunderx-88xx.dts create mode 100644 arch/arm/dts/thunderx-88xx.dtsi create mode 100644 board/cavium/thunderx/Kconfig create mode 100644 board/cavium/thunderx/MAINTAINERS create mode 100644 board/cavium/thunderx/Makefile create mode 100644 board/cavium/thunderx/atf.c create mode 100644 board/cavium/thunderx/thunderx.c create mode 100644 configs/thunderx_88xx_defconfig create mode 100644 include/cavium/atf.h create mode 100644 include/cavium/atf_part.h create mode 100644 include/cavium/thunderx_svc.h create mode 100644 include/configs/thunderx_88xx.h create mode 100644 include/linux/psci.h -- 2.2.0

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[U-Boot] [PATCH v2 0/3] sunxi: support FEL-provided environment vars and "fel" boot target
by Bernhard Nortmann 17 Sep '15

17 Sep '15

This patch series builds upon http://lists.denx.de/pipermail/u-boot/2015-September/226515.html http://lists.denx.de/pipermail/u-boot/2015-September/226688.html v2 combines the previous submissions, and adds some suggested fixes/changes. The sunxi-tool side of things is discussed here: https://www.mail-archive.com/linux-sunxi@googlegroups.com/msg13071.html * Hans de Goede already pointed out that it might be preferable to make use of the spl_boot_device() function even from the main (non-SPL) U-Boot binary (e.g. for the "NAND" case). Currently this function is only available with CONFIG_SPL_BUILD set, and implemented in arch/arm/cpu/armv7/sunxi/board.c Would it be safe to enable it for non-SPL builds and use something like "(spl_boot_device == BOOT_DEVICE_BOARD)" for misc_init_r()? * Side note: the sunxi spl_boot_device() will probably require some future refinement anyway, to account for the 'oddball' A80. That SoC requires the SPL at a different address (0x10000 instead of 0x0). * The test for FEL boot mode ("eGON.BT0") in spl_boot_device() explicitly uses the "io" function readl() to access the signature. Is there a specific reason for this? Marex pointed out (on IRC) that the SRAM might as well be read directly. For now, I have followed the existing code, and used readl() and readb() to work with the SPL header information. * The check_signature() function somewhat duplicates very similar code from arch/arm/include/asm/io.h. That particular piece of code depends on the presence of a "__mem_pci" symbol. However, it seems 'generic' enough - so it may be worth to factor out and reuse it? Regards, B. Nortmann Changes in v2: - Rename field to fel_script_address, discard fel_data_size - Clearing header fields is no longer needed, as mksunxiboot.c zeroes entire image first - renamed fel_data_addr to fel_script_addr, discarded fel_data_size - make sure that FEL-related environment vars are always cleared first - support minimum and maximum SPL (header) version, more verbose error messages - renamed fel_data_addr to fel_scriptaddr - combined both tests into one as suggested by Hans de Goede Bernhard Nortmann (3): sunxi: (mksunxiboot) signature to indicate "sunxi" SPL variant sunxi: retrieve FEL-provided values to environment variables sunxi: add "fel" boot target board/sunxi/board.c | 56 ++++++++++++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 11 +++++++++ tools/mksunxiboot.c | 23 ++++++++++++++++- 3 files changed, 89 insertions(+), 1 deletion(-) -- 2.4.6

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[U-Boot] Trying to load old kernel with new u-boot
by DaveKucharczyk 17 Sep '15

17 Sep '15

One of our mx51 based boards doesn't seem to like 2.6.35 kernel with 2014.07 u-boot. We've ported our boards for the new kernel and new u-boot, but we need the old kernel to also work with new u-boot. So here's what happens... U-Boot 2014.07-svn83200 (Sep 15 2015 - 15:57:02) CPU: Freescale i.MX51 rev3.0 at 800 MHz I2C: ready DRAM: 512 MiB Last reset reason:POR, (1) Boot Device: MMC MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Hit any key to stop autoboot: 0 MMC read: dev # 0, block # 2048, count 6144 ... 6144 blocks read: OK ## Booting kernel from Legacy Image at 92000000 ... Image Name: Linux-2.6.35.3-1129-g691c08a+ Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 2873388 Bytes = 2.7 MiB Load Address: 90008000 Entry Point: 90008000 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ... ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ console [ttymxc1] enabled, bootconsole disabled blah blah boot continues as normal... Looks like new u-boot passes something wrong to the kernel or doesn't pass something we need. Seems like the first half of the kernel output timing is wrong. I tried different bauds to no avail. On a working board we see early on... entering mx51_clocks_init turning off all clocks external_low_reference = 00008000 external_high_reference = 01588800 ckih2_reference = 01770000 oscillator_reference = 016e3600 entering clk_tree_init clk_tree_init for mx51 returned from clk_tree_init setting uart_main_clk to pll3_sw_clk MXC_CCM_CSCDR1 is 00c30458 MXC_Early serial console at MMIO 0x73fc0000 (options '115200') bootconsole [ttymxc1] enabled And then later... console [ttymxc1] enabled, bootconsole disabled Looks like the early console is not working. I'll have to debug this tomorrow, but if anyone has suggestions that would be great. -- View this message in context: http://u-boot.10912.n7.nabble.com/Trying-to-load-old-kernel-with-new-u-boot… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PATCH] arm: mvebu: timer.c: Explicitly move "init_done" var to data section
by Stefan Roese 17 Sep '15

17 Sep '15

As reported by Simon Guinot, commit ade741b3 "arm: mvebu: Call timer_init early before PHY and DDR init" breaks Kirkwood platforms. As the static variable "init_done" is not available at that early boot time. This patch moves it to explicitly to the data section, making it available at that time. Signed-off-by: Stefan Roese <sr(a)denx.de> Reported-by: Simon Guinot <simon.guinot(a)sequanux.org> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- arch/arm/mach-mvebu/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c index c516c41..5449a89 100644 --- a/arch/arm/mach-mvebu/timer.c +++ b/arch/arm/mach-mvebu/timer.c @@ -41,7 +41,7 @@ #define timestamp gd->arch.tbl #define lastdec gd->arch.lastinc -static int init_done; +static int init_done __attribute__((section(".data"))) = 0; /* Timer reload and current value registers */ struct kwtmr_val { -- 2.5.1

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